Trabajo De Diseño02.docx

TRABAJO DE DISEÑO DIGITAL Pregunta N01: Diseñar el siguiente problema, ingresar 3 números y que los ordene de menor a mayor: ALGORITMO: Input A Input B Input C If(A>B){ AUX=A A=B B=AUX} If(B>C){ AUX=C C=B B=AUX} If(A>B){ AUX=A A=B B=AUX} Output A Output B Output C

RUTA DE DATOS:

RUTA DE DATOS EN VHDL: Optimizando la palabra de comando:

Código: Library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_unsigned.all; Entity menoramayor is Port( input: in std_logic_vector(7 downto 0); la,lb,lc,l1,l2,clk: in std_logic; sel: in std_logic_vector(1 downto 0); z: out std_logic_vector(1 downto 0); output: out std_logic_vector(7 downto 0)); End menoramayor; Architecture solucion of menoramayor is signal A,B,C: std_logic_vector(7 downto 0); Begin Process(clk) Begin if rising_edge(clk) then if la='1' then A<=input; elsif lb='1' then B<=input; elsif lc='1' then C<=input; elsif l1='1' then B<=A; A<=B; elsif l2='1' then C<=B; B<=C; end if; end if; end process; z(0) <='1' when A>B else '0'; z(1) <='1' when B>C else '0'; output <= (others=>'Z') when sel="00" else A when sel="01" else B when sel="10" else C; End solucion;

UNIDAD DE CONTROL:

UNIDAD DE CONTROL IMPLEMENTADO EN VHDL: Library IEEE; Use IEEE.std_logic_1164.all; Use IEEE.std_logic_arith.all; Use IEEE.std_logic_unsigned.all; Entity controlmenoramayor is Port( start, clk: in std_logic; la,lb,lc,l1,l2: out std_logic; sel: out std_logic_vector(1 downto 0); z: in std_logic_vector(1 downto 0)); end controlmenoramayor; Architecture solucion of controlmenoramayor is Type estado is (S0,S1,S2,S3,S4,S5,S6,S7,S8,SC); signal ES,EP: estado; Begin Process(clk) Begin if rising_edge(clk) then EP <= ES; end if; end process;

Process(EP) Begin ES <= EP; case EP is when S0 => la<='0';lb<='0';lc<='0';l1<='0';l2<='0';sel<="00"; if start='1' then ES <= S1; else ES <= S0; end if; when S1 => la<='1';lb<='0';lc<='0';l1<='0';l2<='0';sel<="00"; ES <= S2; when S2 => la<='0';lb<='1';lc<='0';l1<='0';l2<='0';sel<="00"; ES <= S3; when S3 => la<='0';lb<='0';lc<='1';l1<='0';l2<='0';sel<="00"; ES <= SC; when S4 => la<='0';lb<='0';lc<='0';l1<='1';l2<='0';sel<="00"; ES <= SC; when S5 => la<='0';lb<='0';lc<='0';l1<='0';l2<='1';sel<="00"; ES <= SC; when S6 => la<='0';lb<='0';lc<='0';l1<='0';l2<='0';sel<="01"; es <= S7; when S7 => la<='0';lb<='0';lc<='0';l1<='0';l2<='0';sel<="10"; es <= S8; when S8 => la<='0';lb<='0';lc<='0';l1<='0';l2<='0';sel<="11"; es <= S0; when SC => la<='0';lb<='0';lc<='0';l1<='0';l2<='0';sel<="00"; if z(0)='1' then ES <= S4; elsif z="10" then ES <= S5; elsif z="00" then ES <= S6; end if; end case; end process; end solucion; INTEGRACION DE LA UNIDAD DE CONTROL Y LA RUTA DE DATOS: Library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_unsigned.all; Entity problema_01 is port( start,clk: in std_logic; input: in std_logic_vector(7 downto 0); output: out std_logic_vector(7 downto 0)); end problema_01; Architecture solucion of problema_01 is component controlmenoramayor Port( start, clk: in std_logic; la,lb,lc,l1,l2: out std_logic; sel: out std_logic_vector(1 downto 0); z: in std_logic_vector(1 downto 0)); end component;

component menoramayor Port( input: in std_logic_vector(7 downto 0); la,lb,lc,l1,l2,clk: in std_logic; sel: in std_logic_vector(1 downto 0); z: out std_logic_vector(1 downto 0); output: out std_logic_vector(7 downto 0)); end component; signal la,lb,lc,l1,l2: std_logic; signal sel: std_logic_vector(1 downto 0); signal z: std_logic_vector(1 downto 0); Begin U1: controlmenoramayor Port map (start,clk,la,lb,lc,l1,l2,sel,z); U2: menoramayor Port map (input,la,lb,lc,l1,l2,clk,sel,z,output); end solucion; SIMULACIONES:

Pregunta N02: Diseñar el siguiente problema, ingresar N números cada vez que se presione load y que me muestre la cantidad de números ingresados luego de ingresar el cero:

ALGORITMO: Input N Cuenta = 0 While(N≠0){ Input N Cuenta=Cuenta+1} Output C

RUTA DE DATOS:

RUTA DE DATOS EN VHDL: Optimizando la palabra de comando:

Código: Library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_unsigned.all; Entity cantnum is Port( input: in std_logic_vector(7 downto 0); l1,l2,ena,clk: in std_logic; z: out std_logic; output: out std_logic_vector(7 downto 0)); End cantnum; Architecture solucion of cantnum is signal N,cuenta: std_logic_vector(7 downto 0); Begin Process(clk) Begin if rising_edge(clk) then if l1='1' then N<=input; cuenta<=(others=>'0'); elsif l2='1' then N<=input; cuenta<=cuenta+1; end if; end if; end process; z <='1' when N=0 else '0'; output <= cuenta when ena='1' else (others=>'Z'); End solucion; UNIDAD DE CONTROL:

UNIDAD DE CONTROL IMPLEMENTADO EN VHDL: Library IEEE; Use IEEE.std_logic_1164.all; Use IEEE.std_logic_arith.all; Use IEEE.std_logic_unsigned.all; Entity controlcantnum is Port( load, clk: in std_logic; l1,l2,ena: out std_logic; z: in std_logic); end controlcantnum; Architecture solucion of controlcantnum is Type estado is (S0,S1,S2,S3,SC); signal ES,EP: estado; Begin Process(clk) Begin if rising_edge(clk) then EP <= ES; end if; end process; Process(EP) Begin ES <= EP; case EP is when S0 => l1<='0';l2<='0';ena<='0'; if load='1' then ES <= S1; else ES <= S0; end if; when S1 => l1<='1';l2<='0';ena<='0'; ES <= SC; when S2 => l1<='0';l2<='1';ena<='0'; ES <= SC; when S3 => l1<='0';l2<='0';ena<='1'; ES <= S3; when SC => l1<='0';l2<='0';ena<='0'; if z='1' then ES <= S3; elsif load='1' then ES <= S2; end if; end case; end process; end solucion;

INTEGRACION DE LA UNIDAD DE CONTROL Y LA RUTA DE DATOS:

Library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_unsigned.all; Entity problema_02 is port( load,clk: in std_logic; input: in std_logic_vector(7 downto 0); output: out std_logic_vector(7 downto 0)); end problema_02; Architecture solucion of problema_02 is component controlcantnum Port( load, clk: in std_logic; l1,l2,ena: out std_logic; z: in std_logic); end component; component cantnum Port( input: in std_logic_vector(7 downto 0); l1,l2,ena,clk: in std_logic; z: out std_logic; output: out std_logic_vector(7 downto 0)); end component; signal l1,l2,ena,z: std_logic; Begin U1: controlcantnum Port map (load,clk,l1,l2,ena,z); U2: cantnum Port map (input,l1,l2,ena,clk,z,output); end solucion;

SIMULACIONES: