Best Project Vlsi Details Anna University

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FPGA IMPLEMENTATION OF ONE BIT DELTA SIGMA CONTROL SYSTEM PROCESSOR

GUIDED BY: Mrs. J. KAMALA Lecturer, Department of Electronics and Communication Engineering, College of Engineering - Guindy, Anna University, Chennai-600 025

PRESENTED BY: Mr. S. MOHAN 200731631 M.E – Applied Electronics, College of Engineering Guindy, Anna University, Chennai-600 025

ABSTRACT A Novel Delta Sigma (ΔΣ) Control System Processor is a novel architecture for digital control system. Control laws can be efficiently implemented with one-bit signals at both the input and output of the system. Delta Sigma modulation is used to shape either analog or multi-bit digital signals into 1-bit format at very high sampling frequencies. This 1-bit format contains all the useful information of the input. Thus making it possible to perform digital signal processing directly applied to any physical device. The delta sigma control system processor utilizes 1-bit processing with the direct benefit of making multi-bit multiplication operations redundant. A simple conditional- negate-and-add (CNA) unit is used for operations in control law implementations. One bit architecture for processor results in less hardware and very high sampling rate. The proposed architecture provides higher efficiency in terms of performance, low cost, and high sampling rates compared to other digital controllers.

IEEE(VLSI) PAPER MAR 2008 Xiaofeng Wu, Vassilios A. Chouliaras, Jose Luis Nunez-Yanez, and Roger M. Goodall, ―A Novel Control System Processor and Its VLSI Implementation,‖ IEEE Trans.VLSI, Vol. 16, No. 3, Mar. 2008, pp. 217–228 REFERENCES REFERENCES [1] W. Forsythe and R. M. Goodall, Digital Control: Fundamentals, Theory and Practice. New York, USA: McGraw-Hill, 1991. [2] R. Middleton and G. Goodwin, Digital Control and Estimation—A Unified Approach. Englewood Cliffs, NJ: Prentice-Hall, 1990. [3] P. Paraskevopoulos, Digital Control Systems. Englewood Cliffs, NJ: Prentice-Hall, 1996. [4] J. C. Candy, Oversampling Delta-Sigma Data Converters: Theory, Design, and Simulation. Piscataway, NJ: IEEE, 1992. [5] S. R. Norsworthy, R. Schreier, and G. C. Themes, Delta-Sigma Data Converters. Piscataway, NJ: IEEE, 1997. [6] V. Peluso and M. Steyaert, Design of Low-Voltage Low-Power CMOS Delta-Sigma A/D Converters. Norwell, MA: Kluwer, 1999. [7] S. Kershaw, S. Summerfield, M. Sandler, and M. Anderson, ―Realisation and implementation of a sigma-delta bitstream FIR filter,‖ IEE Proc.-Circuits Devices Syst., vol. 143, no. 5, pp. 267–273, Oct. 1996. [8] S. Summerfield, S. Kershaw, and M. Sandler, ―Sigma-Delta bitstream filtering in VLSI,‖ in Proc. 37th Midw. Symp. Circuits Syst., Aug. 1994, pp. 1200–1203. [9] P. W. Wong and R. M. Gray, ―FIR filters with sigma-delta modulation encoding,‖ IEEE Trans. Circuits Syst., vol. 38, no. 6, pp. 979–990, Jun. 1990. [10] S. Kershaw, ―Sigma-delta bitstream processors analysis and design,‖ Ph.D. dissertation, Dept. Electron. Elect. Eng., Kings College, Wilkes Barre, PA, Jul. 1996. [11] D. Johns and D. Lewis, ―IIR filtering on delta-sigma modulated signals,‖ Electron. Lett., vol. 27, no. 4, pp. 307–308, Feb. 1991. [12] D. A. Johns and D. M. Lewis, ―Design and analysis of delta-sigma based IIR filters,‖ IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 40, no. 4, pp. 233–240, Apr. 1993. [13] J. Angus and S. Draper, ―An improved method for directly filtering audio signals,‖ presented at the AES 104th Convention, Amsterdam, The Netherlands, 1998.

[14] J. Angus, ―One bit digital filtering,‖ in IEE Colloq. Dig. 1998/252, Apr. 1998, pp. 811–816. [15] X. Wu and R. Goodall, ―One-bit processing for real-time control,‖ presented at the Euro. Control Conf., Cambridge, U.K., 2003. [16] X. Wu and R. M. Goodall, ―FPGA-based control system processing withmodulation,‖ in Proc. 5th World Congr. Intell. Control Autom., 2004, pp. 10–14. [17] V. Kathail, M. Schlansker, and B. R. Rau, ―HPL-PD architecture specification: Version 1.0,‖ HP Labs, Palo Alto, CA, Tech. Rep. HPL-93 80R1. [18] R. Goodall, ―Perspectives on processing for real-time control,‖ Ann. Rev. Control, vol. 25, pp. 123–131, 2001. [19] G. Ritchie, ―Higher order interpolation analog to digital converters,‖ Ph.D. dissertation, Univ. Pennsylvania, Philadelphia, PA, 1977. [20] S. H. Ardalan and J. J. Paulos, ―An analysis of nonlinear behavior in delta-sigma modulators,‖ IEEE Trans. Circuits Syst., vol. 34, no. 6, pp. 593–604, Jun. 1987. [21] B. Liu, ―Effect of finite wordlength on the accuracy of digital filters—A review,‖ IEEE Trans. Circuit Theory, vol. CT-18, pp. 670–677, 1971. [22] R. Agarwal and C. Burrus, ―New recursive digital filter structures having very low sensitivity and roundoff noise,‖ IEEE Trans. Circuits Syst., vol. CAS-22, no. 12, pp. 921–927, Dec. 1975. [23] G. Orlandi and G. Martinelli, ―Low sensitivity recursive digital filters obtained via the delay replacement,‖ IEEE Trans. Circuits Syst., vol. CAS-31, no. 7, pp. 654–657, Jul. 1984. [24] R. Goodall and B. Donoghue, ―Very high sampling rate digital filters using the operator,‖ Proc. Inst. Elect. Eng. G, vol. 140, no. 3, pp. 199–206, 1993. [25] R. A. C. Parra, ―On the design and implementation of a control system processor,‖ Ph.D. dissertation, Dept. Electron. Elect. Eng., Loughbor ough Univ., Loughborough, U.K., 2001. [26] IEEE Standard for Binary Floating-Point Arithmetic, 754-1985. [27] R. Goodall and D. Brown, ―High speed digital controllers using an 8-bit microprocessor,‖ Softw. Microsyst., vol. 4, pp. 109–116, 1985. [28] S. Jones, R. Goodall, and M. Gooch, ―Targeted processor architectures for high-performance controller implementation,‖ Control Eng. Practice, vol. 6, pp. 867–878, 1998. [29] G. Ascia, V. Catania, M. Palesi, and D. Patti, ―Multi-objective opti mization of a Parameterized VLIW architecture,‖ in Proc. NASA/DoD Conf. Evolution Hardw. (EH), 2004. [30] Burr–Brown Corporation, Tucson, AZ, ―High dynamic range delta-sigma modulator,‖ 1997 [Online]. Available: http://www.burrbrown.com

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