Vlsi Training Details

Two Weeks Hands on Training on

VLSI Design & Verification

About the Training: The training aims to cover basic to advanced concepts of VLSI Design and Verification with Verilog, System Verilog, System C and C/C++. The training covers from digital design concepts to advanced RTL design and verification technologies. During this course, you will gain valuable hands-on experience, which provides a practical foundation for creating synthesizable RTL code and creating verification environment based on System Verilog and C/C++ with proper design flow. The focus of this training is completely based on the current market requirement in the semiconductor industries. Level: Fundamental to Intermediate Prerequisites: Basic digital design knowledge Skills Gained: 

Advanced Digital Design, Timing Analysis, State Machines, Memory Devices, RISC & CISC architecture

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CPLD and FPGA Architecture, ASIC Design Flow

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Basics of Synthesis, HDL for Synthesis and Advanced Synthesis Concepts

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Verilog Language for Hardware Design and Logic Synthesis, Design Flow with Verilog

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The File-IO and PLI concepts

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Functional Verification Flow & Terminologies, Verilog Testbench for Simulation

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An Introduction to System C/C/C++ based Hardware Modeling

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A mini Project for Testbench Modeling with C & Verilog

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Design & Verification Methodology with System Verilog

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Understanding the complete Project Execution Cycles

Who Should Attend? Engineers who want to learn advanced VLSI design and verification concepts.

For more details contact:

itie Knowledge Solutions nd

th

#934, 2 Floor, 17 Main Road, rd

Rajajinagar 3 Block Bangalore – 560010 Phone: +91. 80. 23146816 Email: [email protected] http://www.itie.in

Schedule Plan: Day Day 1

Topic of Discussion Advanced Digital Design, Verilog Introduction with basic examples, State Machines, Memory Devices

Self Study  Digital Electronics  Combinational & Sequential Circuits

Day 2

RISC & CISC architecture, CPLD and FPGA architecture, ASIC design flow, HDL Coding Guidelines

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Microprocessors Programmable Logic devices Any Book on Verilog

Day 3

Basics of synthesis, Timing Analysis, HDL for synthesis and advanced synthesis concepts

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Any Book on Verilog Timing Analysis Fundamentals

Day 4

Verilog for hardware design and logic Synthesis, Design Flow with Verilog, Tasks and Functions, Timing Controls,

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Any Book on Verilog

Day 5

State Machine Coding, The File-IO and PLI concepts, Discussion on Coding Exercises

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Any Book on Verilog

Day 6

Functional Verification flow Verilog testbench for simulation

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Verification Methodology Any Book on Verilog

Day 7

System C/C/C++ based Hardware Modeling

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Any Book on C/C++ Any Book on System C

Day 8

A Mini project for Testbench modeling with C & Verilog

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Articles A-1, A-2, A-3

Day 9

A Mini project for Testbench modeling with C & Verilog Continued

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Verification Methodology Any Book on Verilog

Day 10

Design & Verification methodology with System Verilog, Basic Exercises on System Verilog, Understanding the complete project execution cycles

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Any Book on System Verilog