Best Project Vlsi Anna University

FPGA Implementation of One Bit ΔΣ Control System Processor Mr. Mohan S*, Dr. Kamala J** *Master of Engg, Department of ECE, College of Engineering, Anna University, Chennai-25. **Faculty of Electronics and Communication, College of Engineering, Anna University, Chennai-25. Abstract:--A Novel Delta Sigma (ΔΣ) Control System Processor is a new technology and architecture for digital control system. Control laws can be efficiently implemented with one-bit signals at both the input and output of the system. Delta Sigma modulation is used to shape either analogue or multi-bit digital signals into 1-bit format at very high sampling frequencies. This 1-bit format contains all the useful information of the input. Thus making it possible to perform digital signal processing directly control to any physical device. The delta sigma control system processor utilizes 1-bit processing with the direct benefit of making multi-bit multiplication operations redundant. A simple conditional- negate-and-add (CNA) unit is used for operations in control law implementations. One bit architecture for processor results in less hardware and very high sampling rate. The proposed architecture provides higher efficiency in terms of performance, low cost, and high sampling rates compared to other digital controllers. Index Terms:--1-bit processing ΔΣ modulation, control system processor, VLSI, FPGA.

I. INTRODUCTION

R

eal-world automatic control systems were initially based

on analog electronics. With the availability of low-cost highperformance digital platforms such as microprocessors and microcontrollers, control system implementation evolved into the more flexible digital form which is now used almost exclusively. The main objective of such digital systems is the implementation of the control law, meeting the system real-time constraints, and the interfacing to the analog world via multi-bit analog-to-digital (A/D) and digital-to-analog (D/A) converters. In typical applications, the control law implementation directly drives such high performance electromechanical systems at sample rates of greater than 10 kHz; failure to meet the real-time control requirements of these target applications can lead to critical failure. Many A/D and D/A converters make use of an intermediate ΔΣ modulating stage for high quality data conversion. This ΔΣ modulator converts signals into a simple 1bit stream, at very high sampling frequencies. This bit-stream contains all the useful information of the input thus making it possible to perform digital signal processing directly on those 1bit signals. VLSI integration ΔΣ of the modulator along with the control system processor and other associated systems results in very high performance and small form-factor control systems [1]. Moreover, these systems interface to analog signals directly as the decimating filter for the A/D converter and the interpolating filter

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for the D/A converter are both removed. For this reason, ΔΣ based signal processing has been widely investigated in the context of finite-impulse-response (FIR) filters [2], [3], infiniteimpulse-response (IIR) filters [4], audio processing [5], and control system processing [6]. ΔΣ-based control systems can be implemented as software running on existing digital processors, but this does not result in a cost effective solution, particularly when taking the 1-bit feature into consideration. This paper describes a novel, ΔΣ-based control system processor for very demanding control applications and its performance, hardware cost, and maximum sampling rates are compared to other digital controllers, either standalone (including direct, hardwired implementations of control laws) or as software applications executing on very high performance, multi-parallel VLIW architectures. The remainder of this paper is organized as follows. The concept of 1-bit processing is introduced in Section II. Section III describes a direct, hardwired implementation of control laws with 1-bit processing. The processor architecture is given in Section IV, and a case study evaluating the performance of the ΔΣ-CSP in real-life control applications is presented in Section V. Section VI is temperature control application for one bit signal processing where the high speed ΔΣ-CSP can be utilized. Section VII concludes and suggests of ΔΣ-Control System Processor. II. 1-BIT PROCESSING 1-bit processing is a new concept in digital control and was originally proposed for reducing the area occupied by complex VLSI-based control systems [7]. A conventional (bit-parallel) structure is a continuous signal is digitized into a binary (bit-parallel) representation using a multibit A/D converter. The resulting digital signal is digitally processed within the controller and then used to control physical systems after undergoing D/A conversion via an A/D converter. Fig. 1 depicts a 1-bit control system in which the continuous signal is shaped into a single bit-stream via ΔΣ-modulation. The digital ΔΣ-modulator is embedded within the controller, in the main loop, resulting in a 1-bit [pulse density modulation (PDM)] signal after control processing. That processed 1-bit signal is then used to control physical systems directly through PDM which works similarly to pulse-width-modulation (PWM). A characteristic common to both control system architectures is the control law, which is designed using the same approach in both cases, i.e., either classic or modern control theory.

A. ΔΣ Modulation

sensitivity with traditional control system processing using the shift operator z [10], a characteristic that becomes particularly critical with the much higher sample rates required for 1-bit signal processing. It has been recognized that alternative forms, using the δ-operator, overcome a number of these issues [11]. The δ-operator is defined as

Fig. 2 shows a second-order ΔΣ-modulator in which two integrators are cascaded in the forward loop to create a higherorder filter, with each integrator receiving an additional input from the quantizer.

Ai

ΔΣ

Controller

1-Bit

ΔΣ

q 1 T

1-Bit PDM

in which q is the shift operator and T is the sampling period. Equation (2) shows that there is a unification between discrete and continuous time since resembles the continuous time operator d/dt as T→0. This expression can also be simplified even further [12].

Physical System Fig. 1.One-bit control system. xn z/ (z-1)

u

z/ (z-1)

Q (*)

q(x)

δ=q-1

y(n+1)=x(n)+y(n)

The output of the quantizer is a binary value (+/-1) which can be stored in a 1-bit register. For decoding, a decimating filter is required. After decimating, the multi-bit format of the input û is calculated as N

q ( xn)i

(3)

There is just a difference of scaling factors between these two definitions, with the second expression being more direct since it does not involve the division operation of the first equation. The equation y=δ-1x is implemented using the equation

Fig. 2. ΔΣ Modulation

1 û= N

(2)

(4)

Fig. 4 shows these fourth order controller structures, both using the δ-operator. These controller structures have precisely the same overall transfer function, although the set of internal controller states (x1, x2, etc.) is different in each case. This paper concentrates on two primary aspects of control system design: 1) achieving very high sampling rates and 2) minimizing the circuit complexity (area) through taking advantage of 1-bit processing. As a result of these objectives, the modified forms from [6] attract particular interest. The modified canonic architecture has been adopted in a conventional control system processor and will be used as a benchmark against the proposed ΔΣ-CSP, which takes the third form [see Fig. 4] when implementing control laws. However, this form results in very small coefficients with high sampling frequency, which is difficult to represent using a fixedpoint number format.

(1)

i. 0

Where N is the number of samples, xn is the last integrator’s output, and q(xn) is the output of the 1-bit quantizer. If xn is positive or 0, q(xn) is +1. If xn is negative, then q(xn) is -1 [8].

Fig. 5 illustrates a controller architecture implemented with the fourth-order ΔΣ-modulator. In this case, the input u is a 1-bit signal from the 1-bit A/D converter thus, all multiplications in this architecture are performed between that 1-bit signal (+/-1), with a multi-bit coefficient, effectively only changing the sign of that multi-bit coefficient. Multiplication therefore becomes a simple ―conditional-negate‖ operation, thus removing the requirement for large, multi-bit multipliers. This is particularly

Fig. 3. ΔΣ Modulation waveform The above Fig. 3 is a waveform of ΔΣ Modulation. However, the decimating filter is redundant in 1-bit processing. Because û is the average value of q(xn) over N samples, in the case of N being 1 (i.e., no decimator), each sample is directly related to the original input but with quantization noise [9]. When the oversampling frequency is sufficiently high, this quantization noise can be ignored as the noise spectrum within the signal bandwidth is much smaller than the input signal spectrum.

1-bit u P0

x1

P1

-1

B. Controller Structure 1-bit processing requires a very fast sampling frequency which may result in long word lengths for both coefficients and variables within the controller, primarily because the differences between successive values of the input and output become increasingly small. There are known issues on coefficient

q0

nbit

P2

δ-1

δ

x2

P3 -1

δ

x3

-1

δ

y

x4 1-bit

q1

q2

Fig. 4. Alternative modified canonic δ-form.

2

P4

q3

important for VLSI implementations and is a clear advantage of the ΔΣ-CSP over traditional designs, resulting in reduced circuit complexity and computation latency.

forms shown in Fig. 4, where is a binary scaling factor. The transfer function for this structure (not considering the ΔΣmodulator) is

1-bit u P0

P1 -1

q0

nbit

P2 -1

δ

x2

P3 -1

δ

δ

x3

q2

q1

P4 -1

δ

x4

1-bit PDM

Therefore, the coefficients become

ΔΣ

P0 = a5T4k-4; P1 = a4T3k-3; P2 = a3T2k-2 ; P3 = a2T1k-1; p4 = a1T0k-0;

y

q3

Fig. 5. Modified canonic δ-form combined with ΔΣ modulation. u P1

δ-1 n- & k q0

bit

P2 -1

δ &k q1

x2

q2

P3

δ-1 &k

x3

P4

δ-1 &k

x4

1-bit PDM

ΔΣ

(9)

The coefficients are multiplied with a scaling factor. Choosing the value of the scaling factor k requires a careful study as arbitrary values may involve multiplications which will increase the circuitry complexity. To avoid this, is chosen to be a negative power of 2 thus reducing multiplications to shift operations.

1-bit P0

q0 = b4T4k-4 q1 = b3T3k-3 q2 = b2T2k-2 q3 = b1T1k-1

D. Word Length The signal range requirements are usually modest in welldesigned digital control algorithms as full IEEE-754 floatingpoint compliant arithmetic [13] is expensive in terms of power consumption, area, and validation cost. For this reason, the ΔΣCSP adopts a fixed-point arithmetic format [1]. Table I. shows the general number format for the coefficients and state variables.

y

q3

Fig.6. Remodified canonic δ-form with scaling k.

TABLE I

C. Coefficients The transfer function of the modified δ-form controller structure in Fig. 4 can be written as

Number Format Sign Part

Integer Part

Fraction Part

1 Bit

7 Bits

16 Bits

A simple criterion used to determine the number of fractional bits in the range of 8–16 bits and signal with amplitude -128 to 127 which is sufficient for most control applications utilizing ΔΣmodulation, considering that input and output are ±1. There are no overflow or underflow bits specified as they are unnecessary in 1-bit processing [14]. Underflow problem is easily overcome due to the lack of multi-bit multiplications when using the proposed controller architecture of Fig. 6.

Consider for example a generalized single-input–single output (SISO) controller of fourth order. Its transfer function can be represented by

From (3), it is obvious that the operator approximates to sT. when the sampling time T is very small. Here, is the Laplace operator. Hence, from (5) and (6), the following coefficients are obtained: P0 = a5T4; q0 = b4T4 3 P1 = a4T ; q1 = b3T3 2 P2 = a3T ; q2 = b2T2 1 P3 = a2T ; q3 = b1T1 0 p4 = a1T (7)

III. DIRECT IMPLEMENTATION The most straightforward approach to realize ΔΣ-based control systems in VLSI is to implement the controller architecture of Fig. 6 directly. Fig. 7 depicts such a direct implementation of a fourth-order ΔΣ based control system with the 1-bit variables denoted by the thin lines and the multi-bit variables of the format depicted in Table I shown. The input data comes from a ΔΣmodulator which is located off-chip, but the ΔΣ modulator for the output data is integrated with the controller and thus resides onchip. The states that are required for the next-sample calculations are stored in registers. The sample timer is used to determine when to read new input data and write new output data.

As T is very small compared with the time constant of the transfer function, the coefficients become increasingly smaller with increasing controller order. This makes it more difficult to represent such small values in a fixed-point format. In order to scale these coefficients, the controller architecture has to be modified as shown in Fig. 6, essentially a hybrid between the two

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As all the calculations operate on 2-complement numbers, the sign bit identifies a value as positive or negative, where 1 means a negative value and 0 means a positive value. In 1-bit signal representation, -1 is assigned the 0 value; it is thus easy to implement the 1-bit quantizer of the ΔΣ modulator with an inverter. Also, in the ΔΣ modulator, the first, third, fifth and seventh adders require only the addition of a 1-bit signal to the eight most significant bits of the 24-bit signal.

p1

1-bit u

p0

o

o

δ-1

o

p2 δ-1

k

o

p4

δ-1

> D

p3

> D

> D

k

24-bit

q0

o q1

o q2

o q3

o

δ-1 >

D

k

placement etc. The FPGA floor planning of virtex2pro device as shown in Fig. 9. Second Fig is enlarged floor planning of FPGA. Floor planning allows us to predict this interconnect delay by estimating interconnect length. At the start of floor planning we have a net list describing circuit blocks, the logic cells within the blocks, and their connections. Floor planning is thus a mapping between the logical description and the physical description. In this floor planning we wish to predict the interconnect delay before we complete any routing. At the floor planning stage we know only the fanout of a net list and the size of the block that the net list.

k

o

24-bit 1-bit

y D

D

x x[23]

Sample Timer

Fig. 9. Floor planning of fourth-order ΔΣ control system (a) Full Overview. (b) Enlarged Floor planning.

Fig. 7. Direct implementation of a fourth-order ΔΣ control system in VLSI. ΔΣ control system is implemented with a second order sample timer and fourth order controller used. Increase the order of the system provides good accuracy with circuit complexity. The output of sample timer y is one bit signal as shown Fig. 8.

The timing-analysis tool reports that the critical path of clock in the optimized delay is 26.348 ns. The total power consumed by the device is 95 mW, when we use 3.3 V for operating I/O ports and supply voltage. These details describe by Table III. TABLE III

Power and Delay Estimation Summary

Fig. 8. Waveform of a fourth-order ΔΣ control system in VLSI. The fourth-order ΔΣ control system implemented in ISE design environment, the synthesis report was carried out by using the FPGA device Xilinx virtex2pro, speed grade -6. The Table II is details about device utilization summary, TABLE II

Device Utilization Summary Logic Utilization

Available

Used

No. of Slices No. of Slice FF No. of 4 input LUTs No. of bonded IOBs

3008 6016 6016 140

226 146 438 3

Parameter

Current (mA)

Power (mW)

Total Power Consumption Vccint 2.50V: Vccaux 3.30V: Vcco25 3.30V:

-30 05 01

95 75 17 03

Parameter

Delay (ns)

Minimum Clock period (37.954MHz) Minimum input arrival time before clock Maximum output required time after clock

26.348 28.498 04.182

The proposed direct implementation allows us to perform the whole control system processing in a pipelined manner. After completing the calculations, the circuit stops working and awaits the next sample trigger event. Hence, this is the fastest and simplest implementation of a 1-bit controller. However, this architecture is not flexible enough as it is fully hardwired for one particular control task.

The logic synthesis provides a link between an HDL and a net list. Logic synthesis, after getting the pre-simulation result with the help of test bench and we can generate floor planning,

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IV.

in the ΔΣ-CSP that stores the instructions is known as the program RAM or as a single-port SRAM block. The data RAM maximum size of 512 x 24-bit words, utilizes a dual-port configuration and stores the coefficients and initial data. As the program counter is 24-bit wide, it can address a maximum of 16 mega-instructions whereas compile-time switches allow for the static-configuration of both the instruction bit-width as well as the instruction memory size. The program counter maintains a pointer to the currently executing instruction of the control law in the program RAM. The ALU takes the opcode and three input operands, from the I/O block, the accumulator, and the data RAM, respectively, for each calculation cycle. The controller architecture, conditional-negate-and-add (CNA) unit is performs

MICROARCHITURE AND PROCESSOR

To alleviate the rigidity of the direct implementation a novel, processor has been developed resulting in a ΔΣ-based control system processor (ΔΣ-CSP). Fig. 10 depicts the block diagram of the ΔΣ-CSP. All calculations take place in the arithmetic and logic unit (ALU) which has direct access to data read from the I/O unit. The Instruction Set Architecture of the proposed programmable solution is shown in Table IV. The instruction set is fairly small and specialized to control law implementation. TABLE IV ΔΣ-CSP Instruction Set Architecture

Binary Opcode Description 000 001 010 011 100 101 110 111

HLT RDW WRB WRW SRS CAN SET WPC

D= (-) B|A+C

No operation Read data from program RAM Write result to digital output port Write the intermediate states to the data RAM Right shift Conditional negate and accumulate Set timer sampling frequency Set control law start address

Where B is either a coefficient or a state variable, A is a 1-bit signal, and C is a state variable. (-) is a symbol which signifies conditional-negate. After completing the CNA operation, the result of the conditional-negation is added to the state variable and C stored in the accumulator. The ALU includes conditionalnegate-accumulate and shift units only needed [14]. After processing in the ALU, each result is stored in the accumulator for the following instruction at the next clock cycle. Note that the data in this accumulator will be cleared as soon as an ―HLT‖ instruction is read.

The overall word-length of the ΔΣ-CSP 16-bit word format. Each instruction was utilized 3 bits for the opcode, 4 bits for the digital I/O, leaving 9 bits for data RAM addressing. The

V. MOTOR CONTROL APPLICATION

External Interface

To thoroughly evaluate the performance of 1-bit processing in real-life control applications, a practical dc motor controller is demonstrated in this section.

USB core

Program RAM (2^16x24bits) Addr

PC

Data

Opc

ALU Data Accumulator

A. DC Motor and Controller The details of dc motor model using Laplace transfer function was given in [6]. The objective is to control the position of a rotating load with flexibility in the drive shaft. In this particular example the important variable that will be affected by high frequency noise due to the heavily-sampled 1-bit signals is the motor current. A fourth-order position controller was designed including a proportional–integral (PI) filter transfer function is

Instr Inst-Decoder

Addr IO

1-bit Address

Data RAM (512x24bits)

(10)

For 1-bit processing, the SNR is related to the sampling frequency given the proposed controller architecture. The SNR improves when the sampling frequency increases. Therefore, the sampling frequency must be at least 300 Hz to meet the SNR requirement (27 dB). The coefficients for the controller, when the sampling frequency is selected at 1000 Hz, are calculated according to (9) and are listed as follows:

Timing and Control

Fig. 10. ΔΣ-CSP high-level diagram

p0=2.684354560000000x10^-3 p1=5.244977151999999x10^0 p2=4.096655359999999x10^0 p3=1.280512000000000x10^0

instructions, coefficients, and initial data are stored in program and data RAMs (SRAMs) respectively, allowing reprogramming of the controller with different control laws. The memory blocks

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p4=1.000000000000000x10^0 q0=0 q 1=2.097152000000000x10^1 q 2=1.802240000000000x10^1 q 3=1.408000000000000x10^1 K=128

bit digital signal, and fed into FPGA. The output of the FPGA 1bit PDM signal and directly fed into dc motor. PDM is produced by use of ΔΣ-modulator. The output of dc motor is analog signal with the help of position transducer. (12) VI. TEMPERATURE CONTROL APPLICATION

B. Simulation Results Simulations have been carried out in MATLAB/Simulink using the ΔΣ controller interfacing, with a continuous time representation of the physical system. The step response of the overall control system simulation is as shown in Fig. 11. The coefficients are represented in a 24-bit fixed-point word format. A small portion of the simulation results is the peak response at 1 to 1.5ns in x-axis. The only identifiable difference is that the motor oscillates a bit more heavily in simulation. This is due to the effect of Pulse Density Modulation (PDM) and will not affect the whole system performance. After 2ns in x axis, the motor response becomes steady; there is a maximum error within 2.5% due to the effect of fixed point word format, which is acceptable for the particular control system.

This section describes another application of a microprocessor based controller for temperature control in an air-flow system. Fig. 13 gives hardware description of the temperature control system. Let us examine briefly the function of each block. The block labeled keyboard interfaced to the microcomputer through a programmable keyboard display interface chip. The LED display unit provides display of the actual temperature of the heating chamber. The temperature range for the system under consideration is 20 to 60oC. When a thermistor is used as temperature transducer, it is necessary to convert the change in its resistance to an equivalent analog voltage. This is accomplished with Wheatstone bridge; the thermistor exposed to the process air forms one arm of the bridge. Millivolt range of the bridge error voltage is amplified to the range required by ΔΣ converter. The output of the ΔΣ converter is one bit digital measurement of the actual temperature of the process air. This data is fed to the microcomputer through an input port. Key board LED

1-bit Triacs & MicroFiring ΔΣ computer Circuit n-bit

Triac Control ΔΣ Analog Signal

Amplifier

Fig. 11. Step responses of simulink result Hardware simulation verifies the feasibility of the Direct implementation ΔΣ control system. Here, ΔΣ control system was implemented in an FPGA technology. The FPGA device chosen was the Xilinx virtex2pro XC2VP4-6FG256, speed grade -6. Synthesis was carried on the Xilinx synthesis technology (XST), part of the ISE design environment. It is fourth-order controller for demonstration. Fig. 12 shows hardware simulation scheme. 1-bit ADS1201

Xilinx Virtex2pro Controller

Analog Signal Transduce r

ΔΣ

Heater

Transduce r

Heating Chamber

Fig. 13. Block diagram of temperature control system. The microcomputer compares temperature and generates an error signal. The error signal is then processed as per control algorithm, resulting in a control signal in 1-bit PWM (similarly PDM). The power input to the plant may be controlled with the help of triacs and firing circuit interface. If the triac closes the circuit for tp sec. out of T sec. the average power applied to the plant over the sampling period T is

1-bit

tp= (u*R/V2) T

PDM

(13)

Where, V-rms value of the applied voltage and R- resistance of the heater. Depending on the control signal u, tp is calculated in microcomputer. The function of the triacs and firing circuit interface is to process the PWM output of the microcomputer such that the heater is ON when the PWM output is logic 1, and OFF when it is logic 0. Since the heater is operated off 230 V ac at 50 Hz, the firing circuit should also provide adequate isolation between the high voltage ac signals and the low voltage digital signals.

DC MOTOR

Fig. 12. Hardware simulation scheme. Here, the hardware simulation result is same as the simulink result. The ADS1201 [15] is used to convert analog signal into 1-

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[14] S. Jones, R. Goodall, and M. Gooch, ―Targeted processor architectures for high-performance controller implementation,‖ Control Eng. Practice, vol. 6, pp. 867–878, 1998. [15] Burr–Brown Corporation, Tucson, AZ, ―High dynamic range delta-sigma modulator,‖ 1997 [Online]. Available: http://www.burrbrown.com

VII. CONCLUSION The ΔΣ-CSP is an extremely small and fast application-specific processor. Despite its simplicity, the ΔΣ-CSP is a very potent platform for the execution of complex control laws. With the exception of the direct VLSI implementation of the control law, the ΔΣ-CSP provides substantial performance improvement, in terms of the absolute sampling rate and very low power budget, particularly compared to the VLIW architectures. At the same time, it maintains a fully programmable programmer’s model that can easily be retargeted to different control applications whereas the direct implementation would need to be redesigned from scratch. REFERENCES [1] Xiaofeng Wu, Vassilios A. Chouliaras, Jose Luis NunezYanez, and Roger M. Goodall, ―A Novel ΔΣ Control System Processor and Its VLSI Implementation,‖ IEEE Trans.VLSI, Vol. 16, No. 3, Mar. 2008, pp. 217–228. [2] S.Kershaw, S.Summerfield, M.Sandler, and M.Anderson, ―Realisation and implementation of a sigma-delta bitstream FIR filter,‖ IEE Proc.-Circuits Devices Syst., vol. 143, no. 5, pp. 267–273, Oct. 1996. [3] P. W. Wong and R. M. Gray, ―FIR filters with sigma-delta modulation encoding,‖ IEEE Trans. Circuits Syst., vol. 38, no. 6, pp. 979–990, Jun. 1990. [4] D. Johns and D. Lewis, ―IIR filtering on delta-sigma modulated signals,‖ Electron. Lett., vol. 27, no. 4, pp. 307– 308, Feb. 1991. [5] J. Angus, ―One bit digital filtering,‖ in IEE Colloq. Dig. 1998/252, Apr. 1998, pp. 811–816. [6] X. Wu and R. Goodall, ―One-bit processing for real-time control,‖ presented at the Euro. Control Conf., Cambridge, U.K., 2003. [7] R. Goodall, ―Perspectives on processing for real-time control,‖ Ann. Rev. Control, vol. 25, pp. 123–131, 2001. [8] Sangil Park, Ph. D. Strategic Applications DSP Operation Book on ―Motorola DSP, Principles of Sigma-Delta Modulation for Analog-to-Digital Converters‖ APR8/D, pp. 6.1-6.6. [9] S. H. Ardalan and J. J. Paulos, ―An analysis of nonlinear behavior in delta-sigma modulators,‖ IEEE Trans. Circuits Syst., vol. 34, no. 6, pp. 593–604, Jun. 1987. [10] B. Liu, ―Effect of finite wordlength on the accuracy of digital filters—A review,‖ IEEE Trans. Circuit Theory, vol. CT-18, pp. 670–677, 1971. [11] G. Orlandi and G. Martinelli, ―Low sensitivity recursive digital filters obtained via the delay replacement,‖ IEEE Trans. Circuits Syst., vol. CAS-31, no. 7, pp. 654–657, Jul. 1984. [12] R. Goodall and B. Donoghue, ―Very high sampling rate digital filters using the operator,‖ Proc. Inst. Elect. Eng. G, vol. 140, no. 3, pp. 199–206, 1993. [13] IEEE Standard for Binary Floating-Point Arithmetic, 7541985.

Contact details: Mr. Mohan S [Reg No: 200731631], M.E – Applied Electronics, Final Year, Dept. of ECE, College of Engineering, Anna University, Guindy, Chennai– 600 025. Tamil Nadu, India. Mail: [email protected] Dr. Kamala J, ISTE, MITE, Lecturer, Dept. of ECE, College of Engineering, Anna University, Guindy, Chennai– 600 025. Tamil Nadu, India.

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