Substrate Noise Issues In Mixed-signal Chip Designs Using Spice

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SUBSTRATE NOISE ISSUES IN MIXED-SIGNAL CHIP DESIGNS USING SPICE

R Singh S Sali University of Newcastle-upon-Tyne, England

ABSTRACT As digital clocking frequencies continue to increase, substrate noise is fast becoming a critical issue for mixed-signal chip designers. However, current methods for directly modelling the noise in realistically-large Spice designs are impractical, due to numerical instabilities. In this paper, partial modelling of the substrate is introduced and shown to be an efficient and viable approach. The technique is validated using a testbed circuit. Commonly-used noise-reduction schemes are briefly compared and P+ guard-rings are used to reduce the noise in an example circuit.

substrate model. A software tool (SubSim) has been written to automatically integrate the substrate in Spice designs. It is simple and efficient to use, involving no VLSI information and minimal fabrication details. SubSim integrates both CMOS and BJT devices with the substrate and has been written for use in PSpice net-lists. In Section 11, we briefly summarise the theory behind substrate modelling in Spice designs. In Section 111, partial-substrate modelling is proposed as a viable method for making substrate modelling more efficient and practical. In Section IV, we compare the commonly-used methods for reducing substrate noise. In Section V, partial-substrate modelling is used in an example circuit. P+ guard-rings are also integrated, to reduce the noise level.

I. INTRODUCTION Due to the rapid pace of change of silicon-device technologies, circuit designs are becoming very fast and compact. Their implementation is shifting away from PCBs, and even multi-chip modules, to fully integrated on-chip designs. Substrate noise, due to digital switching, has emerged as a key limiting factor in the design process, with digital clocking reaching close to microwave frequencies. Signal integrity is therefore a major problem, and many designers have chosen to remain with PCB or multi-chip designs, until substrate modelling is a more efficient and accurate process. Indirect methods have been published which can accurately, and sometimes efficiently, model the substrate noise (see Verghese et al(l), and Miliozzi et 4 2 ) ) . However, in Spice designs, it is many times not possible to turn to such tools, because of their expense and/or complexity. Efficient modelling of the substrate noise, using tools such as Spice, is therefore a fundamental requirement. Direct integration of the substrate throughout a design has been traditionally used (Joardar(3) and (4), Su et d ( 5 ) and Verghese et a1(6)), but is impractical for realistic designs. This is due to the way Spice numerically solves for the solution values, using a network topology termed the Modified Nodal Admittance (MNA) matrix. In unstable situations, the numerical algorithm finds global minima from which it is unable to recover, and the simulation crashes. In this work, we propose that a first-order approximation to the substrate noise can be gained by modelling only selective regions of the substrate - i.e. using a partial-

11. SUBSTRATE MODELLING IN SPICE DESIGNS The type of substrate model used in Spice designs depends on the doping profile of the substrate. Currently in industry, there are two common profiles either a heavily-doped substrate with a thin lightlydoped epitaxial layer, or a uniformly-doped substrate. The former doping profile is commonly used in CMOS, and in hybrid BiCMOS, technologies and is assumed in this work. Substrate noise occurs when current is injected from the drain into the substrate, when the NMOS device switches. Further CMOS devices at the output drain node, provide high capacitative loading which increases the current flow into the substrate. Digital clock frequencies, using this doping profile, can reach up to about lOOMHz - thus leading to high substrate noise levels. The current is injected vertically into the heavilydoped substrate, as it 'seeks' the lowest resistance path. Therefore, a lumped equivalent circuit can be used to represent the link between the circuit nodes and the substrate. Fig. 1 shows the circuit diagram for the NOT-gate structure, with the substrate connected to the CMOS devices. The bulk resistance, for a chip size of lcm x lcm, can be calculated as approximately lo@. Because the heavily-doped substrate has such a low resistance, it is assumed to be a short circuit and is therefore represented by a single electrical node,

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called the bulk node. This model is sometimes referred to as the single-node model. The resistive link from the substrate terminal of the CMOS device (either PMOS or NMOS) can be represented by equation (1). This equation (taken from (5)) represents the parallel combination of two lumped resistors - the area component of the total resistance, and the resistance due to current flow at the perimeter of the diffusion. In a P-type substrate, as is considered here, the N-wells (used for PMOS and NPN devices) form capacitative links through the epitaxial layer to the bulk node. These are calculated using equation (2). These two equations form the basis for the equivalent circuit, linking the bulk node to the design.

E CN-we,,

=

x Area

T

(2)

and p represent permeability of the N-well and the resistivity of the epitaxial layer, respectively. T is the depth between the N-well and the p+ bulk (across the epitaxial layer). W and L are the dimensions of the diffusion connected to the resistor and Area is the area of the N-well. The symbols kl, k2 and 6 are 3 unknown parameters, which are empirically calculated using measured data from 3 test structures. This is important, so that these theoretically approximate equations show relatively little error. For example, ( 5 ) states a 15% error between the theoretical and measured equivalent lumped resistor values. This approach, to directly modelling the substrate linked with Spice design, is very simple and efficient. In the digital sections, mixed-signal Spice tools (for example PSpice is used here) model the digital gates using highorder behavioural models (digital primitives) which are very fast and simple, but approximate. Between the analogue and digital sections, PSpice inserts A/D and D/A converters, where appropriate. Integration of the bulk node requires the whole circuit to be represented in ‘analogue‘ terms, so that all the device nodes can be connected. E

111. PARTIAL-SUBSTRATE MODELLING Spice is already known to be very limited in the size of circuits it can handle, due to numerical instabilities. Each CMOS (or BJT) device requires a number of simultaneous equations to be solved, at each time point. Bulk node integration causes more problems by integrating further nodes and instabilities. Therefore,

full-substrate integration is both inefficient and impractical. However, if only selected areas of the design - typically the high-frequency digital sections and the sensitive analogue sections - are modelled with a substrate, then much larger circuits can be modelled for substrate noise. To show that this method is accurate to the first-order, a test-bed circuit (shown in Fig. 2) has been used. Two simulations have been run - the circuit has been simulated with all the lines linked to the substrate (fullsubstrate model), and with only the high-frequency digital line (100MHz) and the analogue line connected (partial-substrate model). Fig. 3 shows the bulk noise for the circuit with a 40MHz analogue input of magnitude 2.5&0.1V, where the solid lines represent the full-substrate implementation. Results were taken for both CMOS and BJT comparators (see Fig. 3(a) and 3(b)). As the results show, for this relatively highfrequency analogue input, a 30% partial-substrate model (as used here) gives an acceptable first-order approximation to the noise levels in the substrate. These results also show visually that the dominant frequencies are the same for both full and partial substrate models. This suggests that when the substrate noise results are not accurate in the timedomain, they can be used as a reference point for noise reduction in the frequency domain. Further tests with lower analogue input frequencies (lMHz and 10MHz) confirmed this point.

IV. METHODS FOR REDUCING SUBSTRATE NOISE The various methods, commonly used for substrate noise reduction, include :

0

0

0 0

P+ guard rings. N-well guard rings. Trench oxide isolation. Silicon-on-oxide (SOI). MOSCAPs. chip packaging (RLC) tuning.

For the uniformly-doped substrate profile, (4) has calculated and compared the effectiveness of each method (see Fig. 4). (4) has shown that P+ guardrings are the most effective scheme for noise reduction, at high frequencies. (5) has also drawn this conclusion for the single-node model, noting that the P+ guard rings need to be very close to the device for them to be effective - typically less than the epitaxial layer’s depth. This is because the resistance path becomes lower than passing to the bulk. In order to insure effective use of guard-rings, a separate chip-pin is used which can often be difficult to implement. An alternative method is to bias the guard-ring using a ‘quiet’ digital line.

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From Fig. 4, it is shown that P+ guard-rings are as effective alone, as with both N-well guards and trench oxide isolation. This is because both these latter methods fail to reduce the current flow to the heavilydoped bulk. Silicon-on-Oxide has been used to overcome many noise problems. It is most effective at low frequencies, because of the dc barrier formed by the oxide. This oxide layer is capacitative and therefore loses its opencircuit circuit properties, as the frequency increases. SO1 is a non-standard process and therefore is more expensive than other presented methods. From Fig. 4, an ideal scheme would be a combination of P+ guard-rings and SOL Another method, which can be used to filter out the high frequency components of the bulk noise, is to use MOSCAPs (see (6)) - a MOSFET-type structure which creates an effective capacitative link with the bulk. The value of the capacitance is determined by the dimensions of the device, using equation (2). Also, an important factor is the tuning of the FUC lumped values forming the bond-wires and packaging. In (5), this area was highlighted as a very important factor in noise minimisation. Unfortunately, nonstandard chip-packaging has been the only offered solution. This is again expensive.

V. EXAMPLE CIRCUIT Fig. 5 shows the example circuit used to demonstrate the benefits of partial substrate modelling. Vi, was a 40MHz sine wave, of magnitude 2.5Vf1.5V. SubSim was used to integrate the substrate both partially and fully, and then noise-reduction techniques were applied. The circuit with a full-substrate integrated could not be modelled, using PSpice. An approximately 30% substrate model was created by linking half of the comparators (8/16), from each of the Analogue-toDigital converters, to the bulk node. The A/D and D/A PSpice interface structures, which PSpice automatically inserts alongside digital primitives, were found to destabilise the circuit when digital primitives were modelled with the bulk node - i.e. in analogue mode. This is a common problem which was avoidable here, because the output stages of the comparators show the same driving characteristics as the highest frequency digital gates, in the circuit. Therefore, no digital gates were needed to be modelled with the substrate linked. As the input frequency was sufficiently high, these conditions were taken as similar to that used in the test circuits in Section 111, and therefore were assumed to be accurate to the first-order. Fig. 6 (solid line) shows the substrate noise level, for a full-time period of the input signal. The noise level seems uncomfortably high and SubSim was used to automatically integrate isolation techniques to reduce this level. As mentioned in Section IV,

placement of P+ guard rings close to the digital noise sources and sensitive analogue nodes, is an effective technique commonly used to reduce the substrate noise level. P+ guard-rings were integrated close to the NMOS devices at the positive inputs of each of the comparators which were modelled with the substrate. The dashed line in Fig. 6, shows the resulting substrate noise. The noise level has decreased by approximately 50%, demonstrating the effectiveness of the P+ guardrings. Also, a single MOSCAP was integrated. The resulting bulk noise (Fig. 6, dotted line) shows the delay and smoothing, caused by the capacitor. There is a significant reduction in noise level, which can be increased by raising the capacitance value - i.e. by increasing the MOSCAP’s area. This will increase the attenuation of the bulk noise, at lower frequencies.

VI. CONCLUSIONS In this paper, we have demonstrated the requirement for partial-substrate modelling. A test-bed circuit has been used to validate this method. A partial substrate model was used to investigate the noise and noise levels in an example circuit, which would have not been possible under current methodologies using a full-substrate model. Commonly used noise-reduction schemes have been compared and P+ guard-rings have been used to lower the noise levels in the example circuit.

REFERENCES 1. Verghese N.K. et al, 1996, “Verification techniques for substrate coupling and their application to mixed-signal IC design”, IEEE J. Solid-state, 3 l , 354-365 2. Miliozzi P. et al, 1996, “Subwave: a methodology for modeling digital substrate noise injection in mixed-signal ICs”, IEEE Proc. CICC96, 385-388 3. Joardar K., 1996, ‘Substrate crosstalk in BiCMOS mixed mode integrated circuits’, Elsevier SolidState Electronics, 39, 511-516 4. Joardar K., 1994, “A simple approach to modeling cross-talk in integrated circuits”, IEEE J. SolidState, 29, 1212-1219 5 . Su D.K., Loinaz M.J., Masui S., Wooley B.A., 1993, “Experimental results and modeling techniques for substrate noise in mixed-signal integrated circuits”, IEEE J. Solid-state, 28, 420429 6. Verghese N.K. et al, 1995, ‘Simulation techniques and solutions for mixed-signal noise in integrated circuits”, Kluwer Academic Publishers, Boston

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Fig. 1 : NOT-gate linked with bulk node

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Fig. 3 :Test circuit results (solid line represents full substrate, and dashed line represents partial-substrate)

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Fig. 2 : Test circuit used to validate partial-substrate approach

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Fig. 4 :Comparison of common isolation techniques (data taken from (4))

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Fig. 6 : Comparison of substrate noise, with P+ guard-ringsand MOSCAP integrated

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