The Substrate Noise Detector For Noise Tolerant

THE SUBSTRATE NOISE DETECTOR FOR NOISE TOLERANT MIXED-SIGNAL IC Byung-tae Kang, N. Vijaykrishnan, M. J. IrwisD. Duarte* Microsystems Design Laboratoty Pennsylvania State University, PA 16802 Abshact-A new type of substrate noise detector is proposed. It is embedded in a mixed-signal IC and monitors the level of

substrate noise. The voltage comparators are used to detect errors and a counter tracks tbe number of errors periodically. From tbe number of error, the level of substrate noise is estimated using the probabilistic approach. This type of detector is useful in that it monitors substrate noise in real-time. Using this, tbe various adaptive algorithms become feasible to reduce substrate noise. The details of detector circuits are.

A

v, =v,,

( y : body-effect coefiicient, +6 : the surface inversion potential, and V,: the threshold voltage for VsB Vr is a function of Vss because other parameters are mainly determined by the semiconductor technology. As explained, the substrate voltage is generated by abrupt drainimg of substrate current when digital circuits are switching. The substrate voltage makes the threshold voltage fluctuate, as a consequence, V, changes as a result of the variation. The second step of designing the substrate noise detector is the analytical estimation of TIQ voltage comparator. Before simulating the variance of V,, the substrate noise should be modeled. Eq-2 shows the VS, model [3]. - Eq-2 A . .sin( a n- f + p)

=Ow

I. INTRODUCTION

nalog circuits are being implemented by deep . ' . sub-rmcron CMOS technology and integrated with large digital circuits such as DSP cores. The high speed digital circuits generate substrate noise that is propagated to the analog circuit. This noise can be destructive in embedded analog circuits, dynamic logic and memory. Many papers have been recently published characterizing the substrate noise [I]. In this paper, a new type of substrate noise detector is proposed. It is embedded in the mixed-signal IC and monitors the level of substrate noise. Voltage comparators are used to detect errors and a digital counter counts the number of errors periodically. From the number of errors, the level of substrate noise is estimated using the probabilistic approach. This type of detector is useful in that it monitors substrate noise in real-time. Using tbis, various adaptive algorithms become feasible to reduce the substrate noise. The rest of this paper is organized into three major parts. In section 11, detail design steps of proposed circuit are explained in an analytical way. Section 111 presents the experimental results. Finally, we provide concluding remarks in Section N.

n.

comparator [2] is used The TIQ comparator uses two cascaded CMOS inverters as a comparator for implementing a high-speed flash ADC. Due to space constraints, we do not discuss the principles of this comparator. V, defined as the Vin=Vout point [2] can fluctuate when the threshold voltage of PMOS or NMOS changes. In general, the threshold voltage is determined by Eq-1 +Y(&K-&) - Eq-1

Y

V,

Table-l The mean and variance ofV. along with Vm rmsofVs I 22.9mV I 32.6mV I 65.2mV I 98.6mV Mean I 0.757159 I 0.757239 I 0.756715 I 0.755619 I 0.000038 I 0.000077 1 0.000312 I 0.000733 VX.

A. Probability of Error Approach

* D. Duarte is with Logic Technology Development, Intel Corp.Hillsboro OR 97124 USA (e-maildaYid.e.d~art~~,int~l.com). This work WBS supponed in part by NSF 0082064,CAREER 0093085 and M A R C 0 98-DFd00 GSRC

0-7803-8182-3/03/$17.00 02003 IEEE

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We define A. as a random variable for the magnitude of VsB. It has an uniform distribution. Here onis the harmonic of digital switching frequency. is a random variable for the phase shift and uniformly distributed from 0 to 2%. The mean and variance of V, are simulated by Eq-2. In this simulation, 0.25 micron technology parameters are used and supply voltage is assumed to be 2.5V. We simulate it for IO usec (10000 samples) at lGHz sampling. Table-I summarized the mean and variance values.

DESIGN OF SUBSTRATE NOISE DETECTOR

The first step of designing the substrate noise detector starts with explaining the voltage comparator of the Analog to Digital Converter (ADC). The voltage comparator compares the difference between input voltage and a reference voltage and propagates the result to the encoder part. In this paper, Threshold Inverter Quantization (TIQ)

=

The results of Table 1 imply that the larger Vsa generates the larger error. The distributions is approximately same as Gaussian distribution. For simplicity, we assume the distribution of V, as Gaussian distribution and each comparator's distributions are independent. (In reality, tbis is not true. It will be discussed later). Fig-1 shows the distributions of three comparators in ADC. Vm(i-l) is the lowest and V,(i+l) is the highest bit among three comparators. Three comparators' V, are changing with

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substrate noise independently as Gaussian distribution. When V,(i) is in the region 1 and V&I) is in the region 2, i& comparator produces output 1 and i-l& comparator produces output 0. This is obviously an error and called as monotonic error. In this case, the probability of monotonic error is determined by Eq-3. P.

= Pc(regionl). P. (region2)

other. In this case, the probability of error is determined by Eq-4 (in Fig-I) P, = (region3) + P, (region4) Eq-4 When the noise does not exist, the output of the comparator 1 should be zero and the output of the comparator 2 should be one. But the noise makes V, value of both comparators increase or decrease at the same time. When the V, value of comparator 2 is over 0.77V, its output will be zero. This case is the monotonous error. Conversely, the negative noise makes V, value of two comparators decreasing. Then the output of comparator 1 can be under 0.77V and makes the monotonous error.

-

III. EXPERIMENTAL RESULTS

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Region 3’

Region 4

Fig-1 The monotonic ermr region

B. Proposed Circuit

nQ

Enor

Gain

........... e o ~ , ~ t ~ ~ , , , ,................... , , . , B o o...s...t..e...r

C o ~..................................... t

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F i g 4 Simulation results of subshate noise detector

I i

3 Counter Clock SamphgCloek

‘j I 1 :

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20

11

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i

Fig-2 The subsmte noise detector

TIQ comparator has two pairs of inverter that have different channel length and width. Each comparator’s parameters are summarized in Table-2. The values of V, are measured by HSPICE using 0.25 micron technology. The measured value is close to the calculated value using Eq-l(The calculated value is 0.757V. The error is approximately 1%).

Fig-3 shows the simulation result ofproposed circuit using HSPICE. The input volage is 0.77V and noise’s peak is varying from OV to 12Omv. The fmt half of noise waveform is the positive noise and the second half of noise waveform is the negative noise. From Fig-3 (c), we can see that V, value of comparator 1 is decreased in the negative noise region (especially noise peak is under 4OmV). From Fig-3 (d), we can see that V,,, value of comparator 2 is increased in the positive noise region (especially noise peak is over SOmV). The negative and positive noise is detected by error counter enable. The counter enable accumulates the number of errors within a specified time (Imsec in this case). Using this value, Eq-4 and analytically pre-calcualted values in Table-I, we can estimate the r.m.s. value of substrate noise.

1 Table-2 The s ecification of inverters com arator Width 2.37~ 0.24” NMOS 0.24” PMOS 2.oou 0.24” NMOS in.nsu 0.24”

0.7YV

0.75V

As mentioned earlier, two comparators are dependent on the substrate noise level. If the positive noise is asserted, the V, oftwo comparatorswill be increased at the same time, and vice versa. In Fig-1, we calculated the probability of error assuming that two comparators are independent on substrate noise. To emulate the independency, V,(i) in Fig-I is replaced by a constant voltage source from outside of chip that has the mid-value between V,,,(i-l) and V,(i+l) (0.77V in this case). Then other comparators, V,(i-1) and V,,,(i+l) are independent with V,(i) and remain dependent with each

IV. CONCLUSION A new type of substrate noise detector is proposed and its design steps are explained. It is analytically analyzed, implemented using 0.25 micron technology and tested. It is composed of simple circuits and detects the substrate noise sensitively.

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REFERENCES

111 E.Charbon. R. Ghamurev. P. Miliozzi. R. Mcver. and A. L. Sangiovanni-VinceteUi,SUBSTRATE NOISE, W 2001 121 J. Yoo, K Choi and A. Tangel, “A 1-GSPS CMOS flash AID convener for system-on-chinamlications.”lEEE annual workrhom on YLSI., P p i G - n ~May.iobi. , [3] Y. Zinzius, G. Gielen and W. Sansen, “Analyzing the impact of subsmte noise OD embedded analog-todigital converten,” in Pmc. f s t IEEE InternafionolConference OB Circuifs ond&temr for Communications, 2002, pp. 8 2 4 5 . L

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