Modeling Of Substrate Noise Block Properties

Modeling of Substrate Noise Block Properties for Early Prediction Grzegorz Blakiewicz

Malgorzata Chrzanowska-Jeske

Department of Microelectronic Systems Gdansk University of Technology Gdansk, Poland e-mail: [email protected]

Electrical & Computer Engineering Portland State University Portland, USA e-mail: [email protected]

Abstract— We propose a new approach to substrate noise modeling in early design planning of Mixed-Signal System-onChips (MS-SOCs). It can be applied to a system without any detailed knowledge (physical-layout) about its building blocks. We assume and justify that in early prediction only the most significant noise sources of substrate noise need to be considered. To capture important properties of substrate noise we consider frequency-dependent sensitivity of analog blocks and noise injection model for noisy digital blocks. We use experimental substrate noise simulations to build our models, and give suggestions how to estimate noise parameters for building blocks of MS-SOC.

I. INTRODUCTION Fabricating entire electronic systems on a single chip is a solution to increasing demand for higher speed, improved performance, increased reliability and cost-effective design created by continuous scaling of integrated circuit technologies. In this research we focus on Mixed-Signal System-on-Chips (MS-SoCs) that are composed of digital and analog blocks (cores), usually pre-designed, called IP (Intelectual Property) cores. Depending on the specification level IPs can be soft (described in Verilog, VHDL or another high-level language) firm (netlist description) or hard (layout description). The common-substrate has introduced new difficult to solve design problems. Some of the most challenging problems [1], [2] are related to performance degradation of the analog blocks that experience various types of noise generated mostly by switching of digital circuits and instability of P/G lines transmitted through the common silicon substrate. In the early stages of SoC design a number of details like layout, electrical parameters, power consumption, peak supply current, switching activity, etc might only be known for hard-IPs, and not much information, beyond functional specification and area estimation, is known for firm- and soft-IPs. Detailed substrate noise specifications are rarely

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available even for layout-defined blocks. At early design planning, when block noise properties are only known to a limited extent, high accuracy of noise analysis is unnecessary, but prediction of noise properties is a must. A simplified approximated approach can produce valuable results more reliably than commonly used trial-and-error manual techniques and can help avoid costly iteration of physical synthesis stages. Finding good acceptable solutions require extensive multi-objective numerical optimizations. Two major types of substrate are used by the semiconductor industry to fabricate integrated circuits: lightly-doped and heavily-doped (with a thin epitaxial layer on top). There are well-established noise models for epitaxial-type substrates [3], [4], when blocks’ layout information is available. Because of its complexity however, evaluation of the substrate noise in lightly-doped substrate, the one preferred in mixed signal and RF circuits [2], is a much bigger challenge. For the lightly-doped substrate, the single-node simplification, used for heavily-doped substrate, that allow to treat all substrate noise sources as if they were connected to a single node represented by the low-resistive substrate cannot be used. In the case of lightly-doped substrates each IP core should be considered at least as a separate noise source connected to a specific substrate area (substrate port). To deal with this problem some known detailed analysis methods [2], [5] could be applied. These methods unfortunately require extensive computational efforts, detailed block noise descriptions, limited only to small designs, and therefore not applicable to large and not completely defined MS-SOCs. Another difficulty lays in how to predict parameters related to substrate noise, if no detailed information about the layout of a core is available, or how to model noise performance for large circuits. We should clearly understand that all the early predictions are by their nature only bare approximations, and it is very unlikely if at all, one could precisely predict noise performance of an unspecified blocks. Early predictions if correctly evaluated, enable however, the most efficient

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system optimization, because it can be done at the very beginning of the design process when many possible alternative solutions are available for a designer. In this paper, we describe a proposed frequencydependent models for sensitivity of the analog cores, and noise injection model for digital cores based on early evaluation of supply noise. The remainder of this paper is organized as follows. Section II describes key assumptions and model development methodoly. Section III discusses noise evaluation in MS-SOCs. Section IV and V provide example of numerical calculation and final conclusions.

For example, a typical low-quality operational amplifier with the sensitivity characteristic as the first one of shown in Table I has: SH=1e-3 to 1e-4, fH=10 to 100 Hz. To represent an early noise sensitivity specification for all analog blocks in a typical MS-SOC it is sufficient to consider only few typical configurations, and next perform SPICE-like simulations. We assume the body (substrate) terminals of the most sensitive devices to be at the inputs. TABLE I.

BASIC FUNCTIONAL CLASSIFICATION OF ANALOG BLOCKS

Function

II. ASSUMPTIONS AND METHODOLOGY

Biasing or lowfrequency circuits

To develop early-prediction noise models that are based on limited, or not available block layout information we need to make the following assumptions: 1) Substrate noise is only due to power/ground (P/G) supply network, 2) The digital blocks are sources of noise, and only analog blocks are sensitive to substrate noise, 3) Noise and sensitivity models are frequency-dependent. Recently published works [6], [7] report that the major source of substrate noise is power/ground noise (bounces). At early design stage, only this dominant component can be predicted with reasonable accuracy. Except some special cases (high power and RF blocks) the analog blocks do not generate significant noise. To achieve a good approximation of a real situation, both measures are approximated by frequency-dependent functions.

Piecewise Linear Approximation of Sensitivity Characteristic Sensitivity (S)

SH(dB)

Frequency

fH Base-band circuits

Sensitivity (S)

SH(dB)

SL(dB) Selective RF circuits

Frequency

fH1

fH2

fL3

Sensitivity (S)

SH(dB)

We only consider lightly doped substrates because they are prefered for MS-SOCs. A. Analog Blocks In [8], a center of noise gravity was introduced and successfully used to represent the average noise properties of an analog block. The center can be easily identified in a region containing the most sensitive components of an analog block. It is important to underline, that physical location of the center within the block can be determined even at early stages of the design flow. Typically, the center is located close to the input pins of the block [1]. By identifying the center of noise, it is possible to represent noise properties of the analog block, with reasonable accuracy, by a single electrical node located at that center. A proper noise modeling demands a frequency-dependent description of the block sensitivity. In our approach we define the sensitivity to substrate noise as the transfer function between the body terminals of the most sensitive devices and the output of the analog block. In general, analog blocks have different sensitivity characteristics. To simplify initial experiments we propose a simple classification of the analog blocks, as shown in Table I, based on piecewise linear approximations of real sensitivity characteristics. Parameters specified in the table: the sensitivity limits SH and SL, characteristic frequencies fH(1),(2) and fL(1),(2), can be predicted in advance for soft and firm IPs, long before IPs are completely designed at the layout level.

Frequency

SL(dB) fL1 fH1

fH2 fL2

B. Modeling of Noise Injection To evaluate MS-SOC performance degradation due to substrate noise, the amount of noise injected into the substrate should be known. Based on the previously discussed assumptions, only substrate noise due to supply noise (P/G bounce [6], [7]) is considered. A simple circuit model, shown in Fig. 1 [7], can be used to capture the most important noise injection paths. The current source ISup represents switching activity of the digital core. The remaining devices represent parasitics associated with a package, internal (on-chip) supply distribution network, and the digital IP core. Most parameters can be predicted based on chip design style, a type of the supply network, and a packaging style. The most difficult to predict at early design stage is the switching activity ISup. It is really a challenge to find a good method for accurate enough approximation of switching activity based only on functional soft IP core specification. To overcome this problem we propose to use parameters easily available at early MS-SOC specification, namely the limits for supply bounces and rough P/G network characterization. At early design stages, both the IP cores and P/G supply network are designed simultaneously, but independently.

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External supply

VDD

Package

Lp

+

Internal P/G network RVDD CSup

Lp

RGND

Local VDD CW

A ISup

RC Substrate port Local GND

B

Figure 3. PSD of current impulses ISup. Figure 1. A simplified model of a supply distribution network.

To make P/G network design possible the P/G bounce limits and basic network characterization must be known from the very beginning. In other words, during early design it is assumed, that the final supply network satisfies the assumed supply noise at a given IP core. Supply noise at nodes A and B (Fig. 1) is injected into the substrate via the total depletion capacitance CW of all the n-wells, and the total resistance RC of all the substrate contacts inside the core. The evaluation of the capacitance CW and resistance RC can be done on predictions about the core complexity, a total area of the core, a total of equivalent digital gates, an average substrate contact density per equivalent gate, and an average n-well depletion capacitance per equivalent gate. As a result one can evaluate coupling paths between P/G supply rails and substrate. As mentioned, noise generated by the digital cores can be treated as uniformly injected through the whole area of the core [7]. The important frequency properties of P/G noise are described by using power spectral density (PSD). To explain the method for supply noise PSD evaluation, some representative simulation results are presented in Fig. 2 thru 4. The IP core switching activity ISup is modeled by a series of trapezoidal current impulses with specified rise (tr), fall (tf), and duration (tp) time. We assume a typical P/G supply network with decoupling capacitances CSup. Supply bounces at node A are shown in Fig. 2.

Fig. 4 represents PSD of supply voltage bounces at node A. The bounces are limited in the rise and fall time due to the decoupling capacitance CSup and network parasitics RVDD, LP. As a result the slope of the curves representing PSD (Fig. 4) for all the considered cases is similar at higher frequencies.

Figure 4. PSD of supply voltage bounces at node A.

By comparing curves in Fig. 4 one can conclude, that there are two major kinds of curve shapes that can be used for P/G supply PSD description. TABLE II. Function I/O cores generating P/G bounces with long tr and tf loaded with big capacitances

BASIC DIGITAL IP-CORE CLASSIFICATION Piecewise Linear Approximation of Power Spectral Density (PSD) PSD

No(dB)

N1(dB) Frequency

N2(dB) f=0

Digital cores generating P/G bounces with short tr and tf Figure 2. Power supply bounces at node A.

No(dB)

N1(dB)

PSD of the current impulses ISup is shown in Fig. 3. It can be easily seen that shorter rise or fall time (tr=tf=50ps) of the impulses results in broader spectrum (PSD is becoming almost flat). At low frequencies PSD is proportional to the area under the impulses, so for the longer impulses (tp=500ps) the magnitude of PSD is about 10dB greater.

f1

f2

PSD

Frequency

f0=0

f1

In general, for a typical supply network, PSD of P/G bounces at low frequencies is proportional to the amplitude and duty cycle of the switching current impulses, whereas at higher frequencies PSD is determined mostly by the time

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constant of P/G network and the shortest rise or fall time. Therefore, for the purpose of MS-SOC early noise predictions we propose a basic digital IP core classification as presented in Table II. The PSD parameters presented in Table II, can be approximated based on typical rise and fall times of an equivalent digital gate fabricated at a given technology, and the time constant of the P/G supply network. An example of numerical calculation is presented in Section IV

simulation of a typical OP configuration. The parameters presented in Table II were calculated using the dominant pole (the time constant) of P/G supply network and the shortest rise or fall time specific for the digital blocks. All the digital blocks, except the output buffers, have the second type of characteristic shown in Table II. Substrate coupling (SCi,j in Eqn. (1)) between a pair of blocks was assumed frequency-independent, and described by the formula taken from [8]. Simulation results for 5GHz bandwidth are presented in Table III.

III. NOISE EVALUATION In order to evaluate a substrate noise level SNi at an analog i-th block a cumulative influence of all the neighboring digital cores number j=1, 2,…M is considered. Noise level can be calculated as a sum of products of frequency-dependent analog block sensitivity Si(f), PSD of P/G supply noise Nj(f), and the transfer function SCi,j(f) representing coupling between each pair of blocks. The RMS value of substrate noise is defined by

SN i =

∑ ∫ M

freq _ high

j

freq _ low

(S ( f ) ⋅ SC i

( f ) ) N j ( f )df 2

i, j

(1)

where freq_high and freq_low are frequency limits of interest. In general, coupling between blocks is frequency dependent, but because PSD of supply noise is hardly limited in frequency by decoupling capacitances, it can be assumed that the coupling is frequency-independent up to 5-7GHz. A good approximation for frequency-independent substrate coupling SCi,j can be found in [8]. IV. NUMERICAL EXPERIMENTS

TABLE III.

Simulation technique Spectre & SCA Simplified approach

RMS of substrate noise at OP 35.8uV 42.1uV

V. CONCLUSIONS A new estimation-based approach for substrate noise evaluation in MS-SOCs is presented. The method can be used at very early design stage, during initial floorplan optimization. Our simulations show that the proposed method typically guarantees the total error below 20% for RMS of substrate noise calculation. Future improvements in calculation accuracy are possible, with better understanding of circuit noise parameters and more precise evaluation of circuit switching activities. REFERENCES [1] C. Soens et al., “RF Performance Degradation Due to Coupling of [2]

To verify the presented ideas for substrate noise evaluation we have analyzed a simple MS-SOC consisting of: 1) a ring oscillator based on inverters, 2) a frequency divider based on D-type flip-flops, 3) a set of output buffers loaded with relatively big capacitances, and an analog block – operational amplifier (OP). We assumed a PLCC 44 package with an average inductance and resistance per pin 6.2nH and 3Ω. All the blocks were synthesized in AMS 0.35um CMOS technology using standard cell components with a typical rise and fall times about 60ps. The on-chip P/G supply network using a metal layer with sheet resistance 100mΩ/sqr. has the dominant time constant about 100ps. We have done two kinds of calculations, one for a complete circuit (detailed synthesized layout) using Spectre and Substrate Coupling Analysis (SCA) tools from Cadence environment, and the second simplified calculations based on the method outlined in this paper. For the simplified approach all the blocks were characterized by means of sensitivity (Table I) and supply PSD (Table II). Sensitivity to substrate noise of OP was determined by means of

COMPARISON OF SIMULATION TECHNIQUES

[3] [4]

[5] [6]

[7]

[8]

Digital Swithing Noise in Lightly Doped Substrates,” Proc. Southwest Symposium on Mixed-Signal Design, 2003, pp. 127-132. E. Charbon R. Gharpurey, P. Miliozzi R. G. Meyer, A. SangiovanniVincentelli, “Substrate Noise, Analysis and Optimization for IC Design,” Kluwer Academic Publishers, 2003. M. Van Heijningen et al., “Analysis and Experimental Verification of Digital Substrate Noise Generation for Epi-Type Substrates,” IEEE J. Solid-State Circ., vol. 35, pp. 1002-1008, 2000. M. Van Heijningen et al., “Substrate Noise Generation in Complex Digital Systems: Efficient Modeling and Simulation Methodology and Experimental Verification”, IEEE Journal of Solid-State Circuits, vol. 37, pp. 1065-1072, 2002. J. Kanapka, J Phillips, J White, “Fast Methods for Extraction and Sparsification of Substrate Coupling”, Proc. IEEE DAC’00. A. Nardi, H. Zeng, J. L. Garrett, L. Daniel, A. L. SangiovanniVincentelli, “A Methodology for the Computation of an Upper Bound on Noise Current Spectrum of CMOS Switching Activity,” Proc. IEEE ICCAD’03, pp. 778, 2003. J. F. Osorio, L. Elvira, F. Martorell, J.L. González, X. Aragonès, “Substrate Noise Macro-Modeling of Digital Cores,” Proc. XVIII of Conference on Design of Circuits and Integrated Systems, DCIS’03, 2003, 75-80. G. Blakiewicz, M. Jeske, M. Chrzanowska-Jeske, “ Substrate Noise Optimization in Early Floorplanning for Mixed Signal SOCs”, Proc. IEEE SOCC’04.

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