Modelling And Evaluation Of Substrate Noise Induc

Modelling and evaluation of substrate noise induced by interconnects F. Martorell, D. Mateo and X. Aragone`s Abstract: Interconnects have received attention as a source of crosstalk to other interconnects, but have been ignored as a source of substrate noise. The importance of interconnect-induced substrate noise is evaluated in this paper. A known interconnect and substrate model is validated by comparing simulation results to experimental measurements. Based on the validated modelling approach, a complete study considering frequency, geometrical, load and shielding effects is presented. The importance of interconnect-induced substrate noise is demonstrated after observing that, for typically sized interconnects and state-of-the-art speeds, the amount of coupled noise is already comparable to that injected by hundreds of transistors. The need to include high-frequency effects in the model is also discussed, together with accuracy trade-offs.

1

Introduction

Coupling through the silicon substrate in submicron integrated circuits is known to be a severe source of problems and performance limitation. The trend towards SoC integration, where highly sensitive analogue sections including RF receivers, GHz oscillators and huge digital processing sections coexist in the same die, increases concern about this problem. As a consequence, there is an urgent demand for accurate CAD tools which allow prediction of substrate noise limitations at the design stage. These tools must take into account the most important mechanisms of noise injection to the substrate in current and near-future technologies. In the last decade there has been an effort to determine the most significant sources of substrate noise [1, 2] and provide models and extraction tools for them [3 – 5]. Nevertheless, as signal frequencies move into microwave ranges, the sources of noise and models must be revisited, and the extraction tools adapted to the new conditions. In recent years, tools which extract substrate parasitics have been commercialised, and their performance and accuracy are being progressively improved. These tools are often based on the finite-difference method, and obtain a substrate model consisting of a mesh of impedances between circuit-substrate ports. The mesh of impedances can then be included as a subcircuit in a netlist for a full-circuit analogue simulation. The extracted substrate mesh includes ports wherever a noise injection or reception point is expected. These are usually transistors and substrate contacts. Other noise injection points are commonly ignored, although their importance has not been demonstrated to be negligible.

q IEE, 2003 IEE Proceedings online no. 20030828 doi: 10.1049/ip-cdt:20030828 Paper received 19th May 2003 The authors are with the Electronic Engineering Dept., Universitat Polite`cnica de Catalunya Campus Nord. Edifici C4. Jordi Girona, 1-3. 08034 Barcelona (Spain) 338

These include coupling from large metal areas like capacitors, pads and interconnects. Intuition suggests that long interconnect lines driving GHz switching clocks may be a significant source of noise coupled to substrate, and that coupling between these interconnects and substrate is worth modelling. Up to now, there has been no known numerical study evaluating this source of coupling. In this paper, we model this coupling with a RC distributed interconnect model linked to a substrate mesh extracted with SubstrateStorme [6]. The interconnect-substrate model has been validated by comparing with measurements on test structures. 2

Modelling coupling from interconnects

Substrate extraction tools based on the finite-difference method obtain a model consisting of a mesh of impedances between circuit ports. In circuit extraction, interconnects are usually modelled ideally as a single node, in the best of cases capacitively coupled to ideal ground. Here, we wish to couple the interconnects to the substrate mesh, and we use the classical distributed R-C model illustrated in Fig. 1 [7], which is now referenced to substrate instead of ideal GND. Each interconnect segment of length DL is instanced as two serial resistors R and a capacitance C coupled to a port of the substrate model. The values of R and C can be computed from geometrical and technology information, as DL=2 W C ¼ Carea DL  W þ Cperim 2DL R ¼ RA

ð1Þ

where DL and W are the length and width of the segment, RA is the sheet resistance, and Carea and Cperim are respectively the area and perimeter capacitances. The distributed RC model does not include high-frequency effects such as inductance or skin-effect. Their importance will be discussed later in this paper. We have implemented our proposed interconnect model in the flow of the substrate extraction tool SubstrateStorme from Cadence [6], using a 0.35 mm technology design kit. IEE Proc.-Comput. Digit. Tech., Vol. 150, No. 5, September 2003

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The pads at the left (B) of the lines have no direct contact to the substrate, and are coupled only through their parasitic capacitance. The pads have been accessed with GSG probes and consequently are escorted by two other pads connected to ground, as seen in Fig. 2. The whole structure is enclosed inside a grounded ring of substrate contacts.

3.2 Measurement results

Fig. 1 Equivalent circuit model for an interconnect coupled to substrate

This tool extracts a substrate model consisting of a mesh of resistances between access ports, which is valid for frequencies up to some GHz. We have created new layout layers which allow us to define which interconnects we wish to extract, and the segment divisions in each interconnect. The extraction rules file was modified to identify the selected interconnects and to save important geometrical data. From these data, the resistance and capacitance values were computed according to (1). Then, each interconnect segment was associated to the instance model in Fig. 1, where the R and C are parameterised to the values computed. We also defined the operation of SubstrateStorme to create substrate ports associated to every interconnect segment instance. As a result, we were able to extract the substrate parasitics of any circuit including coupling from interconnects, and to control the accuracy (number of segments) of the interconnect model. 3

Validation of the substrate-interconnect model

The former modelling approach has been validated by comparing AC analysis simulations to experimental measurements on three test structures.

3.1 Description of the test structure Figure 2 shows a photograph of the test structures manufactured in a 3-metal, 0.35 mm technology. The substrate is high-resistive (10 V·cm resistivity), except for a shallow channel-stopper outside active regions. The structures consist of 500 mm long interconnects, connected at both ends to pads to allow probe access. The interconnects are (left to right) 1 mm wide in metal-1 layer, 1 mm wide in metal-3, and 10 mm wide in metal-1, respectively. Near every interconnect there are two 60  60 mm2 pads, upon which coupling will be sensed. The pad at the right (A) of every line is contacted to the substrate, i.e. allows measurement of noise on the substrate surface.

Fig. 2 Test structures implemented in a 0.35 mm technology to measure coupling from interconnects

A HP 8510C network analyser and Picoprobe 40A-150GSG probes were used to measure S-parameters between line ends and the nearby pads. From these measurements, the voltage gain (coupling) between the input and output pads is derived by using Mason’s rule [8], and imposing ZL ¼ Zs ¼ ZO ¼ 50 O: This leads to the simple expression: AV ¼

Vout S21 ¼ Vin 1 þ S11

ð2Þ

This voltage gain determines the amount of noise that reaches the sensor pad (out) coupled through the substrate from the interconnect (in). This voltage gain is compared to that obtained from AC circuit simulations of the test structures extracted as described in Section 2, including a 50 V load at the sensor pad to account for the impedance of the measurement equipment. The parasitic capacitances of all the pads, including those connected to ground, have also been extracted and coupled to the substrate model. Coupling capacitances for the pads and the interconnect model have been obtained from geometrical and technological data with the help of a 2D electromagnetic field solver [9]. Also, a substrate resistivity profile has been reconstructed from the manufacturer’s data. Figure 3 shows the measurement results compared against simulation results for the three test structures, when the far end of the interconnect is left open circuit. Two sets of measurements and simulations are represented, one in which the output is the pad with an ohmic connection to the substrate, and another in which the output is the pad coupled to the substrate through its parasitic capacitance. An excellent agreement between simulation and measurements is verified. The agreement is lost for frequencies near 10 GHz, where the validity of the purely resistive substrate model is lost, and the interconnect starts to acquire transmission-line behaviour. Measurements with the open line present a high reflection coefficient which may lead to inaccurate results. This does not seem to be the case here since measurements were performed on different samples and in different days, giving very little dispersion in all cases. Probe-to-probe coupling

Fig. 3 Voltage coupled from the interconnects to the sensor pads (interconnect is open-ended)

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Fig. 4 Voltage coupled from the interconnects to the sensor pads (interconnect is 50 V loaded)

was also verified to be about 30 dB below the substrate coupling. In spite of this, we repeated the measurements, this time loading the far end of the interconnect with 50 V with the help of a third probe. Results are shown in Fig. 4, again showing excellent agreement with the simulations. Please note that both Fig. 3 and Fig. 4 represent voltages at the sensor pads relative to the voltage at the interconnect input (i.e., relative coupling). This is the reason why the curves in Fig. 3 and Fig. 4 look similar, although in fact absolute voltages were larger in the unloaded interconnect case. Both in Fig. 3 and Fig. 4, a sustained increase of noise coupling with frequency is observed, due to the capacitive nature of the coupling, up to frequencies around 5 GHz. Then, coupling saturates to a level between 40 mV and 15 mV for a 1 V excitation, depending on the interconnect characteristics. These are fairly large noise levels taking into account that the output nodes are low-impedance (due to the 50 V probe connection). 4

Interconnect coupling quantification

4.1 Relative noise level in the substrate Once the modelling approach has been validated, we extend the range of situations studied and quantify the importance of substrate noise induced by interconnects compared to other noise sources. We continue using the layout of the structures studied in the preceding Section, but now remove all the pads except for the two output ones. Figure 5 represents a sketch of the resulting layout. All the remaining

Fig. 6 Noise levels coupled to substrate when a 1 V signal is applied to lines of different widths and metal layers

elements have been extracted and simulated in the same accuracy conditions as in the preceeding Section. Circuit extractions for 1-mm wide and 10-mm wide interconnects laid in metal-1, metal-2 and metal-3 are made. These extractions are simulated in an AC analysis, with the interconnect driving a realistic load consisting of four basic inverters of the 0.35 mm technology used. Noise is sensed on the pad with an ohmic connection to the substrate, which is equivalent to measuring the noise level in the substrate at the pad location. Figure 6 shows the curves obtained, now in a linear scale so as to better appreciate the magnitude of the coupling. Several observations may be drawn from these curves. Firstly, lines with higher capacitance to the substrate (wider interconnect, lower metal layer) present higher coupling levels. Secondly, and most importantly, coupling levels increase from very low levels for tone frequencies below 100 MHz to surprisingly high values at frequencies around and above 1 GHz. The exact coupling levels (up to 50% of the signal in the interconnect) may be a consequence of the particular layout or loading effect, as discussed in Section 5. Nevertheless, the overall observation is that, for tone frequencies above GHz, interconnects couple a very important fraction of their voltage to the substrate, which does not happen for frequencies in the MHz range. Appreciable tones of 10 GHz are already found in 2 GHz clocks [10], and tones of 2 GHz are present in clocks well below 400 MHz. Moreover, multi-GHz tones are common in CMOS RF ICs, where substrate coupling is also a concern. Thus, it may be concluded that in contemporary technologies, interconnects induce substrate noise with an intensity that was not known years ago.

4.2 Interconnect-induced noise against transistor-induced noise

Fig. 5 340

Layout of the basic test structure used in the simulations

The results in Fig. 6 suggest that interconnects are an important source of substrate noise, particularly in the GHz range. Nevertheless, to give real significance to these numbers, a comparison with other noise sources should be provided. To compare with noise injected by active devices, we have replaced the line with an array of 200 inverters simultaneously switching. The inverters are minimum-size ðW=LNMOS ¼ 1=0:3; W=LPMOS ¼ 2:5=0:3Þ: We drive the transistors with a square signal having 0.1 ns rise/fall time, 1.6 ns period, 3.3 V amplitude. The noise injected is compared against the noise injected by lines 1 mm wide and 500 mm long, in different metal layers. Given that transistor-induced noise is coupled from output drains, we IEE Proc.-Comput. Digit. Tech., Vol. 150, No. 5, September 2003

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Fig. 7 Noise waveforms originated by switching interconnects compared with those originated by 200 simultaneously switching CMOS inverters

also drive the line with 200 inverters in parallel. Thus, the switching waveforms coupled to the substrate are identical in both cases. Transistors or lines have the same fanout of four, and are set in the same layout conditions. For a fair comparison, no substrate contacts are included with the NMOS cells. A BSIM3 model is used to simulate the extracted transistors. Figure 7 shows the time-domain noise waveforms obtained. It can be seen that the noise injected by the lines is between two and three times larger than the noise injected by the 200 inverters. Noise coupled directly from transistors has been traditionally considered to be the second most important source of substrate coupled noise (the first to be switching noise in GND and VDD lines). The results in Fig. 7 indicate that noise injected by global interconnects can be at least as important as noise coupled by important amounts of switching transistors. Therefore, it is a noise source which cannot be ignored by circuit designers nor by CAD developers. 5

Layout and circuit considerations

Essentially, in every situation of coupling between an interconnect and a given node in the layout, we find a coupling capacitance between the interconnect and substrate ðCline Þ; a substrate impedance between the interconnect location and the sensor node location ðZcoup Þ; a substrate impedance between that node and GND contacts ðZgnd Þ; and another impedance between the sensitive node location and the sensitive node itself ðZsens Þ; which may be a resistance (sensitive node is a p-diffusion) or a capacitance (sensitive node is an n-diffusion or metal). First, assume that the sensor node has no external load (‘sensor load’ in Fig. 8 is open circuit). Then, the disturbance sensed is equal to the disturbance present in the substrate location below the pad (node A in Fig. 8), whatever the value or nature of Zsens : The substrate node A sees a path to GND and another path to the voltage source driving the line. The amount of noise in the substrate node is determined by the impedance ratio between those two paths. At low frequencies the impedance to the interconnect is very high due to the series capacitance Cline ; thus the path through Zgnd dominates and hence the low noise appreciated in Fig. 6. At very high frequencies, the capacitance impedance is negligible, and coupling reaches its maximum. At some frequency between these two extremes, the impedances of both paths become comparable and the transition between the two situations is produced. This explains the behaviour seen in Fig. 6. In this unloaded situation, the maximum amount of noise reached at very high frequencies depends on the ratio between Zcoup and Zgnd ; which is essentially determined by the (average) distances between the sensor and the interconnect, and the sensor and ground contacts. Given the symmetry of the test structure in Fig. 5 with respect to the sensor pads, the relative voltages seen in Fig. 6 saturate about 0.5 at very high frequencies. A proportionately scaled version of the test structure would lead to the same maximum coupling, independent of absolute dimensions. On the contrary, the relative position of the sensor node determines the noise level. A different distribution of ground contacts in our test layout could give less worrying results, but a non-ideal ground connection including package parasitics would give worse noise levels [5].

5.1 Geometrical and loading effects Noise levels reached in Fig. 6 may seem amazingly high to some observers, which is a consequence of the layout and loading conditions of the test structures. Nevertheless, the reason for the high levels is not the short distance between the interconnect and the measuring point in Fig. 5 (approximately 100 mm), but the relative distance of the measuring point to the noise source (the interconnect) and quiet ground. To support our discussion, we use the simplified equivalent circuit depicted in Fig. 8.

5.2 Effect of a load impedance in the sensor node

Fig. 8 Simplified equivalent circuit for a noisy interconnect coupled through the substrate to a surface node (bottom half of structure in Fig. 5)

Fig. 9 Noise coupled to a sensitive device through parasitic capacitance, when a 1 V signal is applied to lines of different widths and metal layers

In the preceeding Sections, we have quantified the noise present at the substrate surface. Nevertheless, these noise levels will be attenuated when coupled to a sensitive device,

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both because of the coupling impedance to that device (Zsens in Fig. 8) and because of its load effect (sensor load in Fig. 8). The lower the sensor load and the higher the coupling impedance, the lower the noise levels at the device. In order to quantify how much of the substrate noise is coupled to a sensitive device, we now measure noise on the pad capacitively coupled to the substrate. The parasitic capacitance between the pad and substrate corresponds to the drain junction capacitance of a relatively large transistor, about 68 mm wide. We load the pad with the output of a voltage reference formed with saturated transistors of W=L ¼ 68=0:3; thus replacing the drain junction capacitance of the NMOS by the pad capacitance. This way, we observe how much of the substrate noise is coupled to the voltage reference through the junction capacitance. Figure 9 shows how the effect of the load reduces the noise levels reaching the sensitive node between one and two orders of magnitude (the ratio is not frequency-constant). These noise levels now match the expected amount of substrate-coupled noise, and are consistent with the levels observed in the measurements (Fig. 3), where the output node was loaded with a 50 V impedance.

tool, SubstrateStorme), again resulting in negligible differences. Die thickness was about 500 mm. Measurement and simulation results, for the coupling from the interconnect in metal-1, 1 mm wide, are plotted in Fig. 10, showing the inefficiency of the backside contact and, again, the coincidence between experimental measurements and simulations of our model.

5.4 Shielding effect of lower-layer interconnects

A conductive attachment between the chip backside and the grounded package die paddle has sometimes been suggested as a means to improve substrate grounding. Recalling again the equivalent circuit in Fig. 8, the ground impedance Zgnd would have two contributions: one path to the surface ring of contacts, and one to the grounded backside contact. Nevertheless, the ground impedance reduction is expected to be significant only if highly conductive wafers are used. On the contrary, highly resistive substrates like those in our test structures should be insensitive to this technique, because the substrate impedance to the surface contacts should be much lower than the impedance to the backside. In order to verify this insensitivity, we have performed measurements of the test structures in two different backside conditions. In one case, we attached the samples to a glass support, thus isolating the backside from any electrical conduction. In the other case, the samples were directly mounted on a grounded surface. We measured coupling between the interconnects and the substrate surface contact, and the differences were negligible. Also, we extracted the substrate assuming floating or grounded backside connection (this is allowed for by the substrate parasitics extraction

We have demonstrated the potential of interconnects as substrate noise injectors. Nevertheless, this does not mean that the thousands of interconnects in an IC will all be injecting substrate noise. Those used for local routing are very short, while global nets laid in upper metal layers usually have other nets below, which will shield coupling to the substrate. However, these general rules are not always accomplished, and some long interconnects may be found which inject noise, for example when routing from the digital core to I/O or other circuit sections. Also, it is easy to find wide and non-shielded power-supply lines, which will couple switching noise to the substrate. We wish to quantify how lower-layer interconnects reduce the amount of noise injected to the substrate by upper lines. This will quantify the importance of noise injection in shielded situations or, read in another way, the efficacy of shields to reduce coupling. We now repeat the simulations for the 1 mm wide lines laid in metal-2 and metal-3 layers, now superposed to other lines in all the remaining lower layers. Noisy and shielding interconnects are aligned and have identical dimensions. Thus, fringing fields from the upper line still allow coupling to the substrate. Again, we use a field simulator to obtain the capacitance matrices for these particular situations. We consider three different loading conditions for the shielding lines. A saturated small NMOS driver ðW=L ¼ 1=0:3Þ provides a high impedance load. A large NMOS transistor ðW=L ¼ 100=0:3Þ provides a medium impedance load. A direct connection to GND provides a low impedance load. Figure 11 shows the results in all these conditions, compared with the results with no shield. It may be seen that the shields driven by a high impedance do not reduce the coupling to the substrate significantly. On the contrary, shields driven by large drivers or connected to ground do achieve a significant noise reduction, between 50% and 60% at high frequencies. This reduction, although significant,

Fig. 10 Measurement and simulation results of the substrate coupling introduced by an interconnect, assuming grounded or floating chip backside (substrate is highly resistive)

Fig. 11 Noise levels coupled to substrate when a 1 V signal is applied to 1-mm wide lines in metal-2 or metal-3 (these lines are shielded by lower-layer metal lines, driven by high, medium or low impedances)

5.3 Backside circuit connection

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will probably not be enough to eliminate substrate noise problems. Thus, the conclusions from the plot in Fig. 11 are twofold. First, a single interconnect routed below a noisy line does not eliminate substrate noise injection. Second, to make an interconnect shield effective, it should be grounded and be significantly wider than the switching interconnect, in order also to collect its fringing fields. 6

Model optimisation

6.1 Number of divisions in the model In all the simulation results presented in the preceding Sections, the interconnects were instanced as 500 R-C-R stages like those in Fig. 1, i.e. one stage per micron of interconnect length. This value was taken to ensure maximum accuracy and a valid model. Nevertheless, it is obvious that in a real circuit extraction, such an accuracy level would be prohibitive. Modelling an interconnect with N segments means adding 3N nodes, N capacitors and 2N resistors to the circuit. Moreover, the complexity of the substrate mesh increases quadratically with the number of segments. Therefore, computational efficiency demands reducing the number of interconnect segments as much as possible, with the associated consequence of a loss of accuracy. In order to quantify how much accuracy is lost with a coarser model, the simulation of the test structures has been redone, now reducing the number of segments to 100, 20, 5 and 1 (equivalent to one segment every 5 mm, 25 mm, 100 mm and 500 mm, respectively). The results obtained are shown in Fig. 12, together with the original simulation results and the experimental measurements. It may be seen that a coarser model certainly produces a loss of accuracy, up to a 40% difference with respect to the experimental value. This is a significant figure, but still reasonable if we contemplate the effect of process variations or the expected accuracy of noise prediction in general. In any event, a reasonable compromise may be found between accuracy and computational burden, which is better than not extracting any coupling to the substrate at all. A more detailed study should be performed so as to decide this compromise value, since particular geometry or nonsymmetry could give more importance to the number of model divisions.

6.2 Modelling high-frequency effects All the simulations presented in preceding sections use the distributed RC model for the interconnect introduced in

Fig. 12 Experimental results compared to simulations with interconnect models of different accuracy (length of an interconnect division which is instanced as a RCR stage): metal-1, 1 mm wide

Section 2, and a pure resistive extraction of the substrate. These models are valid for frequencies below the GHz range, but somewhere above that limit high-frequency effects appear and the model has to be revised. Three highfrequency effects may become important in the range of frequencies presented in the experimental measurements (20 GHz): inductive effects and skin effect in the interconnect, and dielectric behaviour of the substrate. In this Section, we discuss the importance of these three effects, and present some results with the improved model. According to transmission line theory, inductive effects for a 500 mm long interconnect become necessary above 15 GHz. Complete discussions of the conditions necessary to choose between distributed RC or RLC models may be found in [10, 11]. We have included inductive effects in our simulations by extending the RC model to an RLC model, which can easily be done without significant computational cost. From S parameter measurements between line ends, we have obtained ABCD parameters and then RLCG values, following the procedure detailed in [12 – 14]. The inductance values obtained at high frequencies are between 1.3 nH/mm and 1.6 nH/mm, which are similar to other measurements results published in [10, 12, 13]. Comparison between experimental and simulation results with the RC and RLC models are shown in Fig. 13. It may be seen that inductive effects start to be appreciable at 5 GHz, but are only significant above 10 GHz. The appreciated effect is a reduction in the amount of noise coupled to the substrate. Simulation results with the RC model underestimated the substrate noise prediction above 10 GHz, and inclusion of inductive effects has increased the differences between experimental and simulation results. Skin effect has not been described as a significant effect in current VLSI technologies, but is expected to appear for frequencies over 10 GHz. It manifests itself as a concentration of current density in the external walls of the conductor, thus reducing its effective cross-section, and increasing resistance. No effective closed-form expressions for resistance calculation including skin effect are available. In [13], an infinite wide conductor is assumed to calculate an expression of its effective resistance, assuming fields concentrated in the bottom surface of the conductor. This expression predicts that sheet resistance of the metal-1 interconnects in our test structures will increase by 45% at 10 GHz with respect to its DC value, while for a metal-3 interconnect, the increase would be 65%. Nevertheless, this expression overestimates the skin effect for typical interconnect widths, while it underestimates it for wide interconnects [15]. Instead of a closed expression, we have used the 2D field solver embedded in the HSPICE circuit simulator [11] to extract the interconnect resistance values including skin-effect. Then, we have repeated the simulations of the test structures, including inductive and skin effects. The result was a very slight decrease of coupling at frequencies over 10 GHz with respect to the RLC simulations shown in Fig. 13. Curves are not represented because they are hardly distinguishable from those in Fig. 13. Our conclusion is that skin-effect does not affect prediction of substrate noise from interconnects, at least for frequencies up to 20 GHz. The last high-frequency effect remaining is the dielectric behaviour of the substrate. According to Maxwell’s theory, displacement current from time-varying electric fields adds to current density from constant electric fields. This results in practice in the following expression for the total current: J ¼ ðs þ jo"ÞE

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ð3Þ 343

Fig. 13

Measurements compared to simulations with and without inductive effects in the interconnect model

Table 1: Comparison of resistive and dielectric components for a high-resistive substrate, at some significant frequencies o1 ¼ 0:1 @ 1.5 GHz o1 ¼ 0:2 @ 3 GHz o1 ¼ 0:5 @ 7.5 GHz o1 ¼  @ 15 GHz

The real part in (3) stands for the resistive behaviour of the substrate, while the imaginary part stands for its dielectric behaviour. Modelling the substrate as a mesh of resistances ignores the dielectric behaviour, which is a valid assumption up to a certain frequency limit. Above that limit, the substrate should be modelled as a mesh of resistances and capacitances. Table 1 shows the relationship between the real and the dielectric components in (3), for some indicative frequencies, assuming a resistive substrate of r ¼ 10 O cm: It can be seen that the error committed when ignoring the dielectric effect can be tolerated for frequencies in the first GHz, but will definitely be of importance for frequencies approaching 10 GHz, and especially above that limit. Unfortunately enough, the version of SubstrateStorme we have used does not allow the inclusion of this dielectric effect in the substrate modelling, thus we have not been able to verify its effect on the coupling simulations. Nevertheless, (3) indicates that the dielectric effect is translated in an increase of effective conductivity of the substrate, and thus an increase of coupling. This coheres with the comparison of experimental measurements and simulations in Fig. 13, which indicate that high-frequency coupling is larger than predicted by the simulations. Thus, we attribute this discrepancy to the pure resistive modelling of the substrate. 7

technology. The validated simulation procedure has been used to evaluate the importance of interconnects as a source of substrate noise. It has been determined that, for typical medium-sized interconnects and GHz speeds, the amount of coupling is very important, exceeding the noise coupled from hundreds of MOS transistors. Like any parasitic coupling through the substrate, the amount of noise received in a circuit node increases with increasing load impedance and relative distance to the noise source and ground. Shielding offered by single lines has been shown to be insufficient to eliminate coupling. Also, we have determined that a low-resolution lumped interconnect model is enough to predict coupling with reasonable accuracy. Three sources of high-frequency effects have been discussed. Skin-effect has been shown to be of negligible importance in our frequency range, while inductive effects should be included in the interconnect model for frequencies above 10 GHz. A discrepancy between our model and measurements remains at high frequencies, which we attribute to the dielectric behaviour of the substrate. From the frequency dependence of our measurements, it is expected that interconnect-induced coupling will gain importance in future technologies, and become a dominant source of substrate noise, an extra source of power dissipation, and a potential reason for circuit malfunctioning. Thus, its consideration by designers and in substrate parasitics extraction tools should be encouraged. 8

Acknowledgments

This work has been supported by Spanish CICYT project TIC 2001-2337. We also wish to thank Olga Boric-Lubecke from Lucent Technologies for her assistance in the measurements, and the SubstrateStorm team from Cadence for their support and collaboration.

Conclusions

A model for noise coupling between integrated signal interconnects and silicon substrate has been proposed and integrated in the SubstrateStorme substrate extraction flow. Simulations of interconnects injecting noise to the substrate show excellent agreement with measurements of several test structures implemented in a 0.35 mm 344

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