Intro To Boundary-scan (jtag)
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Intro to Boundary-Scan (JTAG)
Outline • • • • •
What is 1149.1? 1149.1 Basics Documentation & Resources 1149.1 for the Designer Extended Uses for the TAP Controller
IEEE 1149.1 Boundary-Scan • Facilitates board testing • Provides an on-chip means of controlling and testing pads • Boundary-scan components can also be used for other test purposes: – Logic and RAM BIST control – Scan chain control – Scan wrapper config., test modes, etc.
Intro To Boundary-Scan
4
Intro To Boundary-Scan
5
Pad & Parametric Test • 1149.1 can be used to control and exercise pads independent of the chip core • Leakage on tri-state outputs • Measure voltage and current for output pads driving 0 or 1 • Test logic levels captured by input pads at various voltages
Outline • • • • •
What is 1149.1? 1149.1 Basics Documentation & Resources 1149.1 for the Designer Extended Uses for the TAP Controller
1149.1 Hardware • Test Access Port: 5 pins • TAP Controller – Finite State Machine – Internal registers (Bypass, Instruction, etc.) – Test control logic
• Boundary-Scan Register Chain • Internal Data Registers (Optional)
Boundary-Scan Components I
TMS
O
TDI TCK
TAP Controller
Chip Core
TDO TRST_N
9
TAP Controller Components SO
SI
TDI
Bypass Reg. Instruction Register
TMS TCK TRST_N
Finite State Machine
Instruction Decode
Various TAP Outputs: UpdateDR, CaptureDR, TriState, Etc.
TDO
10
Intro To Boundary-Scan
11
1
TAP Controller State Diagram Test-Logic-Reset
0 Run-Test/Idle
1
1
Select-DR-Scan
0
Select-IR-Scan
0 1
0
Capture-DR
0
1
Capture-IR
0
0
Shift-DR
Shift-IR
1
1
Exit1-DR
Exit1-IR
1
0
0
Pause-IR
1
1 0
Exit2-DR
Exit2-IR
1
1
Update-DR
1
1
0
0
Pause-DR
0
0
0
Update-IR
1
0
Intro To Boundary-Scan
13
Intro To Boundary-Scan
14
BYPASS Instruction • A mandatory instruction • The default instruction for TAPs with no IDCODE register • Short scan path: 1 bit between TDI and TDO • Usually loaded in chips that are idle while other chips on the board are being tested 15
BYPASS Data Path SO
SI
TDI
Bypass Reg. Instruction Register
TMS TCK
Finite State Machine
Instruction Decode
TRST_N TDO
16
EXTEST & SAMPLE/PRELOAD • EXTEST is the “workhorse” JTAG instruction – Sample (“Capture”) & Drive (“Update”) output signals – Sample & optionally drive input signals
• Data is first loaded into boundary register chain with SAMPLE/PRELOAD instruction – Samples inputs and outputs, pass-through – Loads boundary register with data
17
SAMPLE/PRELOAD: Start SAMPLE/ PRELOAD TMS TDI TCK TDO
TAP Controller
Chip Core
BYPASS
TRST_N
18
1
TAP Controller State Diagram Test-Logic-Reset
0 Run-Test/Idle
1
1
Select-DR-Scan
0
Select-IR-Scan
0 1
0
Capture-DR
0
1
Capture-IR
0
0
Shift-DR
Shift-IR
1
1
Exit1-DR
Exit1-IR
0
0
0
Pause-DR
1 0
Exit2-DR
Exit2-IR
1
1
Update-DR
1
0
Pause-IR
1 0
0
0
Update-IR
1
0
Instruction Register Data Path SO
SI
TDI
Bypass Reg. Instruction Register
TMS TCK
Finite State Machine
Instruction Decode
TRST_N TDO
20
1
TAP Controller State Diagram Test-Logic-Reset
0 Run-Test/Idle
1
1
Select-DR-Scan
0
Select-IR-Scan
0 1
0
Capture-DR
0
1
Capture-IR
0
0
Shift-DR
Shift-IR
1
1
Exit1-DR
Exit1-IR
0
0
0
Pause-DR
1 0
Exit2-DR
Exit2-IR
1
1
Update-DR
1
0
Pause-IR
1 0
0
0
Update-IR
1
0
SAMPLE/PRELOAD: UpdateIR SAMPLE/ DATA PRELOAD
TMS TDI TC K TDO
TAP Controller
Chip Core
SMP/PRLD BYPASS
TRST_N
22
1
TAP Controller State Diagram Test-Logic-Reset
0 Run-Test/Idle
1
1
Select-DR-Scan
0
Select-IR-Scan
0 1
0
Capture-DR
0
1
Capture-IR
0
0
Shift-DR
Shift-IR
1
1
Exit1-DR
Exit1-IR
0
0
0
Pause-DR
1 0
Exit2-DR
Exit2-IR
1
1
Update-DR
1
0
Pause-IR
1 0
0
0
Update-IR
1
0
SAMPLE/PRELOAD: CaptureDR Capture (sample)
0
DATA
1
0
1
Mode=0
TMS TDI TC K TDO
0 TAP Controller
Chip Core
1
SMP/PRLD 0
TRST_N 0
1
0
1
24
1
TAP Controller State Diagram Test-Logic-Reset
0 Run-Test/Idle
1
1
Select-DR-Scan
0
Select-IR-Scan
0 1
0
Capture-DR
0
1
Capture-IR
0
0
Shift-DR
Shift-IR
1
1
Exit1-DR
Exit1-IR
0
0
0
Pause-DR
1 0
Exit2-DR
Exit2-IR
1
1
Update-DR
1
0
Pause-IR
1 0
0
0
Update-IR
1
0
SAMPLE/PRELOAD: ShiftDR 01
0 1
1 0
1 0
DATA TMS TDI TCK TDO
0 1 TAP Controller
Chip Core
10
SMP/PRLD 1 0
TRST_N 1 0 1 0
1 0
0 1
0 1
1 0
26
1
TAP Controller State Diagram Test-Logic-Reset
0 Run-Test/Idle
1
1
Select-DR-Scan
0
Select-IR-Scan
0 1
0
Capture-DR
0
1
Capture-IR
0
0
Shift-DR
Shift-IR
1
1
Exit1-DR
Exit1-IR
0
0
0
Pause-DR
1 0
Exit2-DR
Exit2-IR
1
1
Update-DR
1
0
Pause-IR
1 0
0
0
Update-IR
1
0
SAMPLE/PRELOAD: UpdateDR 1
0
1
0
Mode=0 TMS TDI TCK TDO
1 TAP Controller
Chip Core
0
SMP/PRLD 1
TRST_N 1
0
1
0
28
1
TAP Controller State Diagram Test-Logic-Reset
0 Run-Test/Idle
1
1
Select-DR-Scan
0
Select-IR-Scan
0 1
0
Capture-DR
0
1
Capture-IR
0
0
Shift-DR
Shift-IR
1
1
Exit1-DR
Exit1-IR
0
0
0
Pause-DR
1 0
Exit2-DR
Exit2-IR
1
1
Update-DR
1
0
Pause-IR
1 0
0
0
Update-IR
1
0
EXTEST: UpdateIR 1 EXTEST
0
1
0
Mode=1
TMS TDI TCK TDO
1 TAP Controller
0
Chip Core
EXTEST
1
TRST_N 1
0
1
0
30
1
TAP Controller State Diagram Test-Logic-Reset
0 Run-Test/Idle
1
1
Select-DR-Scan
0
Select-IR-Scan
0 1
0
Capture-DR
0
1
Capture-IR
0
0
Shift-DR
Shift-IR
1
1
Exit1-DR
Exit1-IR
0
0
0
Pause-DR
1 0
Exit2-DR
Exit2-IR
1
1
Update-DR
1
0
Pause-IR
1 0
0
0
Update-IR
1
0
EXTEST: CaptureDR Capture (sample)
1
0 1
1
0 1
DATA TMS TDI TCK TDO
1 TAP Controller
0 1
Chip Core
EXTEST 1
TRST_N
1
0 1
1
1 0
32
1
TAP Controller State Diagram Test-Logic-Reset
0 Run-Test/Idle
1
1
Select-DR-Scan
0
Select-IR-Scan
0 1
0
Capture-DR
0
1
Capture-IR
0
0
Shift-DR
Shift-IR
1
1
Exit1-DR
Exit1-IR
0
0
0
Pause-DR
1 0
Exit2-DR
Exit2-IR
1
1
Update-DR
1
0
Pause-IR
1 0
0
0
Update-IR
1
0
EXTEST: ShiftDR 0 1
0 1
0 1
0 1
DATA TMS TDI TCK TDO
0 1 TAP Controller
Chip Core
0 1
EXTEST 0 1
TRST_N 1 1 1 1
0 1
0 1
0 1
0 1
34
1
TAP Controller State Diagram Test-Logic-Reset
0 Run-Test/Idle
1
1
Select-DR-Scan
0
Select-IR-Scan
0 1
0
Capture-DR
0
1
Capture-IR
0
0
Shift-DR
Shift-IR
1
1
Exit1-DR
Exit1-IR
0
0
0
Pause-DR
1 0
Exit2-DR
Exit2-IR
1
1
Update-DR
1
0
Pause-IR
1 0
0
0
Update-IR
1
0
EXTEST: UpdateDR 0 DATA
0
0
0
Mode=1
TMS TDI TCK TDO
0 TAP Controller
0
Chip Core
EXTEST
0
TRST_N 0
0
0
0
36
Intro To Boundary-Scan
37
Intro To Boundary-Scan
38
Intro To Boundary-Scan
39
Intro To Boundary-Scan
40
Intro To Boundary-Scan
41
Intro To Boundary-Scan
42
Intro To Boundary-Scan
43
Outline • • • • •
What is 1149.1? 1149.1 Basics Documentation & Resources 1149.1 for the Designer Extended Uses for the TAP Controller
44
Boundary-Scan Documentation • IEEE Standard: – IEEE Std 1149.1-1990 & 1149.1a-1993: “IEEE Standard Test Access Port and Boundary-Scan Architecture” – IEEE Std 1149.1b-1994: “Supplement to IEEE Std 1149.1-1990 ….” (BDSL) – IEEE Std 1149.1-2001
• “The Boundary-Scan Handbook”, Second Edition (1998), by Ken Parker 45
Outline • • • • •
What is 1149.1? 1149.1 Basics Documentation & Resources 1149.1 for the Designer Extended Uses for the TAP Controller
46
Beyond Board-Test: Extending the TAP Controller • The TAP Controller runs the show for boundary-scan and other TAP-based tests • Some TAP-based test functions have become increasingly complex & specialized – Test signal control – BIST control and capture – Scan shifting
• Most functions are based on TAP registers 47
Static Register: IDCODE • 32 Bits predefined in internal register: – – – –
Version (4 bits) Part Number (16 bits) Manufacturer (11 bits) LSB is set to 1
• Scan out through TDO during IDCODE instruction
1X 0X 1X 0X V P M 1 TDI
0 TDO 1 0V 1P 0M 01
Instruction: BYPASS IDCODE
48
Update-Only: User Register • General-purpose bits • User defines and connects signals • Scan in a value (through TDI) to set • Used for test modes, configurable logic, etc. • No capture capability
TAP State: UpdateDR
1 0 1 1
10 00 10 10 0 0 1 0 1 0 1
TDI
TDO 0 0 0 0
Instruction: SELUSER
49
Capture/Update Register: RAMBIST • Capture and update capability • User-defined signals: – Drive RAMBIST enable – Read RAMBIST results
• Scan in a value (through TDI) to set • Scan out results through TDO
1 1 1 0 R0 TDI
11 01 11 X 1 0 R1 R2
TDO 1 0 1 X
X 4 Instruction: SELRAMBIST RUNRAMBIST
R3 TAP State: ScanDR UpdateDR RunTest CaptureDR ScanDR
50
Outline • • • • •
What is 1149.1? 1149.1 Basics Documentation & Resources 1149.1 for the Designer Extended Uses for the TAP Controller
IEEE 1149.1 Boundary-Scan • Facilitates board testing • Provides an on-chip means of controlling and testing pads • Boundary-scan components can also be used for other test purposes: – Logic and RAM BIST control – Scan chain control – Scan wrapper config., test modes, etc.
Intro To Boundary-Scan
4
Intro To Boundary-Scan
5
Pad & Parametric Test • 1149.1 can be used to control and exercise pads independent of the chip core • Leakage on tri-state outputs • Measure voltage and current for output pads driving 0 or 1 • Test logic levels captured by input pads at various voltages
Outline • • • • •
What is 1149.1? 1149.1 Basics Documentation & Resources 1149.1 for the Designer Extended Uses for the TAP Controller
1149.1 Hardware • Test Access Port: 5 pins • TAP Controller – Finite State Machine – Internal registers (Bypass, Instruction, etc.) – Test control logic
• Boundary-Scan Register Chain • Internal Data Registers (Optional)
Boundary-Scan Components I
TMS
O
TDI TCK
TAP Controller
Chip Core
TDO TRST_N
9
TAP Controller Components SO
SI
TDI
Bypass Reg. Instruction Register
TMS TCK TRST_N
Finite State Machine
Instruction Decode
Various TAP Outputs: UpdateDR, CaptureDR, TriState, Etc.
TDO
10
Intro To Boundary-Scan
11
1
TAP Controller State Diagram Test-Logic-Reset
0 Run-Test/Idle
1
1
Select-DR-Scan
0
Select-IR-Scan
0 1
0
Capture-DR
0
1
Capture-IR
0
0
Shift-DR
Shift-IR
1
1
Exit1-DR
Exit1-IR
1
0
0
Pause-IR
1
1 0
Exit2-DR
Exit2-IR
1
1
Update-DR
1
1
0
0
Pause-DR
0
0
0
Update-IR
1
0
Intro To Boundary-Scan
13
Intro To Boundary-Scan
14
BYPASS Instruction • A mandatory instruction • The default instruction for TAPs with no IDCODE register • Short scan path: 1 bit between TDI and TDO • Usually loaded in chips that are idle while other chips on the board are being tested 15
BYPASS Data Path SO
SI
TDI
Bypass Reg. Instruction Register
TMS TCK
Finite State Machine
Instruction Decode
TRST_N TDO
16
EXTEST & SAMPLE/PRELOAD • EXTEST is the “workhorse” JTAG instruction – Sample (“Capture”) & Drive (“Update”) output signals – Sample & optionally drive input signals
• Data is first loaded into boundary register chain with SAMPLE/PRELOAD instruction – Samples inputs and outputs, pass-through – Loads boundary register with data
17
SAMPLE/PRELOAD: Start SAMPLE/ PRELOAD TMS TDI TCK TDO
TAP Controller
Chip Core
BYPASS
TRST_N
18
1
TAP Controller State Diagram Test-Logic-Reset
0 Run-Test/Idle
1
1
Select-DR-Scan
0
Select-IR-Scan
0 1
0
Capture-DR
0
1
Capture-IR
0
0
Shift-DR
Shift-IR
1
1
Exit1-DR
Exit1-IR
0
0
0
Pause-DR
1 0
Exit2-DR
Exit2-IR
1
1
Update-DR
1
0
Pause-IR
1 0
0
0
Update-IR
1
0
Instruction Register Data Path SO
SI
TDI
Bypass Reg. Instruction Register
TMS TCK
Finite State Machine
Instruction Decode
TRST_N TDO
20
1
TAP Controller State Diagram Test-Logic-Reset
0 Run-Test/Idle
1
1
Select-DR-Scan
0
Select-IR-Scan
0 1
0
Capture-DR
0
1
Capture-IR
0
0
Shift-DR
Shift-IR
1
1
Exit1-DR
Exit1-IR
0
0
0
Pause-DR
1 0
Exit2-DR
Exit2-IR
1
1
Update-DR
1
0
Pause-IR
1 0
0
0
Update-IR
1
0
SAMPLE/PRELOAD: UpdateIR SAMPLE/ DATA PRELOAD
TMS TDI TC K TDO
TAP Controller
Chip Core
SMP/PRLD BYPASS
TRST_N
22
1
TAP Controller State Diagram Test-Logic-Reset
0 Run-Test/Idle
1
1
Select-DR-Scan
0
Select-IR-Scan
0 1
0
Capture-DR
0
1
Capture-IR
0
0
Shift-DR
Shift-IR
1
1
Exit1-DR
Exit1-IR
0
0
0
Pause-DR
1 0
Exit2-DR
Exit2-IR
1
1
Update-DR
1
0
Pause-IR
1 0
0
0
Update-IR
1
0
SAMPLE/PRELOAD: CaptureDR Capture (sample)
0
DATA
1
0
1
Mode=0
TMS TDI TC K TDO
0 TAP Controller
Chip Core
1
SMP/PRLD 0
TRST_N 0
1
0
1
24
1
TAP Controller State Diagram Test-Logic-Reset
0 Run-Test/Idle
1
1
Select-DR-Scan
0
Select-IR-Scan
0 1
0
Capture-DR
0
1
Capture-IR
0
0
Shift-DR
Shift-IR
1
1
Exit1-DR
Exit1-IR
0
0
0
Pause-DR
1 0
Exit2-DR
Exit2-IR
1
1
Update-DR
1
0
Pause-IR
1 0
0
0
Update-IR
1
0
SAMPLE/PRELOAD: ShiftDR 01
0 1
1 0
1 0
DATA TMS TDI TCK TDO
0 1 TAP Controller
Chip Core
10
SMP/PRLD 1 0
TRST_N 1 0 1 0
1 0
0 1
0 1
1 0
26
1
TAP Controller State Diagram Test-Logic-Reset
0 Run-Test/Idle
1
1
Select-DR-Scan
0
Select-IR-Scan
0 1
0
Capture-DR
0
1
Capture-IR
0
0
Shift-DR
Shift-IR
1
1
Exit1-DR
Exit1-IR
0
0
0
Pause-DR
1 0
Exit2-DR
Exit2-IR
1
1
Update-DR
1
0
Pause-IR
1 0
0
0
Update-IR
1
0
SAMPLE/PRELOAD: UpdateDR 1
0
1
0
Mode=0 TMS TDI TCK TDO
1 TAP Controller
Chip Core
0
SMP/PRLD 1
TRST_N 1
0
1
0
28
1
TAP Controller State Diagram Test-Logic-Reset
0 Run-Test/Idle
1
1
Select-DR-Scan
0
Select-IR-Scan
0 1
0
Capture-DR
0
1
Capture-IR
0
0
Shift-DR
Shift-IR
1
1
Exit1-DR
Exit1-IR
0
0
0
Pause-DR
1 0
Exit2-DR
Exit2-IR
1
1
Update-DR
1
0
Pause-IR
1 0
0
0
Update-IR
1
0
EXTEST: UpdateIR 1 EXTEST
0
1
0
Mode=1
TMS TDI TCK TDO
1 TAP Controller
0
Chip Core
EXTEST
1
TRST_N 1
0
1
0
30
1
TAP Controller State Diagram Test-Logic-Reset
0 Run-Test/Idle
1
1
Select-DR-Scan
0
Select-IR-Scan
0 1
0
Capture-DR
0
1
Capture-IR
0
0
Shift-DR
Shift-IR
1
1
Exit1-DR
Exit1-IR
0
0
0
Pause-DR
1 0
Exit2-DR
Exit2-IR
1
1
Update-DR
1
0
Pause-IR
1 0
0
0
Update-IR
1
0
EXTEST: CaptureDR Capture (sample)
1
0 1
1
0 1
DATA TMS TDI TCK TDO
1 TAP Controller
0 1
Chip Core
EXTEST 1
TRST_N
1
0 1
1
1 0
32
1
TAP Controller State Diagram Test-Logic-Reset
0 Run-Test/Idle
1
1
Select-DR-Scan
0
Select-IR-Scan
0 1
0
Capture-DR
0
1
Capture-IR
0
0
Shift-DR
Shift-IR
1
1
Exit1-DR
Exit1-IR
0
0
0
Pause-DR
1 0
Exit2-DR
Exit2-IR
1
1
Update-DR
1
0
Pause-IR
1 0
0
0
Update-IR
1
0
EXTEST: ShiftDR 0 1
0 1
0 1
0 1
DATA TMS TDI TCK TDO
0 1 TAP Controller
Chip Core
0 1
EXTEST 0 1
TRST_N 1 1 1 1
0 1
0 1
0 1
0 1
34
1
TAP Controller State Diagram Test-Logic-Reset
0 Run-Test/Idle
1
1
Select-DR-Scan
0
Select-IR-Scan
0 1
0
Capture-DR
0
1
Capture-IR
0
0
Shift-DR
Shift-IR
1
1
Exit1-DR
Exit1-IR
0
0
0
Pause-DR
1 0
Exit2-DR
Exit2-IR
1
1
Update-DR
1
0
Pause-IR
1 0
0
0
Update-IR
1
0
EXTEST: UpdateDR 0 DATA
0
0
0
Mode=1
TMS TDI TCK TDO
0 TAP Controller
0
Chip Core
EXTEST
0
TRST_N 0
0
0
0
36
Intro To Boundary-Scan
37
Intro To Boundary-Scan
38
Intro To Boundary-Scan
39
Intro To Boundary-Scan
40
Intro To Boundary-Scan
41
Intro To Boundary-Scan
42
Intro To Boundary-Scan
43
Outline • • • • •
What is 1149.1? 1149.1 Basics Documentation & Resources 1149.1 for the Designer Extended Uses for the TAP Controller
44
Boundary-Scan Documentation • IEEE Standard: – IEEE Std 1149.1-1990 & 1149.1a-1993: “IEEE Standard Test Access Port and Boundary-Scan Architecture” – IEEE Std 1149.1b-1994: “Supplement to IEEE Std 1149.1-1990 ….” (BDSL) – IEEE Std 1149.1-2001
• “The Boundary-Scan Handbook”, Second Edition (1998), by Ken Parker 45
Outline • • • • •
What is 1149.1? 1149.1 Basics Documentation & Resources 1149.1 for the Designer Extended Uses for the TAP Controller
46
Beyond Board-Test: Extending the TAP Controller • The TAP Controller runs the show for boundary-scan and other TAP-based tests • Some TAP-based test functions have become increasingly complex & specialized – Test signal control – BIST control and capture – Scan shifting
• Most functions are based on TAP registers 47
Static Register: IDCODE • 32 Bits predefined in internal register: – – – –
Version (4 bits) Part Number (16 bits) Manufacturer (11 bits) LSB is set to 1
• Scan out through TDO during IDCODE instruction
1X 0X 1X 0X V P M 1 TDI
0 TDO 1 0V 1P 0M 01
Instruction: BYPASS IDCODE
48
Update-Only: User Register • General-purpose bits • User defines and connects signals • Scan in a value (through TDI) to set • Used for test modes, configurable logic, etc. • No capture capability
TAP State: UpdateDR
1 0 1 1
10 00 10 10 0 0 1 0 1 0 1
TDI
TDO 0 0 0 0
Instruction: SELUSER
49
Capture/Update Register: RAMBIST • Capture and update capability • User-defined signals: – Drive RAMBIST enable – Read RAMBIST results
• Scan in a value (through TDI) to set • Scan out results through TDO
1 1 1 0 R0 TDI
11 01 11 X 1 0 R1 R2
TDO 1 0 1 X
X 4 Instruction: SELRAMBIST RUNRAMBIST
R3 TAP State: ScanDR UpdateDR RunTest CaptureDR ScanDR
50
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