Ti Jtag Seminar

Topic 8 - JTAG Boundary Scan

JTAG (IEEE 1149.1/P1149.4) Tutorial - Introductory

JTAG (IEEE 1149.1/P1149.4) Tutorial - Introductory

Agenda ■

JTAG

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(IEEE 1149.1/P1149.4)

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Tutorial Introductory

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1997 TI Test Symposium

AL 10Sept.-97 1149.1(JTAG)-Tut.I-1

What Is JTAG? The Increasing Problem of Test Conventional Methods of Test The Boundary-Scan Idea The Boundary-Scan Architecture Typical Applications

(5 minutes) (5 minutes) (10 minutes) (15 minutes) (15 minutes) (15 minutes)

Interconnect Testing Logic Cluster Testing Memory Testing System-Level Test

Real JTAG Applications For More Information Q&A

(10 minutes) (5 minutes) (10 minutes) 1997 TI Test Symposium

AL 10Sept.-97 1149.1(JTAG)-Tut.I-2

JTAG (IEEE 1149.1/P1149.4) Tutorial - Introductory

JTAG (IEEE 1149.1/P1149.4) Tutorial - Introductory

Standard Approach To Test

JTAG / IEEE 1149.1

What Is JTAG?

1997 TI Test Symposium

AL 10Sept.-97 1149.1(JTAG)-Tut.I-3

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Developed by Joint Test Action Group (over 200 SC, test, and system vendors) starting in mid '80's

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Sanctioned by IEEE as Std 1149.1 Test Access Port and Boundary-Scan Architecture in 1990

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Solution: Build test facilities/test points into chips

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Focus: Ensure compatibility between all compliant ICs 1997 TI Test Symposium

AL 10Sept.-97 1149.1(JTAG)-Tut.I-4

JTAG (IEEE 1149.1/P1149.4) Tutorial - Introductory

JTAG (IEEE 1149.1/P1149.4) Tutorial - Introductory

… and Boundary-Scan Architecture

Standard Test Access Port ... User Register

TDO

TDI

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Scan effectively partitions digital logic to facilitate control and observation of its function

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Chip-Internal Scan: Partitions chips at storage cells (latches/ flipflops) to effectively partition sequential logic into clusters of combinational logic

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Boundary-Scan: Partitions boards at chip I/Os for control and observation of board-level nodes

Bypass Register DR

TMS TCK

TAP Controller

IR

Decode Logic

CORE

Instruction Register

TRST*

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4/5-Wire Interface at Chip-Level

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Serial Instruction/Serial Data Port

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Extensible to Include — user-defined instructions — user-defined data registers

AL 10Sept.-97 1149.1(JTAG)-Tut.I-5

1997 TI Test Symposium

AL 10Sept.-97 1149.1(JTAG)-Tut.I-6

1997 TI Test Symposium

JTAG (IEEE 1149.1/P1149.4) Tutorial - Introductory

JTAG (IEEE 1149.1/P1149.4) Tutorial - Introductory

The Incredible Shrinking Board ■

Miniaturization results in loss of test access

The Increasing Problem of Test Yesterday 1997 TI Test Symposium

AL 10Sept.-97 1149.1(JTAG)-Tut.I-7

Today

1997 TI Test Symposium

AL 10Sept.-97 1149.1(JTAG)-Tut.I-8

JTAG (IEEE 1149.1/P1149.4) Tutorial - Introductory

The Ever-Expanding Chip ■

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Can’t Afford Not To Test Cost will increase by a factor of ten as fault finding moves from one level of complexity to the next. The result:

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Yesterday AL 10Sept.-97 1149.1(JTAG)-Tut.I-9

JTAG (IEEE 1149.1/P1149.4) Tutorial - Introductory

Increasing integration at chip level complicates controllability

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Tom orrow ?

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Reduced Profit Margins

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Delayed Product Introduction

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Dissatisfied Customers

C1 1D

1. 2. 3. 4.

Today 1997 TI Test Symposium

Device level Board level System level Field level

1 unit of cost 10 units of cost 100 units of cost 1,000 units of cost 1997 TI Test Symposium

AL 10Sept.-97 1149.1(JTAG)-Tut.I-10

JTAG (IEEE 1149.1/P1149.4) Tutorial - Introductory

JTAG (IEEE 1149.1/P1149.4) Tutorial - Introductory

Conventional Methods of Board Test Functional Test (‘Edge-Connector’ Test)

Conventional Methods of Test AL 10Sept.-97 1149.1(JTAG)-Tut.I-11

1997 TI Test Symposium

AL 10Sept.-97 1149.1(JTAG)-Tut.I-12

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Based on board function, rather than structure

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Test generation primarily manual

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Test access limited to primary I/O only

1997 TI Test Symposium

JTAG (IEEE 1149.1/P1149.4) Tutorial - Introductory

JTAG (IEEE 1149.1/P1149.4) Tutorial - Introductory

Conventional Methods of Board Test

Conventional Methods of Board Test

In-Circuit Test (‘Bed-of-Nails’ Test)

In-Circuit Test (‘Bed-of-Nails’ Test)

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Based on board structure, but limited by chip complexity

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Chip function can be ignored for shorts testing

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Expensive testers and fixtures required

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Test access limited by: — Fine pitch packages — Double-sided boards — Conformal coating — MCMs

Chip function must be considered for continuity test

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Test generation, though automated, requires ICT models

1997 TI Test Symposium

AL 10Sept.-97 1149.1(JTAG)-Tut.I-13

1997 TI Test Symposium

AL 10Sept.-97 1149.1(JTAG)-Tut.I-14

JTAG (IEEE 1149.1/P1149.4) Tutorial - Introductory

JTAG (IEEE 1149.1/P1149.4) Tutorial - Introductory

The Boundary Scan Idea

The Boundary-Scan Idea 1997 TI Test Symposium

AL 10Sept.-97 1149.1(JTAG)-Tut.I-15

CORE

CORE

CORE

Boundary scan cells bound each net, providing for continuity testing

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Observe/Control cells provide for test and normal function

1997 TI Test Symposium

Boundary Scan Method of Board Test

Scan provides a means to arbitrarily observe test results and source test stimulus

CORE

CORE

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JTAG (IEEE 1149.1/P1149.4) Tutorial - Introductory

The Boundary Scan Idea

CORE

‘In-Circuit’ test points moved onto the silicon, creating ‘Virtual Nails’

AL 10Sept.-97 1149.1(JTAG)-Tut.I-16

JTAG (IEEE 1149.1/P1149.4) Tutorial - Introductory

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CORE

Based on board structure; Not limited by chip function/ complexity

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Test access is not limited by board physical factors

CORE

Scan method requires minimal on chip/board resources (pins/nets) CORE

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CORE

J T A G

AL 10Sept.-97 1149.1(JTAG)-Tut.I-17

1997 TI Test Symposium

AL 10Sept.-97 1149.1(JTAG)-Tut.I-18

1997 TI Test Symposium

JTAG (IEEE 1149.1/P1149.4) Tutorial - Introductory

JTAG (IEEE 1149.1/P1149.4) Tutorial - Introductory

Boundary Scan Method of Board Test Chip function need not be considered for board test (shorted/open nets) Test generation is highly automated; Simple ‘In-Circuit Library’ models (BSDL) are vendorsupplied or EDA-generated

1997 TI Test Symposium

AL 10Sept.-97 1149.1(JTAG)-Tut.I-19

CORE

SO (Serial Output) OBSERVE

TEST/DATA MUX

CAPTURE/SCAN MUX

SCAN LATCH/FLOP

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CORE

ID Register TDI

TDO

Boundary scan and other test data registers operate under control of instruction register Data is scanned from TDI to TDO through selected test data register or instruction register under control of Test Access Port (TAP) controller

Bypass Register DR

TMS TCK

TAP Controller

IR

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Decode Logic Instruction Register

TAP operates synchronously to TCK using TMS for state selection

1997 TI Test Symposium

AL 10Sept.-97 1149.1(JTAG)-Tut.I-20

JTAG (IEEE 1149.1/P1149.4) Tutorial - Introductory

The Test Access Port Controller 1 Test Logic Reset 0 1 0 Run Test/Idle

Select DR-Scan

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1

1

Shift-IR

1

1997 TI Test Symposium

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Pause-DR

1

1

Exit 2-DR

0

0

Exit 2-IR

1

1 Update-IR

0

1997 TI Test Symposium JTAG (IEEE 1149.1/P1149.4) Tutorial - Introductory

The Sample/Preload Instruction (REQUIRED)

(REQUIRED) Provides for test external to chip, such as interconnect test Output pins operate in test mode, driven from contents of BSC update latch Input data captured in BSC scan latches prior to shift operation ■ ID Register TDI Bypass Register DR

TMS TCK

TAP Controller

IR

AL 10Sept.-97 1149.1(JTAG)-Tut.I-23

TDO

Shift operation allows test response to be observed at TDO while next test stimulus inserted at TDI

Decode Logic Instruction Register

Following shift operation, new test stimulus transferred to BSC update latches

1997 TI Test Symposium

0

1

AL 10Sept.-97 1149.1(JTAG)-Tut.I-22

The Extest Instruction

CORE

0

Pause-IR

JTAG (IEEE 1149.1/P1149.4) Tutorial - Introductory

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1

Exit 1-IR

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1

Scans consist of 3 primary steps: — CAPTURE — SHIFT — UPDATE

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1

Exit 1-DR

0

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Shift-DR

1

16-state TAP provides 4 major operations: — RESET — RUN-TEST — SCAN-DR — SCAN-IR

Capture-IR

0 0

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0

Capture DR

state transitions occur on rising edge of TCK based on the current state and the TMS input value ONLY

1

Select IR-Scan

0

Update-DR

AL 10Sept.-97 1149.1(JTAG)-Tut.I-21

UPDATE LATCH/FLOP

SI (Serial Input)

JTAG (IEEE 1149.1/P1149.4) Tutorial - Introductory

The Control Architecture

CONTROL

NO (Normal Output)

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NI (Normal Input)

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The Boundary Scan Cell

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Provides means to preload boundary before entry to test mode

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Output and input pins operate in normal mode Input pin data and core logic output data captured in BSC scan latches

CORE

■ ID Register TDI Bypass Register DR

TMS TCK

TAP Controller

IR

AL 10Sept.-97 1149.1(JTAG)-Tut.I-24

Decode Logic Instruction Register

TDO

Shift operation allows test response to be observed while next test stimulus inserted at TDI Following shift operation, new stimulus transferred to BSC update latches

1997 TI Test Symposium

JTAG (IEEE 1149.1/P1149.4) Tutorial - Introductory

JTAG (IEEE 1149.1/P1149.4) Tutorial - Introductory

The Bypass Instruction (REQUIRED)

CORE

ID Register

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Provides for abbreviated scan path through chip

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Output and input pins operate in normal mode

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The one-bit bypass register is selected for scans

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Mandatory that an all-ones value updated into the IR decodes to Bypass, as well as any opcodes which are otherwise undefined

TDO

TDI

Typical JTAG Applications

Bypass Register DR

TMS

TAP IR Controller

TCK

Decode Logic Instruction Register

1997 TI Test Symposium

AL 10Sept.-97 1149.1(JTAG)-Tut.I-25

1997 TI Test Symposium

AL 10Sept.-97 1149.1(JTAG)-Tut.I-26

JTAG (IEEE 1149.1/P1149.4) Tutorial - Introductory

JTAG (IEEE 1149.1/P1149.4) Tutorial - Introductory

Interconnect Test

Interconnect Test

Full B/S Board

Partial B/S Board

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All nets bound by BSC's and/or primary I/O requiring no physical access

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Parallel access reduced to card edge only

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Test generation and application fast and easy

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Not all nets are bound by boundary scan and/or primary I/O, perhaps requiring some ICT access

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Expense and complexity reduced for test generation and test application for chips/nets with B/S access

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Cluster testing may be used to access non-scan nets

J T A G

J T A G

1997 TI Test Symposium

AL 10Sept.-97 1149.1(JTAG)-Tut.I-27

1997 TI Test Symposium

AL 10Sept.-97 1149.1(JTAG)-Tut.I-28

JTAG (IEEE 1149.1/P1149.4) Tutorial - Introductory

JTAG (IEEE 1149.1/P1149.4) Tutorial - Introductory

Logic Cluster Test

Logic Cluster Test

AL 10Sept.-97 1149.1(JTAG)-Tut.I-29

1997 TI Test Symposium

‘LVT18502

Address Memory Array

Buffer

Control

Registered Transceiver Buffer

‘LVT18502 Scan Path IEEE 1149.1

Data

Parallel Data In

AL 10Sept.-97 1149.1(JTAG)-Tut.I-30

TCK TDO TDI

BIST methods (PRPG/PSA) can be used for increased test throughput and near "At-speed" performance

TMS

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Control Logic (Non-Scan)

‘LVT18502

Test response can be captured at B/S inputs

Buffer

Latch

‘LVT18504

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Microprocessor

Deterministic test stimulus (ATPG-generated) can be driven to cluster from B/S outputs

LOGIC "CLUSTER"

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Buffer

‘ABT18502

Random-logic cluster is bound by boundaryscannable chips

‘ABT18502

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1997 TI Test Symposium

JTAG (IEEE 1149.1/P1149.4) Tutorial - Introductory

JTAG (IEEE 1149.1/P1149.4) Tutorial - Introductory

Memory Test

Memory Test ‘ABT18502

Latch ■

Memory array bound by boundary scan chips

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Automatic test patterns can be generated and driven from B/S outputs

Address Memory Array

‘ABT18502

Buffer

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Test response can be captured at B/S inputs

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Transceivers can test for net shorts w/o memory R/W

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BIST methods (PRPG/PSA) can be used for increased test throughput

Control

‘LVT18504

Registered Transceiver

Data

SN74BCT8245 1A1 1B1 1B2 1A2 1B3 1A3 1B4 1A4 2A1 2B1 2B2 2A2 2B3 2A3 2B4 2A4

256 x 8 RAM Array D0 A0 D1 A1 D2 A2 D3 A3 D4 A4 D5 A5 D6 A6 D7 A7

DIR G

WE

TDO TMS

SN74BCT8244 1A1 1Y1 1Y2 1A2 1Y3 1A3 1Y4 1A4 2Y1 2A1 2Y2 2A2 2Y3 2A3 2Y4 2A4 G2 G1 TDO TMS

1997 TI Test Symposium

AL 10Sept.-97 1149.1(JTAG)-Tut.I-31

TDI TCK

SN74BCT8244 1Y1 1A1 1Y2 1A2 1Y3 1A3 1Y4 1A4 2Y1 2A1 2Y2 2A2 2Y3 2A3 2Y4 2A4 G2 G1 TDO TMS

CS

TDI TCK

256 ACCESSES

1,000,000 ACCESSES

IEEE 1149.1 EXTEST & SAMPLE)

Time To Apply Scans Patterns

5.625000 Seconds 512 512

375.00 Minutes 2,000,000 2,000,000

IEEE 1149.1 (with BIST capability)

Time To Apply Scans Patterns

0.000041 Seconds 7 512

< 0.01 Minutes 28,000 2,000,000

MODE

TDI TCK

1997 TI Test Symposium

AL 10Sept.-97 1149.1(JTAG)-Tut.I-32

JTAG (IEEE 1149.1/P1149.4) Tutorial - Introductory

JTAG (IEEE 1149.1/P1149.4) Tutorial - Introductory

System-Level Test

A S P

A S P

A S P

TDO TDI TMS TCK

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TAP-addressable interface unit extends JTAG access beyond board-level

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System-level test

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System design verification

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Sys integration (Mfg test)

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Sys self-test (Field Svc)

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Supports in place board test and board-to-board test

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Allows reuse of device/ board test data

Real JTAG Applications

✦ ASP-Addressable Scan Port Device 1997 TI Test Symposium

AL 10Sept.-97 1149.1(JTAG)-Tut.I-33

1997 TI Test Symposium

AL 10Sept.-97 1149.1(JTAG)-Tut.I-34

JTAG (IEEE 1149.1/P1149.4) Tutorial - Introductory

JTAG (IEEE 1149.1/P1149.4) Tutorial - Introductory

Real Applications of the TAP

Design Verification/Debug ■

■ I

N S

T C

E

R

A

N T

N

E

A

S

L

T

CORE BIST

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Emulation

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Programming

■ TAP

■ TDI

TCK

AL 10Sept.-97 1149.1(JTAG)-Tut.I-35

TMS

Scan access to chips, boards, systems for: — Design verification/debug — Manufacturing test — Hardware/software integration — Field test/diagnostics Access built-in self-test (BIST) Access on-chip/in-circuit emulation (ONCE/ICE) Access in-system programming (ISP) of PLDs/EEPROMs Let your imagination run wild!!!

TDO

1997 TI Test Symposium

Provides control and observation of system under test without need for physical access — Ease of set-up for test —

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Can be used in standard system configuration (no need for card extenders, etc.) Can be used in environmental chambers Can access on-chip emulation for software/debug Can access ISP for code download/offload/ changes 1997 TI Test Symposium

JTAG (IEEE 1149.1/P1149.4) Tutorial - Introductory

JTAG (IEEE 1149.1/P1149.4) Tutorial - Introductory

System Configuration Maintenance

Manufacturing Test ■

ICT

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Provides test and diagnostic capabilities of in-circuit test without need/expense of physical access — Improved fault coverage/diagnostic without large capital expense — Highly automated test generation reduces test development time

J T A G

Provides low-level test access within configured systems for: — In-house system integration — Fielded-system test and diagnostics — Built-in self-test — In-field upgradability via ISP, etc. — Remote field test, diagnostic and upgrade

J T A G

1997 TI Test Symposium

AL 10Sept.-97 1149.1(JTAG)-Tut.I-37

1997 TI Test Symposium

AL 10Sept.-97 1149.1(JTAG)-Tut.I-38

JTAG (IEEE 1149.1/P1149.4) Tutorial - Introductory

JTAG (IEEE 1149.1/P1149.4) Tutorial - Introductory

TI’s JTAG Educational Products

IEEE Standards

Call (214)-638-0333 to ORDER

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Call (800) 678-IEEE to ORDER

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Scan Educator PC-based tutorial with interactive — boundary-scan simulation. FREE download at — http://www.ti.com/sc/data/jtag/scanedu.exe

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IEEE 1149.1 Testability videotapes Two-part video presenting an overview and — instructions for boundary scan. Item No. SATV001 (NTSC VHS) and — SATV002 (PAL VHS), $149 each. In process of converting to MPEG on CD-ROM —

AL 10Sept.-97 1149.1(JTAG)-Tut.I-40

IEEE Std 1149.1-1990 (Includes IEEE Std 1149.1a-1993), IEEE Standard Test Access Port and Boundary-Scan Architecture, ISBN 1-55937-350-4, IEEE order number SH16626.

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IEEE 1149.1 Boundary-Scan

IEEE Std 1149.1b-1994, Supplement to IEEE Std 1149.1-1990, ISBN 155937-497-7, IEEE order number SH94256. —

1997 TI Test Symposium

The official document which specifies the international standard for a test access port and boundary-scan architecture. Informally known as the JTAG standard, it was officially ratified by the IEEE in February 1990. Since, it has been supplemented twice. The first supplement, ratified in June 1993, is included in the referenced document. The second supplement is currently a separate document, as referenced below.

The official document which specifies the international standard for a boundary-scan description language. This supplement to IEEE Std 1149.1-1990 was ratified in September 1994.

1997 TI Test Symposium

AL 10Sept.-97 1149.1(JTAG)-Tut.I-42

JTAG (IEEE 1149.1/P1149.4) Tutorial - Introductory

Tutorials/Handbooks ■

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The Test Access Port and Boundary-Scan Architecture, Colin M. Maunder, Rodham E. Tulloss, ed., IEEE CS Press, ISBN 0-8186-9070-4. — Edited by two principal chairs of the IEEE 1149.1 working group, this Computer Society tutorial compiles several of the seminal papers on boundaryscan along with several invited papers on various topics including applications, implementation, and others. It will primarily be of interest to the design and/or test engineer. The Boundary-Scan Handbook, Kenneth P. Parker, Kluwer Academic Publishers, ISBN 0-7923-9270-1. — Authored by the principal force behind the Boundary-Scan Description Language (BSDL) and an IEEE 1149.1 working group principal as well as a long time manufacturing and design-for-test expert, this is truly considered THE indispensable handbook on boundary scan for the design and/or test engineer. Boundary-Scan Test - A Practical Approach, Harry Bleeker, Peter van den Eijnden, Frans de Jong, Kluwer Academic Publishers, ISBN 0-792-9296-5. — Authored by several JTAG and IEEE 1149.1 working group principals, this book is a ready reference to boundary-scan technology, its benefits, and considerations for design and test managers and engineers.

AL 10Sept.-97 1149.1(JTAG)-Tut.I-43

1997 TI Test Symposium

JTAG (IEEE 1149.1/P1149.4) Tutorial - Introductory

Abbreviations/Acronyms ASIC

Application-Specific Integrated Circuit

IEEE

ASP ATE

Addressable Scan Port Automatic Test Equipment

ISP

Institute of Electrical & Electronics Engineers IR Instruction Register In-System Programming

ATPG BIST

Automatic Test Pattern Generation Built-In Self-Test

JTAG MCM

Joint Test Action Group Multi-Chip Module

B/S BSC

Boundary-Scan Boundary-Scan Cell

Mfg PCB

Manufacturing Printed Circuit Board

BSDL BSR

Boundary-Scan Description Language Boundary-Scan Register

PLD PRPG

Programmable Logic Device Pseudo-Random Pattern Generation

BST CAE

Boundary-Scan Test Computer-Aided Engineering

PSA PWB

Parallel Signature Analysis Printed Wiring Board

DFT DR

Design-for-Test Data Register

SPL SVF

Scan Path Linker Serial Vector Format

DSP EDA

Digital Signal Processing/Processor Electronic Design Automation

TAP TBC

Test Access Port Test Bus Controller

eTBC FPGA

Embedded Test Bus Controller Field-Programmable Gate Array

TCK TDI

Test Clock Test Data Input

HSDL ICE

Hierarchical Scan Description Language In-Circuit Emulation

TDO TMS

Test Data Output Test Mode Select

ICT

In-Circuit Test

TRST UUT

Test Reset Unit Under Test

AL 10Sept.-97 1149.1(JTAG)-Tut.I-46

1997 TI Test Symposium