Boundary_scan_logic.ppt

Digital Boundary Scan Logic

Introduction • Testing a stand-alone chip (not mounted on printed circuit board (PCB)) is relatively easy because all I/O pins are controllable and observable with external test equipment. • Once a chip is mounted on a PCB , the test becomes much more complex . Also difficulties in dealing with multiple-layer boards. • Bed-of-nails (physical probing(check) technique) – Which is conventional method to test the on-board components contacts with PCB

• But in the multi-layer boards, the ability of probing using the Bed-of-nails is too hard.

What is JETAG and JTAG (IEEE standard 1149.1) •

In the mid-1980s, a group of test engineers from several European electronics system companies began to get together to search for possible solutions to the problem of testing surface mount packages and multiple chip modules (MCMs).

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This group, known as the Joint European Test Action Group (JETAG), finally concluded that the best way to address this problem is to create a serial shiftregister around the boundary of the chip similar to scan design to get I/O accessibility of the chip.

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In 1988, JETAG was joined by representatives from North American companies who had also been working on this problem and had come to a similar conclusion. The combined group was renamed the Joint Test Action Group (JTAG).

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Through the efforts of JTAG, the idea of “boundary scan” was formally converted into a test architecture and a set of associated design rules, which were quickly approved by the IEEE as a test standard (Std. 1149.1) in 1990.

Principle of Boundary scan •

A memory element is added on each primary input (input cell) and primary output (output cell) of a chip is called boundary scan cell.

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The collection of boundary-scan cells is configured into two modes – Parallel mode : act as a parallel-in- parallel-out shift register(capture and update) – Serial mode : act as a Serial-in-serial-out shift register(scan)

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parallel load operation(capture) – Input side : •

signal values on PI’s are parallely captured into input cells (IN to R1 if input cell)

– Output side •

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core logic output response is parallely captured into output cells. (core to R1 if output cell) (TDO)

parallel unload operation (update) – Output side •

The captured values of core response in R1 are parallely unload to the PO’s in the output cells (R1 to R2 if output cell).

– Input side •

The captured values of PI’s in R1 are parallely passed into the core logic through R2in the input cells (R1 to core in input cells through R2)

(TDI)

Basic boundary scan cell • basic universal boundary-scan cell known BC_1. • It has four modes of operation: – Normal • Direct path from PI(parallel_in) to PO(parallel_out)

– Update(mode=1) • content of the update hold cell is passed through to PO

– Capture • PI is captured by capture scan cell

– Serial shift • content of the capture scan cell is passed through to SO

Extest • Using the boundary scan cells(BSC), test the interconnect structure between two devices is called Extest. • Parallel-load from driver of chi1 to sensor of chi2 and serial-shift-out from sensor of chip2.

core

o/p cell

i/p cell

Transmitter or Driver: Update register of output cell(R2) Receiver or Sensor Capture register of the input cell(R1)

Intest • Using the boundary scan cells(BSC), test the internal functionality of the device is called Intest. • Parallel load-in from driver to core and parallel capture from core to sensor, then serial-shift-out from sensor

Target Register Modes • Whenever a register is selected to become active between TDI and TDO, it always possible to perform the following three operations on the register – Capture : followed by – Shift : followed by – Update

• The order of the these operations is fixed by the FSM design of the TAP controller.

Contd.

Contd. •

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Test-Logic/Reset – All logic testing is disabled in this state and resets the IR and IR stores default values that select device ID reg. If device ID reg is not present, then it select Bypass reg. Run-Test/Idle – Idle : It retains the last state of the test logic. – Run-Test : During this state, the TAP controller can execute an internal test, such as BIST, previously selected by the instruction register. Select-DR-Scan – This state controls whether to enter the Data Path or the Select-IR-Scan state. Select-IR-Scan – This state controls whether or not to enter the Instruction Path. – The TAPC can return to the Test-Logic-Reset state otherwise. Capture-IR – In this state, the shift register bank in the Instruction Register parallely loads a pattern of fixed values on the rising edge of TCK. – The last two significant bits must always be "01“ checkerboard values for boundary-scan infrastructure(tester) test Shift-IR – In this state, the instruction register gets connected between TDI and TDO, and the parallel captured pattern gets shifted-out on each rising edge of TCK and the instruction available on the TDI pin is also shifted-in to the instruction register.

LVTAP default test starts once it powerd-up (observed from Qualcom stil file)

• The following test done by default in LVTAP – Instruction register test(INSTREG_test) – Bypass reg test(BYPASSREG_test) – Internal Data register Test(INTDR_test)

BYPASSREG_test (observed from Qualcom stil file) (Bypass instruction1: 0000000000000000000000000000) (Bypass instruction2: 1111111111111111111111111111) •

Load IR with BYPASS instruction: 000000000000000000000000000 (it selects the 1-bit Bypass reg).

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Test1: Verify that the TAP FSM can skip the SHIFT-DR state via –

IDLE -> SELECT-DR -> CAPTURE-DR(load default value 0) -> EXIT1-DR -> PAUSE-DR

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Load BYPASS register(1-bit register) with a logic one (1-bit through TDI) : scan-in 1 Compare the standard-imposed(previous(default) loaded) value of logic zero in TDO(scan-out 0). End shifting in PAUSE-DR state Load BYPASS register with a zero(scan-in 0)(Skipping capture-DR state). Compare TDO with previous scanned-in value of one(scan-out 1). End shifting in PAUSE-DR state

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Test2 : Verify that the TAP FSM can skip the IDLE state between two DR-STATES, via –

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PAUSE-DR -> EXIT2-DR -> UPDATE-DR -> SELECT-DR -> CAPTURE-DR -> EXIT1-DR -> PAUSE-DR.

Load BYPASS register with a logic one. Compare BYPASS captured value with the standard-imposed value of logic zero. End shifting in IDLE state Load IR with BYPASS instruction: 1111111111111111111111111111. Load BYPASS register with a logic one. Compare BYPASS captured value with the standard-imposed value of logic zero. End shifting in PAUSE-DR state Load BYPASS register with a zero (Skipping capture-DR state). Compare TDO with previous scanned-in value of one. End shifting in IDLE state

Where to Place Boundary-Scan Cells? • boundary-scan cells are placed on the device in, – digital input ports, – digital output ports, – control lines of bidirectional (IO) ports – tristate (0Z) ports.

• The boundary-scan register is selected by the following instructions – – – –

Extest Sample Preload Intest

Boundary scan cells for Bi-directional pins(IO) • conceptually at least, three boundary-scan cells are required for bi-directional IOs : – one on the input side – one on the output side – one on the control(OEN) of the IO status.

• In practice, the two IO scan cells are usually combined into a single multi- function cell called aBC_7.

input output

Control(OEN)

Boundary-Scan Cells for tri-state (OZ) Pins

• Two boundary-scan cells are required for tri-state pins: – One on the output side – One on the status control signal into the output driver amplifier output

driver control

Application at the Board Level

Testing a boundary scan board •

Step 1. Test the Tester (board-level boundary-scan infrastructure test). – It is done by select only Instruction Register(IR) and capture the least two fixed bits “01” of IR using Capture_IR and shift that captured “01” serially to TDO using Shift_IR.

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Step 2. Test the boundary-scan to boundary-scan interconnect – Use the Extest instruction to select the boundary-scan registers to apply stimulus and capture responses across the interconnect structures between the boundary-scan devices on the board.

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Step 3. Test the Non-boundary-scan region – Apply tests to the non-boundary-scan devices, such as memory devices or unstructured clusters, that can be accessed from the boundary-scan registers of the boundary-scan devices.

infra-structure test • The first test that should be performed for a PCB test is called the infrastructure test. • This test is used to determine whether all the components are installed correctly. • This test take-place by using the last two bits of the instruction register (IR) are always ``01''. • By shifting out the IR of each device in the chain, it can be determined whether the device is properly installed (connected). • This is accomplished(carried-out) by making the TAP controller for IR read.

Tester Hardware • TCK speeds are generally in the region of 10 MHz to 25 MHz. • The stimulus/response patterns along with the correct value-changes on TMS, are stored in RAM devices mounted on the controller card. • It hold the applied stimulus values and collect actual response values for comparison with the expected values.

• Overall, the test-preparation and testapplication software in the PC is controlled under Windows 2000, XP or NT.

Board and System-Level Boundary-Scan Control Architectures • Bus master for chips with boundary scan – (a) ring architecture with shared TMS – (b) ring architecture with separate TMS – (c) star architecture – (d) multidrop architecture – (e) hierarchical architecture.

Contd.

Pins for Custom Boundary Cell Support

IEEE_11491 Boundary Cells and Usage

Writing the IOSpecList • To write out an IOSpecList based on the information in the boundary scan data structures, use the following command: – write_io_speclist > iospeclist_file

• The IOSpecList output file contains all ports (functional, test, and TAP) in the design and specifies the type and location of the boundary scan cells to be inserted on all the functional ports.It also contains information for all JTAG instructions.

BSDL (Qualcomm) • BSDL contains information about the boundary scan structure of a component (chip). • It is used to check whether the component is compliant (accommodate) to the IEEE 1149.1 standard. • It can be used in automatic generation of board tests for the ATE. • It can be used to synthesize the standard 1149.1 circuit.

Various ports and #boundary scan cells(BSC) • • • • •

In : input only pin -> 1 BSC Buffer : A 2-state output only pin -> 1 BSC Out : A 3-state output only pin -> 2 BSC INOUT : A Bidirectional pin -> 3 BSC Linkage : Power,Ground,Analog,No-connect pins -> No BSC