Dell Latitude E7240 (compal La-9431p).pdf
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A
B
C
D
E
COMPAL CONFIDENTIAL MODEL NAME : VAZ50 PCB NO : LA-9431P (DAA00005Z10) BOM P/N : 4319LL31LXX
1
1
GPIO MAP: 3.0C
Goliad 12"
2
2
Haswell ULT
2013-05-17 3
4
REV : 1.0 (A00) @ : Nopop Component 1@ : M/B 8M SPI ROM Component SPI on MB 2@ : TAA/B 8M SPI ROM EMC@ : EMI & ESD & RF Component Vpro 1@/4@/EMC@/ XDP@ : XDP Component 3@/EMC_3@ CONN@ : Connector Component non-Vpro 1@/EMC@/ 3@ : Delete componet for cost down BOM 3@/EMC_3@ EMC_3@ : Delete EMC component for cost down BOM 4@ : M/B 4M SPI ROM Component non-Vpro 5@ : TAA/B 4M SPI ROM (cost down) 1@/EMC@ 7@ : M/B for 8M SPI(Reverse)
TAA
3
2@/5@/EMC@ 3@/EMC_3@ 2@/5@/EMC@ 3@/EMC_3@ 2@/5@/EMC@/ 4
DELL CONFIDENTIAL/PROPRIETARY Compal Electronics, Inc. PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
MB PCB Part Number
Description
DAA00005Z10
PCB 0VM LA-9431P REV1 M/B 4
A
B
C
D
Title
Cover Sheet Size
Document Number
Date:
Friday, May 17, 2013
Rev 0.3
LA-9431P Sheet E
1
of
59
A
B
C
D
E
Goliad12 Block Diagram
Memory BUS (DDR3L)
DDRIII-DIMM X2
1333/1600MHz
eDP CONN
1
BANK 0, 1, 2, 3, 4 ,5 ,6 ,7
eDP
REV. type
PAGE 22
PAGE 18 19
DP
Mini-DP
1
PAGE 27
USB2.0[3]
Camera PAGE 22
DP
For MB/Dock DP Video Switch IDT VMM2320 VGA
Pericom PI3VDP12412
DP
INTEL HASWELL ULT
DDI2
PAGE 27
PAGE 21
Trough eDP Cable
DOCKED_LIO_EN
SLGC55594A USB2.0[0]
NX3DV221
SW_USB2.0[0] USB POWER SHARE PAGE 33
USB20 Switch PAGE 33
BGA CPU DOCKING PORT 2
HDMI
HDMI CONN PAGE 23
Reduce Level ShifterPAGE 23
USB
PAGE 6~17
Card reader
SD4.0 PAGE 30
O2 Micro OZ777FJ2LN PAGE 30
PCIE4
WLAN+BT/ 60GHz
PAGE 28
PAGE 31
3
USB2.0[2] LAN SWITCH PI3L720
LPC
TDA8034HN
RFID RJ45 PAGE 35
Fingerprint CONN
FP_USB
Full Mini Card mSATA PAGE 25
2
USB3.0/2.0 PAGE 35
32M 4K sector
INT.Speaker HDA Codec ALC3226
PAGE 26
Vol bottom SW
PAGE 26
W25Q32FVSSIQ PAGE 7
Touch Screen Conn
SMSC SIO ECE5048
CPU XDP Port
DAI
PAGE 9
To Docking side
Trough eDP Cable
Automatic Power Switch (APS) PAGE 9
Dig. MIC
PAGE 36
USB2.0[4]
WiFi ON/OFF
PAGE 22
PAGE 35
Trough eDP Cable
PAGE 29 USH board
PAGE 37
IO/B
DC/DC Interface
SMSC KBC MEC5075
FAN CONN
3
PAGE 40
Combo Jack
PAGE 22
USH BCM5882
PAGE 35
PAGE 33
DOCK _USB2.0[5] DOCK_USB3.0[3]
PAGE 20 Near Field Communications con
64M 4K sector
USB2.0[6]
PAGE 28
Transformer
W25Q64FVSSIQ
PAGE 29
SATA2
Smart Card
PAGE 33
USB3.0/2.0
HD Audio I/F SATA0 USB2.0[7]
Discrete TPM AT97SC3204
PAGE 31
USB3.0/2.0+PS
IO/B
PCIE6_L0
Full Mini Card WWAN+mSATA
SW_USB2.0[5] SW_USB3.0[3]
USB3.0[1]
SPI
PCIE3
USB3.0[2]
USB2.0[1]
PCIE5_L0
PCI Express BUS
Intel Clarkville I218LM
DOCK _USB2.0[0]
USB2.0[5] PI3USB3102 USB3&2 Switch USB3.0[3] PAGE 32
PAGE 34
DAI DOCK_USB3.0[3] SATA1 DOCK_USB2.0[0] DOCK_USB2.0[5]
DOCKED
DDI1
BC BUS
PAGE 39
PAGE 37
Power On/Off SW & LED PAGE 40
4
KB and TP CONN PAGE 38
4
DELL CONFIDENTIAL/PROPRIETARY Compal Electronics, Inc. Title
Block Diagram Size
Document Number
Rev 0.3
LA-9431P Date: A
B
C
D
Friday, May 17, 2013
Sheet E
2
of
59
5
4
3
2
1
POWER STATES Signal
SLP S3#
SLP S4#
SLP S5#
SLP A#
M PLANE
SUS PLANE
RUN PLANE
S0 (Full ON) / M0
HIGH
HIGH
HIGH
HIGH
ON
ON
ON
ON
ON
S3 (Suspend to RAM) / M3
LOW
HIGH
HIGH
HIGH
ON
ON
ON
OFF
OFF
S4 (Suspend to DISK) / M3
LOW
LOW
HIGH
HIGH
ON
ON
OFF
OFF
OFF
S5 (SOFT OFF) / M3
LOW
LOW
LOW
HIGH
ON
ON
OFF
OFF
OFF
S3 (Suspend to RAM) / M-OFF
LOW
HIGH
HIGH
LOW
ON
OFF
ON
OFF
OFF
S4 (Suspend to DISK) / M-OFF
LOW
LOW
HIGH
LOW
ON
OFF
OFF
OFF
OFF
S5 (SOFT OFF) / M-OFF
LOW
LOW
LOW
LOW
ON
OFF
OFF
OFF
OFF
State
D
ALWAYS PLANE
CLOCKS
USB3.0
PCIE
power plane
+5V_ALW
+3.3V_SUS
+5V_RUN
+3.3V_M
+3.3V_M
+3.3V_ALW
+1.35V_MEM
+3.3V_RUN
+1.05V_M
+1.05V_M
+3.3V_ALW_PCH
+0.675V_DDR_VTT
+3.3V_RTC_LDO
+1.05V_RUN
DESTINATION
USB3.0 1
JUSB3-->Right
USB3.0 2
JUSB1-->Rear left
USB3.0 3
JUSB2-->Rear Right//DOCK
D
PCIE 1 PCIE 2 PCIE 3
LOM
PCIE 4
WLAN (WiGi)
PCIE 5
MMI (CARD READER)
PCIE 6
PM TABLE C
SATA
SATA 3
WWAN(PP/mSATA)
SATA 2
NA
SATA 1
mSATA
SATA 0
DOCK
C
(M-OFF)
+VCC_CORE
USB PORT# State
B
S0
ON
ON
ON
ON
ON
S3
ON
ON
OFF
ON
OFF
S5 S4/AC
ON
OFF
OFF
ON
OFF
S5 S4/AC don't exist
OFF
OFF
OFF
OFF
OFF
HSW ULT
need to update Power Status and PM Table
DESTINATION
0
JUSB1 // E-Dock 1
1
JUSB3
2
WLAN + BT
3
CAMERA
4
USH->SMART CARD
5
JUSB2 // E-Dock 2
6
WWAN
7
TOUCH
B
USH
0
BIO
1
NA
A
A
DELL CONFIDENTIAL/PROPRIETARY Compal Electronics, Inc. PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
Title
Index and Config. Size
4
3
2
Rev 0.3
LA-9431P Date:
5
Document Number Friday, May 17, 2013
Sheet 1
3
of
59
4
3
+3.3V_RUN
D
ADAPTER
1
PWRSHARE_EN# ESATA_USB_PWR_EN#
TPS51212 (PU300)
DOCKED
+1.05V_RUN
2
A_ON
5
G547I2P81U (U35)
USB_SIDE_EN#
G547I2P81U (U32)
G547I2P81U (U52) D
+1.05V_M
TPS22966 (U31)
+5V_USB_ CHG_PWR
+USB_PWR
+USB_SIDE_PWR
MPHYP_PWR_EN
+1.05V_MODPHY
ALWON C
+1.35V_MEM
0.675V_DDR_VTT_ON
+VCC_CORE
C
+5V_ALW
RUN_ON
TPS22966 (U3)
ENVDD_PCH
TPS22966 (U22)
AUX_EN_WOWL
TPS22966 (U22)
3.3V_HDD_EN
SIO_SLP_LAN#
+3.3V_ALW
MCARD_WWAN_PWREN
SUS_ON
TPS22966 (U45)
TPS51285BRUKR (PU100)
APL3512A (U9)
TPS22966 (U46)
TPS22966 (U43)
TPS22966 (U18) B
SUS_ON
B
RT8207 (PU11)
H_VR_EN
TPS51622 (PU500)
A_ON
CHARGER
RUN_ON
+BL_PWR_SRC
PCH_ALW_ON
FDC654P (Q2)
RUN_ON
EN_INVPWR
+3.3V_RUN_VMM
RUN_ON
+1.05V_RUN_VMM
+PWR_SRC
RUN_ON
BATTERY
SI3456DDV (Q125)
+3.3V_ALW_PCH
+5V_RUN _AUDIO +3.3V_M
+3.3V_WLAN
+3.3V_LAN
+3.3V_mSATA_WWAN
+3.3V_HDD
+LCDVDD
3.3V_TS_EN
+3.3V_SUS
3.3V_CAM_EN
+3.3V_RUN
+0.675V_DDR_VTT
+3.3V_RUN _AUDIO
+5V_RUN
+1.05V_RUN
LP2301ALT1G (Q1)
+3.3V_TSP
A
A
+3.3V_CAM
LP2301ALT1G (Q3)
DELL CONFIDENTIAL/PROPRIETARY Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
Title
Power Rail Size
4
3
2
Rev 0.3
LA-9431P Date:
5
Document Number Friday, May 17, 2013
Sheet 1
4
of
59
5
4
3
2
1
2.2K
SMBUS Address [0x9a]
+3.3V_ALW_PCH
2.2K AP2
MEM_SMBCLK
AH1
MEM_SMBDATA
202
2N7002
DIMMA
200
2N7002 1K
PCH D
202
+3.3V_ALW_PCH
1K AN1 AH3
AK1
AU3
SML1_SMBCLK
3A
0ohm
LAN_SMBCLK
28
SML0DATA
0ohm
LAN_SMBDATA
31
LOM
2.2K
+3.3V_ALW_PCH 2.2K
3A
2.2K B4
DOCK_SMB_CLK
A3
DOCK_SMB_DAT
1A
XDP
51
2.2K
B6
1A
D
53
SML1_SMBDATA
A5
DIMMB
200
SML0CLK
0ohm depop
NFC_SMBCLK
0ohm depop
NFC_SMBDATA
NFC
+3.3V_ALW 127 129
DOCKING 30
2.2K C
2.2K 1B
B5
LCD_SMBCLK
A4
LCD_SMBDAT
WWAN
32
+3.3V_ALW
C
1B
2.2K
KBC
2.2K 1C 1C
A56 B59
PBAT_SMBCLK PBAT_SMBDAT
+3.3V_ALW 100 ohm
7
100 ohm
6
BATTERY CONN
2.2K
2.2K A50 1E B53 1E
+3.3V_SUS M9
USH_SMBCLK
L9
USH_SMBDAT
B
USH B
2.2K
2.2K
MEC 5075 2B
A49
CARD_SMBCLK
2B
B52
CARD_SMBDAT
+3.3V_ALW
10K
+3.3V_ALW
10K B50 1G A47 1G
9
CHARGER_SMBCLK
8
CHARGER_SMBDAT
Charger
2.2K 2.2K 2D A
2D
B7 A7
+3.3V_ALW
BAY_SMBDAT BAY_SMBCLK
A
2.2K 2.2K 2A
B7
+3.3V_ALW
Compal Electronics, Inc.
GPU_SMBDAT Title
2A
A7
SMBUS TOPOLOGY
GPU_SMBCLK Size
Document Number
Rev 0.3
LA-9431P Date: 5
4
3
2
Friday, May 17, 2013
Sheet 1
5
of
59
5
4
3
2
1
2
RC1 330K_0402_1%
1
+RTC_CELL
D
+3.3V_ALW_PCH
1
2
@ RC3
INTVRMEN - INTEGRATED SUS 1.05V VRM ENABLE High - Enable Internal VRs Low - Enable External VRs
PCH_AZ_SDOUT 1K_0402_5%
FLASH DESCRIPTOR SECURITY OVERRIDE LOW = ENABLE (DEFAULT) HIGH = DISABLE
2
PCH_RTCX1_R 1 @ RC4
2 0_0402_5%
PCH_RTCX1
2
YC1
CC2 1
1 RC7 +RTC_CELL
CMOS setting
CMOS_CLR1 Shunt
Clear CMOS
Open
Keep CMOS
ME_CLR1
RC8 RC6
1 1
215P_0402_50V8J
1
2
@ ME1
TPM setting
Shunt
Clear ME RTC Registers
Open
Keep ME RTC Registers
1 CC3
2
SHORT PADS~D 2 1U_0402_6.3V6K
1
1
2
HASWELL_MCP_E
UC1E
C
PCH_RTCX2 INTRUDER# PCH_INTVRMEN SRTCRST# PCH_RTCRST#
2 1M_0402_5% 2 220K_0402_5% 20K_0402_5% <9>
1
2
32.768KHZ_12.5PF_Q13FC135000040
C
RC5 10M_0402_5%
15P_0402_50V8J
1
CC1 1
1
2
D
@ RC2 330K_0402_1%
1
PCH_INTVRMEN
AW5 AY5 AU6 AV7 AV6 AU7
RTCX1 RTCX2 INTRUDER INTVRMEN SRTCRST RTCRST
SATA_RN0/PERN6_L3 SATA_RP0/PERP6_L3 SATA_TN0/PETN6_L3 SATA_TP0/PETP6_L3
RTC
PCH_RTCRST#
@ CMOS1 SHORT PADS~D 1 2 1U_0402_6.3V6K
CMOS place near DIMM
<26> <36>
PCH_AZ_CODEC_SDIN0 ME_FWP
1 RC9
AW8 PCH_AZ_BITCLK AV11 PCH_AZ_SYNC AU8 PCH_AZ_RST# PCH_AZ_CODEC_SDIN0 AY10 AU12 2 PCH_AZ_SDOUT AU11 AW10 1K_0402_5% AV10 AY8
HDA_BCLK/I2S0_SCLK HDA_SYNC/I2S0_SFRM HDA_RST/I2S_MCLK HDA_SDI0/I2S0_RXD HDA_SDI1/I2S1_RXD HDA_SDO/I2S0_TXD HDA_DOCK_EN/I2S1_TXD HDA_DOCK_RST/I2S1_SFRM I2S1_SCLK
AUDIO
SATA
SATA_PRX_DKTX_N0_C SATA_PRX_DKTX_P0_C SATA_PTX_DKRX_N0_C SATA_PTX_DKRX_P0_C
J8 H8 A17 B17
SATA_RN1/PERN6_L2 SATA_RP1/PERP6_L2 SATA_TN1/PETN6_L2 SATA_TP1/PETP6_L2
2
CC4
J5 H5 B15 A15
SATA_PRX_DTX_N1_C SATA_PRX_DTX_P1_C SATA_PTX_DRX_N1_C SATA_PTX_DRX_P1_C
<34> <34> <34> <34>
DOCK
<25> <25> <25> <25>
SATA HDD (for Goliad 12 to MSATA)
J6 H6 B14 C15
SATA_RN2/PERN6_L1 SATA_RP2/PERP6_L1 SATA_TN2/PETN6_L1 SATA_TP2/PETP6_L1
F5 E5 C17 D17
SATA_RN3/PERN6_L0 SATA_RP3/PERP6_L0 SATA_TN3/PETN6_L0 SATA_TP3/PETP6_L0
SATA_PRX_mSATATX_N3 SATA_PRX_mSATATX_P3 SATA_PTX_mSATARX_N3 SATA_PTX_mSATARX_P3
<31> <31> <31> <31>
mSATA HDD(for WWAN card)
PCH Rx side need use strap pin to update PCIE +/-
1
RC16 0_0603_5%
<9> <9> <9> <9> <9>
2
@
B
+1.05V_M_JTAG2 RC17
<9>
1 PCH_JTAG_TDI 51_0402_1%
2
1 PCH_JTAG_TDO 51_0402_1%
2
1 PCH_JTAG_TMS 51_0402_1%
2
1 PCH_JTAG_JTAGX 1K_0402_1%
2
1 PCH_JTAG_TCK 51_0402_1%
RC18
PCH_JTAG_TRST# PCH_JTAG_TCK PCH_JTAG_TDI PCH_JTAG_TDO PCH_JTAG_TMS @ T3 @ T4 PCH_JTAG_JTAGX @ T5
PCH_JTAG_TRST# PCH_JTAG_TCK PCH_JTAG_TDI PCH_JTAG_TDO PCH_JTAG_TMS PAD~D PAD~D PCH_JTAG_JTAGX PAD~D
AU62 AE62 AD61 AE61 AD62 AL11 AC4 AE63 AV2
PCH_TRST PCH_TCK PCH_TDI PCH_TDO PCH_TMS RSVD RSVD JTAGX RSVD
A12 L11 K10 C12 U3
SATA_IREF RSVD RSVD SATA_RCOMP SATALED
JTAG
2 SATA_IREF @ RC14 SATA_COMP SATA_ACT#
MPCIE_RST# <31,7> HDD_DET# <25> PCH_GPIO36 <10> mCARD_PCIE_SATA#
+3.3V_RUN
<36>
1 +PCH_ASATA3PLL 0_0402_5% PAD~D T1 @ PAD~D T2 @ SATA_ACT#
1 HDD_DET# 100K_0402_5% mCARD_PCIE_SATA# 1 10K_0402_5%
<40>
SATA Impedance Compensation Rev1p2
+PCH_ASATA3PLL
1
SATA_COMP @ RC10
@ RC22
2 RC11 2 RC12
B
5 OF 19 RC20
V1 MPCIE_RST# U1 HDD_DET# V6 PCH_GPIO36 AC1 mCARD_PCIE_SATA#
SATA0GP/GPIO34 SATA1GP/GPIO35 SATA2GP/GPIO36 SATA3GP/GPIO37
+1.05V_M
2 3.01K_0402_1%
RC19
CAD note: Place the resistor within 500 mils of the PCH. Avoid routing next to clock pins. reference FFRD sch 0.5
reference 479493 figure 7-1
HDA for Codec <26> <26> <26> <26>
PCH_AZ_CODEC_SDOUT
1
2
1
2
PCH_AZ_SDOUT 33_0402_5% PCH_AZ_SYNC 33_0402_5% 2 PCH_AZ_RST# 33_0402_5% 2 PCH_AZ_BITCLK 33_0402_5%
RC23
PCH_AZ_CODEC_SYNC
RC24
1
PCH_AZ_CODEC_RST#
RC25
1
PCH_AZ_CODEC_BITCLK 27P_0402_50V8J @ CC5
A
RC26 EMC@
1 A
2
EMI depop location
DELL CONFIDENTIAL/PROPRIETARY PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 5
4
3
2
Compal Electronics, Inc. Title
MCP(1/12) Size
Document Number
Date:
Friday, May 17, 2013
Rev 0.3
LA-9431P Sheet 1
6
of
59
5
4
3
2
1
+3.3V_RUN HASWELL_MCP_E
1 R2
AF2 AD2 AF4
PCH_CL_CLK1 PCH_CL_DATA1 PCH_CL_RST1#
<11>
SML0CLK SML0DATA PCH_GPIO73 SML1_SMBCLK SML1_SMBDATA
SML1_SMBCLK <37> SML1_SMBDATA <37> PCH_CL_CLK1 PCH_CL_DATA1 PCH_CL_RST1#
2
1
2
1
@ RC29
2
1
2
1
+3.3V_M
U1
<36>
2
SPI_WP#_SEL @ R8
SPI_WP#_SEL
1 2 3 4
SPI_PCH_CS0#_R SPI_DIN64 SPI_PCH_DO2_64
1 R122 1 R123
1 0_0402_5%
1@
/CS VCC DO(IO1) /HOLD(IO3) /WP(IO2) CLK GND DI(IO0) W25Q64FVSSIQ_SO8
8 7 6 5
SPI_PCH_DO3_64 1@ R5 1 SPI_CLK64 1@ R7 1 1@ R9 1 SPI_DO64
2 33_0402_5% 2 33_0402_5% 2 33_0402_5%
2 DDR_XDP_WAN_SMBDAT 10K_0402_5% 2 DDR_XDP_WAN_SMBCLK 10K_0402_5%
+3.3V_M
200 MIL SO8
4@ C6 1 2
32Mb Flash ROM reference PDG0.7
0.1U_0402_25V6 U2
PCH_SPI_CS1# 4@ R14 1 PCH_SPI_DIN 4@ R15 1 PCH_SPI_DO2 4@ R19 1
2
SPI_WP#_SEL @R23 @ R23
2 0_0402_5% 2 33_0402_5% 2 33_0402_5%
SPI_PCH_CS1#_R SPI_DIN32 SPI_PCH_DO2_32
1 0_0402_5%
1 2 3 4
PCH_SPI_DO PCH_SPI_DO
2@ 5@
R11 R12
1 1
2 33_0402_5% 2 33_0402_5%
PCH_SPI_CLK PCH_SPI_CLK PCH_SPI_CS0# PCH_SPI_CS1#
2@ 5@ 2@ 5@
R13 R18 R10 R17
1 1 1 1
2 2 2 2
PCH_SPI_DIN PCH_SPI_DIN
2@ 5@
R22 R41
1 1
2 33_0402_5% 2 33_0402_5%
1 3 5 7 TAA_CLK64 9 TAA_CLK32 TAA_CS0#_R 11 TAA_CS1#_R 13 15 17 TAA_DIN64 19 TAA_DIN32 TAA_DO64 TAA_DO32
33_0402_5% 33_0402_5% 0_0402_5% 0_0402_5%
4@
/CS DO/IO1 /WP/IO2 GND
VCC /HOLD/IO3 CLK DI/IO0
8 7 6 5
SPI_PCH_DO3_32 4@ R16 1 4@ R20 1 SPI_CLK32 SPI_DO32 4@ R21 1
2 33_0402_5% 2 33_0402_5% 2 33_0402_5%
21 23
PCH_SPI_DO3 PCH_SPI_CLK PCH_SPI_DO
1 3 5 7 9 11 13 15 17 19
2 4 6 8 10 12 14 16 18 20
G G
G G
10/100/1G LAN --->
<28> <28> <10,28>
WLAN (Mini Card 2)--->
<31> <31> <31>
MMI---> +3.3V_RUN
WWAN (Mini Card 1)---> 8 7 6 5
DGPU_PWROK MINI2CLK_REQ# MINI1CLK_REQ# MPCIE_RST#
DGPU_PWROK MPCIE_RST#
1
2
1
2
2
1
2
1
RC30
RC34 RC36 RC37 RC38 RC39
22 24
R43 R48 R58 R59
1 1 1 1
2 2 2 2
33_0402_5% 33_0402_5% 33_0402_5% 33_0402_5%
PCH_SPI_DO3 PCH_SPI_DO3 PCH_SPI_DO2 PCH_SPI_DO2
C
XB use 50185-02041-001
2 XTAL24_IN_R 0_0402_5%
<30> <30> <30> <31> <31> <31>
PCH_TPM_LPC_EN +3.3V_RUN CLK_PCIE_LAN# CLK_PCIE_LAN LANCLK_REQ#
1 RC57
PCIECLK_REQ0# 10K_0402_5%
B41 A41 Y5 RC56
1
2 10K_0402_5% CLK_PCIE_LAN# CLK_PCIE_LAN LANCLK_REQ#
C41 B42 AD1 B38 C37 N1
CLK_PCIE_MINI2# CLK_PCIE_MINI2 MINI2CLK_REQ#
CLK_PCIE_MINI2# CLK_PCIE_MINI2 MINI2CLK_REQ# CLK_PCIE_MMI# CLK_PCIE_MMI MMICLK_REQ# +3.3V_RUN CLK_PCIE_MINI1# CLK_PCIE_MINI1 MINI1CLK_REQ#
2
RC55
1
A39 B39 U5
CLK_PCIE_MMI# CLK_PCIE_MMI MMICLK_REQ# 2 10K_0402_5% CLK_PCIE_MINI1# CLK_PCIE_MINI1 MINI1CLK_REQ#
B37 A37 T2
CLKOUT_PCIE_N0 CLKOUT_PCIE_P0 PCIECLKRQ0/GPIO18
XTAL24_IN XTAL24_OUT RSVD RSVD DIFFCLK_BIASREF
CLKOUT_PCIE_N1 CLKOUT_PCIE_P1 PCIECLKRQ1/GPIO19 CLOCK
CLKOUT_PCIE_N2 CLKOUT_PCIE_P2 PCIECLKRQ2/GPIO20
SIGNALS
CLKOUT_PCIE_N3 CLKOUT_PCIE_P3 PCIECLKRQ3/GPIO21
TESTLOW_C35 TESTLOW_C34 TESTLOW_AK8 TESTLOW_AL8 CLKOUT_LPC_0 CLKOUT_LPC_1 CLKOUT_ITPXDP_N CLKOUT_ITPXDP_P
CLKOUT_PCIE_N4 CLKOUT_PCIE_P4 PCIECLKRQ4/GPIO22
A25 B25
2
3 4 YC2 24MHZ_12PF_X3G024000DC1H
XTAL24_IN XTAL24_OUT
K21 M21 C26
CLK_BIASREF
C35 C34 AK8 AL8
MCP_TESTLOW1 MCP_TESTLOW2 MCP_TESTLOW3 MCP_TESTLOW4
AN15 AP15
PCI_CLK_LPC_0 PCI_CLK_LPC_1
CC7 1
18P_0402_50V8J
1 2
2 <29>
ADD EMI solution(EMC)
1 2 3 4
1
TAA Config 2@ 5@ 2@ 5@
TAA_DO3_64 TAA_DO3_32 TAA_DO2_64 TAA_DO2_32
1
2
2 1
C43 C42 U2
1
+3.3V_RUN
RP4
2
+3.3V_M
2 4 6 8 10 12 14 16 18 20
RC44 1M_0402_5%
1
HASWELL_MCP_E
UC1F
@ C76 0.1U_0402_25V6
2
PCH_GPIO73 10K_0402_5% SML1_SMBCLK 2.2K_0402_5% SML1_SMBDATA 2.2K_0402_5% SML0CLK 1K_0402_5% SML0DATA 1K_0402_5%
RC28
W25Q32FVSSIQ_SO8
@ R57 33_0402_5%
B
@ C85 0.1U_0402_25V6
1
1
ACES_50185-02041-001
SPI_CLK64
@ R45 33_0402_5%
2
1
2
Intel PDG 0.9
1 @ RC40 SPI_CLK32
2
PCH_SPI_DO3 PCH_SPI_CLK PCH_SPI_DO CONN@ JTAA1
C
<20>
+3.3V_RUN 1@ C5 1 2
MEM_SMBCLK 2.2K_0402_5% MEM_SMBDATA 2.2K_0402_5%
D
<20>
NFC_SMBDATA
0_0402_5%
0.1U_0402_25V6
2 0_0402_5% 2 33_0402_5% 2 33_0402_5%
<18,19,31,9> +3.3V_ALW_PCH
<28>
NFC_SMBCLK
0_0402_5%
@ RC35
PCH_SPI_CS0# 1@ R3 1 PCH_SPI_DIN 1@ R4 1 PCH_SPI_DO2 1@ R6 1
<18,19,31,9>
DDR_XDP_WAN_SMBDAT
<28>
LAN_SMBDATA
0_0402_5%
@ RC33
Rev1p2
200 MIL SO8
4
LAN_SMBCLK
0_0402_5%
@ RC31
reference PDG0.7
DDR_XDP_WAN_SMBCLK
QC1A DMN66D0LDW-7_SOT363-6
SML0DATA
64Mb Flash ROM
1
QC1B DMN66D0LDW-7_SOT363-6
3
MEM_SMBDATA
<31> <31> <31>
SML0CLK
7 OF 19
6
MEM_SMBCLK
S
R1
CL_CLK CL_DATA CL_RST
C-LINK
PCH_SMB_ALERT#
D
PCH_SPI_DO PCH_SPI_DIN PCH_SPI_DO2 PCH_SPI_DO3
2 PCH_SPI_DO2 1K_0402_5% 2 PCH_SPI_DO3 1K_0402_5% reference PDG0.7
SPI
PCH_SMB_ALERT# MEM_SMBCLK MEM_SMBDATA
S
1
SPI_CLK SPI_CS0 SPI_CS1 SPI_CS2 SPI_MOSI SPI_MISO SPI_IO2 SPI_IO3
AN2 AP2 AH1 AL2 AN1 AK1 AU4 AU3 AH3
D
+3.3V_M
SMBALERT/GPIO11 SMBCLK SMBDATA SML0ALERT/GPIO60 SMBUS SML0CLK SML0DATA SML1ALERT/PCHHOT/GPIO73 SML1CLK/GPIO75 SML1DATA/GPIO74
LPC
G
AA3 Y7 Y4 AC2 AA2 AA4 Y6 AF1
PCH_SPI_CLK PCH_SPI_CS0# PCH_SPI_CS1#
D
LAD0 LAD1 LAD2 LAD3 LFRAME
2
AU14 AW12 AY12 AW11 AV12
LPC_LAD0 LPC_LAD1 LPC_LAD2 LPC_LAD3 LPC_LFRAME#
LPC_LAD0 LPC_LAD1 LPC_LAD2 LPC_LAD3 LPC_LFRAME#
G
<25,29,36,37> <25,29,36,37> <25,29,36,37> <25,29,36,37> <25,29,36,37>
5
UC1G
2 PAD~D T6 PAD~D T7
CC6 1
18P_0402_50V8J
@ @
B
0_0402_5% 22_0402_5% 22_0402_5%
1 1 1
2 RC65 @ PCI_CLK_LPC 2 RC64 EMC_3@ 2 RC66 EMC@
B35 A35
CLK_PCI_DOCK <34> CLK_PCI_LPDEBUG <25>
CLKOUT_PCIE_N5 CLKOUT_PCIE_P5 PCIECLKRQ5/GPIO23
<10>
6 OF 19
Rev1p2
<31,6>
10K_8P4R_5% +PCH_VCCACLKPLL
PCI_CLK_LPC_0 12P_0402_50V8J
2
1 @CC15 @ CC15 PCI_CLK_LPC
PCI_CLK_LPC_1 12P_0402_50V8J
2
1 @CC14 @ CC14
EMC@ RC58 1
2 22_0402_5%
EMC@ RC61 1
2 22_0402_5%
EMC@ RC63 1
2 22_0402_5%
CLK_PCI_TPM_TCM <36>
CLK_PCI_MEC
<37>
2
1
2
1
2
1
2
1
2
MCP_TESTLOW1 10K_0402_5% MCP_TESTLOW2 10K_0402_5% MCP_TESTLOW3 10K_0402_5% MCP_TESTLOW4 10K_0402_5%
<29>
CLK_PCI_5048
1 CLK_BIASREF 3.01K_0402_1%
A
RC45 RC46 RC47 RC50 RC52
A
DELL CONFIDENTIAL/PROPRIETARY PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
For RF request(EMC) Every pin need one gnd by itself 5
4
3
2
Compal Electronics, Inc. Title
MCP(2/12) Size
Document Number
Date:
Friday, May 17, 2013
LA-9431P Sheet 1
Rev 0.3 7
of
59
5
4
D
UC1C <18>
DDR_A_D[0..63]
DDR_A_D0 DDR_A_D1 DDR_A_D2 DDR_A_D3 DDR_A_D4 DDR_A_D5 DDR_A_D6 DDR_A_D7 DDR_A_D8 DDR_A_D9 DDR_A_D10 DDR_A_D11 DDR_A_D12 DDR_A_D13 DDR_A_D14 DDR_A_D15 DDR_A_D16 DDR_A_D17 DDR_A_D18 DDR_A_D19 DDR_A_D20 DDR_A_D21 DDR_A_D22 DDR_A_D23 DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 DDR_A_D28 DDR_A_D29 DDR_A_D30 DDR_A_D31 DDR_A_D32 DDR_A_D33 DDR_A_D34 DDR_A_D35 DDR_A_D36 DDR_A_D37 DDR_A_D38 DDR_A_D39 DDR_A_D40 DDR_A_D41 DDR_A_D42 DDR_A_D43 DDR_A_D44 DDR_A_D45 DDR_A_D46 DDR_A_D47 DDR_A_D48 DDR_A_D49 DDR_A_D50 DDR_A_D51 DDR_A_D52 DDR_A_D53 DDR_A_D54 DDR_A_D55 DDR_A_D56 DDR_A_D57 DDR_A_D58 DDR_A_D59 DDR_A_D60 DDR_A_D61 DDR_A_D62 DDR_A_D63
C
B
AH63 AH62 AK63 AK62 AH61 AH60 AK61 AK60 AM63 AM62 AP63 AP62 AM61 AM60 AP61 AP60 AP58 AR58 AM57 AK57 AL58 AK58 AR57 AN57 AP55 AR55 AM54 AK54 AL55 AK55 AR54 AN54 AY58 AW58 AY56 AW56 AV58 AU58 AV56 AU56 AY54 AW54 AY52 AW52 AV54 AU54 AV52 AU52 AK40 AK42 AM43 AM45 AK45 AK43 AM40 AM42 AM46 AK46 AM49 AK49 AM48 AK48 AM51 AK51
SA_DQ0 SA_DQ1 SA_DQ2 SA_DQ3 SA_DQ4 SA_DQ5 SA_DQ6 SA_DQ7 SA_DQ8 SA_DQ9 SA_DQ10 SA_DQ11 SA_DQ12 SA_DQ13 SA_DQ14 SA_DQ15 SA_DQ16 SA_DQ17 SA_DQ18 SA_DQ19 SA_DQ20 SA_DQ21 SA_DQ22 SA_DQ23 SA_DQ24 SA_DQ25 SA_DQ26 SA_DQ27 SA_DQ28 SA_DQ29 SA_DQ30 SA_DQ31 SA_DQ32 SA_DQ33 SA_DQ34 SA_DQ35 SA_DQ36 SA_DQ37 SA_DQ38 SA_DQ39 SA_DQ40 SA_DQ41 SA_DQ42 SA_DQ43 SA_DQ44 SA_DQ45 SA_DQ46 SA_DQ47 SA_DQ48 SA_DQ49 SA_DQ50 SA_DQ51 SA_DQ52 SA_DQ53 SA_DQ54 SA_DQ55 SA_DQ56 SA_DQ57 SA_DQ58 SA_DQ59 SA_DQ60 SA_DQ61 SA_DQ62 SA_DQ63
3
2
HASWELL_MCP_E
<19>
SA_CLK#0 SA_CLK0 SA_CLK#1 SA_CLK1 SA_CKE0 SA_CKE1 SA_CKE2 SA_CKE3 SA_CS#0 SA_CS#1 SA_ODT0 SA_RAS SA_WE SA_CAS SA_BA0 SA_BA1 SA_BA2 SA_MA0 SA_MA1 SA_MA2 SA_MA3 SA_MA4 SA_MA5 SA_MA6 SA_MA7 SA_MA8 SA_MA9 SA_MA10 SA_MA11 SA_MA12 SA_MA13 SA_MA14 SA_MA15
DDR CHANNEL A
SA_DQSN0 SA_DQSN1 SA_DQSN2 SA_DQSN3 SA_DQSN4 SA_DQSN5 SA_DQSN6 SA_DQSN7 SA_DQSP0 SA_DQSP1 SA_DQSP2 SA_DQSP3 SA_DQSP4 SA_DQSP5 SA_DQSP6 SA_DQSP7 SM_VREF_CA SM_VREF_DQ0 SM_VREF_DQ1
3 OF 19
AU37 AV37 AW36 AY36
M_CLK_DDR#0 M_CLK_DDR0 M_CLK_DDR#1 M_CLK_DDR1
AU43 AW43 AY42 AY43
DDR_CKE0_DIMMA DDR_CKE1_DIMMA
AP33 AR32
DDR_CS0_DIMMA# DDR_CS1_DIMMA#
M_CLK_DDR#0 M_CLK_DDR0 M_CLK_DDR#1 M_CLK_DDR1
<18> <18> <18> <18>
DDR_CKE0_DIMMA DDR_CKE1_DIMMA
<18> <18>
DDR_CS0_DIMMA# DDR_CS1_DIMMA#
<18> <18>
AP32 AY34 AW34 AU34
DDR_A_RAS# DDR_A_WE# DDR_A_CAS#
AU35 AV35 AY41
DDR_A_BS0 DDR_A_BS1 DDR_A_BS2
AU36 AY37 AR38 AP36 AU39 AR36 AV40 AW39 AY39 AU40 AP35 AW41 AU41 AR35 AV42 AU42
DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13 DDR_A_MA14 DDR_A_MA15
AJ61 AN62 AM58 AM55 AV57 AV53 AL43 AL48
DDR_A_DQS#0 DDR_A_DQS#1 DDR_A_DQS#2 DDR_A_DQS#3 DDR_A_DQS#4 DDR_A_DQS#5 DDR_A_DQS#6 DDR_A_DQS#7
AJ62 AN61 AN58 AN55 AW57 AW53 AL42 AL49
DDR_A_DQS0 DDR_A_DQS1 DDR_A_DQS2 DDR_A_DQS3 DDR_A_DQS4 DDR_A_DQS5 DDR_A_DQS6 DDR_A_DQS7
AP49 AR51 AP51
DDR_A_RAS# DDR_A_WE# DDR_A_CAS#
<18> <18> <18>
DDR_A_BS0 <18> DDR_A_BS1 <18> DDR_A_BS2 <18> DDR_A_MA[0..15]
<18>
DDR_A_DQS#[0..7]
DDR_A_DQS[0..7]
UC1D
DDR_B_D[0..63]
<18>
<18>
+SM_VREF_CA +SM_VREF_DQ0 +SM_VREF_DQ1
DDR_B_D0 DDR_B_D1 DDR_B_D2 DDR_B_D3 DDR_B_D4 DDR_B_D5 DDR_B_D6 DDR_B_D7 DDR_B_D8 DDR_B_D9 DDR_B_D10 DDR_B_D11 DDR_B_D12 DDR_B_D13 DDR_B_D14 DDR_B_D15 DDR_B_D16 DDR_B_D17 DDR_B_D18 DDR_B_D19 DDR_B_D20 DDR_B_D21 DDR_B_D22 DDR_B_D23 DDR_B_D24 DDR_B_D25 DDR_B_D26 DDR_B_D27 DDR_B_D28 DDR_B_D29 DDR_B_D30 DDR_B_D31 DDR_B_D32 DDR_B_D33 DDR_B_D34 DDR_B_D35 DDR_B_D36 DDR_B_D37 DDR_B_D38 DDR_B_D39 DDR_B_D40 DDR_B_D41 DDR_B_D42 DDR_B_D43 DDR_B_D44 DDR_B_D45 DDR_B_D46 DDR_B_D47 DDR_B_D48 DDR_B_D49 DDR_B_D50 DDR_B_D51 DDR_B_D52 DDR_B_D53 DDR_B_D54 DDR_B_D55 DDR_B_D56 DDR_B_D57 DDR_B_D58 DDR_B_D59 DDR_B_D60 DDR_B_D61 DDR_B_D62 DDR_B_D63
AY31 AW31 AY29 AW29 AV31 AU31 AV29 AU29 AY27 AW27 AY25 AW25 AV27 AU27 AV25 AU25 AM29 AK29 AL28 AK28 AR29 AN29 AR28 AP28 AN26 AR26 AR25 AP25 AK26 AM26 AK25 AL25 AY23 AW23 AY21 AW21 AV23 AU23 AV21 AU21 AY19 AW19 AY17 AW17 AV19 AU19 AV17 AU17 AR21 AR22 AL21 AM22 AN22 AP21 AK21 AK22 AN20 AR20 AK18 AL18 AK20 AM20 AR18 AP18
1
HASWELL_MCP_E
SB_DQ0 SB_DQ1 SB_DQ2 SB_DQ3 SB_DQ4 SB_DQ5 SB_DQ6 SB_DQ7 SB_DQ8 SB_DQ9 SB_DQ10 SB_DQ11 SB_DQ12 SB_DQ13 SB_DQ14 SB_DQ15 SB_DQ16 SB_DQ17 SB_DQ18 SB_DQ19 SB_DQ20 SB_DQ21 SB_DQ22 SB_DQ23 SB_DQ24 SB_DQ25 SB_DQ26 SB_DQ27 SB_DQ28 SB_DQ29 SB_DQ30 SB_DQ31 SB_DQ32 SB_DQ33 SB_DQ34 SB_DQ35 SB_DQ36 SB_DQ37 SB_DQ38 SB_DQ39 SB_DQ40 SB_DQ41 SB_DQ42 SB_DQ43 SB_DQ44 SB_DQ45 SB_DQ46 SB_DQ47 SB_DQ48 SB_DQ49 SB_DQ50 SB_DQ51 SB_DQ52 SB_DQ53 SB_DQ54 SB_DQ55 SB_DQ56 SB_DQ57 SB_DQ58 SB_DQ59 SB_DQ60 SB_DQ61 SB_DQ62 SB_DQ63
D
SB_CK#0 SB_CK0 SB_CK#1 SB_CK1 SB_CKE0 SB_CKE1 SB_CKE2 SB_CKE3 SB_CS#0 SB_CS#1 SB_ODT0 SB_RAS SB_WE SB_CAS SB_BA0 SB_BA1 SB_BA2
DDR CHANNEL B
SB_MA0 SB_MA1 SB_MA2 SB_MA3 SB_MA4 SB_MA5 SB_MA6 SB_MA7 SB_MA8 SB_MA9 SB_MA10 SB_MA11 SB_MA12 SB_MA13 SB_MA14 SB_MA15 SB_DQSN0 SB_DQSN1 SB_DQSN2 SB_DQSN3 SB_DQSN4 SB_DQSN5 SB_DQSN6 SB_DQSN7 SB_DQSP0 SB_DQSP1 SB_DQSP2 SB_DQSP3 SB_DQSP4 SB_DQSP5 SB_DQSP6 SB_DQSP7
AM38 AN38 AK38 AL38
M_CLK_DDR#2 M_CLK_DDR2 M_CLK_DDR#3 M_CLK_DDR3
AY49 AU50 AW49 AV50
DDR_CKE2_DIMMB DDR_CKE3_DIMMB
AM32 AK32
DDR_CS2_DIMMB# DDR_CS3_DIMMB#
M_CLK_DDR#2 M_CLK_DDR2 M_CLK_DDR#3 M_CLK_DDR3
<19> <19> <19> <19>
DDR_CKE2_DIMMB DDR_CKE3_DIMMB
<19> <19>
DDR_CS2_DIMMB# DDR_CS3_DIMMB#
<19> <19>
AL32 AM35 AK35 AM33
DDR_B_RAS# DDR_B_WE# DDR_B_CAS#
AL35 AM36 AU49
DDR_B_BS0 DDR_B_BS1 DDR_B_BS2
AP40 AR40 AP42 AR42 AR45 AP45 AW46 AY46 AY47 AU46 AK36 AV47 AU47 AK33 AR46 AP46
DDR_B_MA0 DDR_B_MA1 DDR_B_MA2 DDR_B_MA3 DDR_B_MA4 DDR_B_MA5 DDR_B_MA6 DDR_B_MA7 DDR_B_MA8 DDR_B_MA9 DDR_B_MA10 DDR_B_MA11 DDR_B_MA12 DDR_B_MA13 DDR_B_MA14 DDR_B_MA15
AW30 AV26 AN28 AN25 AW22 AV18 AN21 AN18
DDR_B_DQS#0 DDR_B_DQS#1 DDR_B_DQS#2 DDR_B_DQS#3 DDR_B_DQS#4 DDR_B_DQS#5 DDR_B_DQS#6 DDR_B_DQS#7
AV30 AW26 AM28 AM25 AV22 AW18 AM21 AM18
DDR_B_DQS0 DDR_B_DQS1 DDR_B_DQS2 DDR_B_DQS3 DDR_B_DQS4 DDR_B_DQS5 DDR_B_DQS6 DDR_B_DQS7
DDR_B_RAS# DDR_B_WE# DDR_B_CAS#
<19> <19> <19>
DDR_B_BS0 <19> DDR_B_BS1 <19> DDR_B_BS2 <19> DDR_B_MA[0..15]
<19>
C
DDR_B_DQS#[0..7]
<19>
DDR_B_DQS[0..7]
<19>
B
4 OF 19
Rev1p2
Rev1p2
A
A
DELL CONFIDENTIAL/PROPRIETARY PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 5
4
3
2
Compal Electronics, Inc. Title
MCP(3/12) Size
Document Number
Date:
Friday, May 17, 2013
Rev 0.3
LA-9431P Sheet 1
8
of
59
5
4
3
2
1
+3.3V_ALW_PCH
+RTC_CELL
2
B
O 3
A
RC71
PCH_PCIE_WAKE# 10K_0402_5%
PCH_DPWROK @ RC79
1
2
PCH_RSMRST#_R 0_0402_5%
ME_SUS_PWR_ACK_R @ RC82
1
2
SUSACK#_R 0_0402_5%
RESET_OUT#
1
2
SYS_PWROK_R 0_0402_5%
@ RC84
PCH_PLTRST#_EC
PCH_PLTRST#_EC
<25,29,31,36,37>
1 DSWODVREN
0.1U_0402_25V6
UC3 TC7SH08FU_SSOP5~D
<37>
PM_APWROK
SIO_SLP_A#
1
PM_APWROK
2
B A
4
O 3
2
4
2
1
PCH_PLTRST#
PM_APWROK_R
UC7 TC7SH08FU_SSOP5~D
1
D
1
SYS_RESET#
@ UC2 74AHC1G09GW_TSSOP5~D
5
4
@ RC78 330K_0402_1%
1
D
+3.3V_ALW2 @ CC82 1 2
5
0.1U_0402_25V6
O A
3
+PCH_VCCDSW3_3
B
2
P
1 ME_RESET# 8.2K_0402_5%
2
G
2
P
1
XDP_DBRESET# @ RC76
@ CC9 1
0.1U_0402_25V6
G
5
@ RC74
SUS_STAT#/LPCPD# 10K_0402_5%
P
2
G
1
RC73 330K_0402_1%
1 2 @ RC72 0_0402_5% +3.3V_RUN @ CC8 1 2
2
+3.3V_RUN
2
@ RC144
0_0402_5%
DSWODVREN - ON DIE DSW VR ENABLE
+3.3V_RUN
HIGH = ENABLED (DEFAULT) 1
2
@ RC81
ME_RESET# 8.2K_0402_5%
HASWELL_MCP_E
UC1H
LOW = DISABLED
SYSTEM POWER MANAGEMENT
<12,36>
<20> <29> <30> <28>
+3.3V_ALW_PCH
<21> RP10
1 2 3 4
8 7 6 5
ME_SUS_PWR_ACK USB_OC3# SIO_EXT_WAKE# KB_DET#
@ RC86
SUSACK#
<36,9> SYS_PWROK <15,37> RESET_OUT# @ RC300 1 PLTRST_NFC# 1 @ RC89 PLTRST_USH# 1 @ RC90 PLTRST_MMI# 1 @ RC91 PLTRST_LAN# 1 @ RC92 PLTRST_VMM2320# <38> PCH_RSMRST#_Q <37> ME_SUS_PWR_ACK
2 2 2 2 2
@ RC87 @ RC88 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% @ RC93 @ RC94
1
2 0_0402_5%
1 1
2 0_0402_5% 2 0_0402_5%
SUSACK#_R SYS_RESET# SYS_PWROK_R PCH_PWROK PM_APWROK_R PCH_PLTRST#
2 0_0402_5% PCH_RSMRST#_R 2 0_0402_5% ME_SUS_PWR_ACK_R SIO_PWRBTN# <37,9> SIO_PWRBTN# AC_PRESENT <12,37> AC_PRESENT PCH_BATLOW# <12> PCH_BATLOW# SIO_SLP_S0# <37> SIO_SLP_S0# <36> SIO_SLP_WLAN#
USB_OC3# <11> SIO_EXT_WAKE# <12,36> KB_DET# <12,38>
1 1
AK2 AC3 AG2 AY7 AB5 AG7
AW6 AV4 AL7 AJ8 AN4 AF3 AM5
SUSACK SYS_RESET SYS_PWROK PCH_PWROK APWROK PLTRST
DSWVRMEN DPWROK WAKE
AW7 AV5 AJ5
DSWODVREN PCH_DPWROK PCH_PCIE_WAKE#
V5 AG4 AE6 AP5
CLKRUN# SUS_STAT#/LPCPD# SUSCLK SIO_SLP_S5#
AJ6 AT4 AL5 AP4 AJ7
SIO_SLP_S4# SIO_SLP_S3# SIO_SLP_A# SIO_SLP_SUS# SIO_SLP_LAN#
PCH_DPWROK <36> PCH_PCIE_WAKE# <37> JAPS1 CONN@
CLKRUN/GPIO32 SUS_STAT/GPIO61 SUSCLK/GPIO62 SLP_S5/GPIO63
RSMRST SUSWARN/SUSPWRDNACK/GPIO30 PWRBTN ACPRESENT/GPIO31 BATLOW/GPIO72 SLP_S0 SLP_WLAN/GPIO29
SLP_S4 SLP_S3 SLP_A SLP_SUS SLP_LAN
CLKRUN# T10
+3.3V_ALW_PCH
<10,29,36,37>
SIO_SLP_S3#
+PCH_VCCDSW3_3
PAD~D@ SIO_SLP_S5# <37> T11 PAD~D@ T12 PAD~D @ SIO_SLP_S4# <36,39,43> SIO_SLP_S3# <36,39,43> SIO_SLP_A# <36,39,44> SIO_SLP_SUS# <36> SIO_SLP_LAN# <28,36>
SIO_SLP_S5# SIO_SLP_S4# SIO_SLP_A#
+PCH_VCCDSW3_3 <6>
PCH_RTCRST#
PCH_RTCRST#
<37,40>
POWER_SW#_MB
POWER_SW#_MB
10K_8P4R_5%
SYS_RESET# SIO_SLP_S0# Rev1p2
8 OF 19
1
2
RC136
PCH_RSMRST#_R 10K_0402_5% +3.3V_RUN
C
XDP@
2
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 GND GND ACES_50506-01841-P01 C
CC41 1
UC6
XDP@
0.1U_0402_25V6
14 <6>
1 PCH_JTAG_TDO XDP@ RC95
PCH_JTAG_TDO
2 TDO_XDP 0_0402_5%
2
1 RC103 XDP@
2 TDI_XDP_R 0_0402_5%
<6>
PCH_JTAG_TMS
2 TMS_XDP 0_0402_5%
9 10
RUNPWROK TRST#_XDP
<36,37>
H_PROCHOT#
12 13
RUNPWROK
RUNPWROK
5 4
RUNPWROK
1 RC101 XDP@
2A
@ CC149 22P_0402_50V8J
2
CPU_XDP_TDO
6
CPU_XDP_TDI
2B
8
CPU_XDP_TMS
1
2OE 3A
3B
2
2
@
+1.05V_RUN
4B
4OE
GND
11
CPU_XDP_TRST#
Place near JXDP1 7 15
2
<6>
2
PCH_JTAG_JTAGX
RC5 need to close to JCPU1
<15>
1 CPU_XDP_TCLK RC97 @
0_0402_5%
2
+1.05V_VCCST
1
<13> <13>
CFG2 CFG3
CFG2 CFG3
<15>
2 PCH_JTAG_TDO 0_0402_5%
1 TDI_XDP_R RC104 @
2 PCH_JTAG_TCK 0_0402_5%
1 CPU_XDP_TCLK RC124 @
<18,19,31,7> <18,19,31,7>
<13> <13>
CFG4 CFG5
CFG4 CFG5
CFG6 <13> CFG6 2 1K_0402_5% RC105 1 CFG7 <13> CFG7 XDP@ 2 1K_0402_5% H_CPUPWRGD @ RC106 1 H_VCCST_PWRGD_XDP 2 0_0402_5% @ RC107 1 CFD_PWRBTN#_XDP SIO_PWRBTN#
H_VCCST_PWRGD <37,9>
1 TDO_XDP RC123 @
0_0402_5% B
@ RC113
CFG0 CFG1
CFG0 CFG1
XDP_OBS0_R XDP_OBS1_R
1 CPU_XDP_TRST# RC135 @
0_0402_5%
ESD request, place near CPU side
1
<13> <13>
74CBTLV3126BQ_DHVQFN14_2P5X3
PCH_JTAG_TRST#
CPU_PWR_DEBUG# <36,9> SYS_PWROK
DDR_XDP_WAN_SMBDAT DDR_XDP_WAN_SMBCLK <6> PCH_JTAG_TCK
@ RC108 @ RC110
1 1
2 0_0402_5% 2 0_0402_5%
CPU_PWR_DEBUG#_R SYS_PWROK_XDP
@ RC111 @ RC112 @ RC142
1 1 1
2 0_0402_5% 2 0_0402_5% 2 0_0402_5%
DDR_XDP_SMBDAT_R1 DDR_XDP_SMBCLK_R1 PCH_JTAG_TCK_R CPU_XDP_TCLK
GND0 GND1 OBSFN_A0 OBSFN_C0 OBSFN_A1 OBSFN_C1 GND2 GND3 OBSDATA_A0 OBSDATA_C0 OBSDATA_A1 OBSDATA_C1 GND4 GND5 OBSDATA_A2 OBSDATA_C2 OBSDATA_A3 OBSDATA_C3 GND6 GND7 OBSFN_B0 OBSFN_D0 OBSFN_B1 OBSFN_D1 GND8 GND9 OBSDATA_B0 OBSDATA_D0 OBSDATA_B1 OBSDATA_D1 GND10 GND11 OBSDATA_B2 OBSDATA_D2 OBSDATA_B3 OBSDATA_D3 GND12 GND13 PWRGOOD/HOOK0 ITPCLK/HOOK4 HOOK1 ITPCLK#/HOOK5 VCC_OBS_AB VCC_OBS_CD HOOK2 RESET#/HOOK6 HOOK3 DBR#/HOOK7 GND14 GND15 SDA TD0 SCL TRST# TCK1 TDI TCK0 TMS GND16 GND17 SAMTE_BSH-030-01-L-D-A CONN@
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60
CFG17 CFG16
CFG17 CFG16
CFG8 CFG9
CFG8 CFG9
CFG10 CFG11
CFG10 CFG11
<13> <13>
CFG19 CFG18
CFG19 CFG18
<13> <13>
CFG12 CFG13
CFG12 CFG13
<13> <13>
CFG14 CFG15
CFG14 CFG15
<13> <13>
XDP_RST#_R XDP_DBRESET#
<13> <13> <13> <13>
2
1
RC109 XDP@
TDO_XDP TRST#_XDP TDI_XDP TMS_XDP 1 CFG3_R RC99 XDP@
PCH_PLTRST#_EC 1K_0402_5% B
2 CFG3 1K_0402_5%
+1.05V_RUN
2
H_CATERR# 49.9_0402_1% 2 H_PROCHOT# 62_0402_5%
2 1 2
XDP@ RC102 1K_0402_5%
1 2
1
HASWELL_MCP_E
UC1B
<36> ESD request
CPU_DETECT# <37>
PECI_EC
CPU_DETECT# H_CATERR# PECI_EC
D61 K61 N62
2H_PROCHOT#_R 56_0402_5%
K63
2 PROC_DETECT CATERR PECI
MISC
PRDY PREQ PROC_TCK PROC_TMS PROC_TRST PROC_TDI PROC_TDO
JTAG
CAD Note: Avoid stub in the PWRGD path while placing resistors RC115
<37,46,47,48>
H_PROCHOT#
1 RC117
H_CPUPWRGD
C61
PROCHOT
PROCPWRGD
THERMAL
2
1RC125
SM_RCOMP0
121_0402_1%
2
1RC129
SM_RCOMP1
100_0402_1%
2
1RC133
SM_RCOMP2
SM_RCOMP0 SM_RCOMP1 SM_RCOMP2 <18>
DDR3_DRAMRST#_CPU <18> DDR_PG_CTRL
CAD Note: Trace width=12~15 mil, Spcing=20 mils Max trace length= 500 mil
AU60 AV60 AU61 AV15 AV61
SM_RCOMP0 SM_RCOMP1 SM_RCOMP2 SM_DRAMRST SM_PG_CNTL1
CPU_XDP_PRDY# CPU_XDP_PREQ# CPU_XDP_TCLK CPU_XDP_TMS CPU_XDP_TRST# CPU_XDP_TDI CPU_XDP_TDO
J60 H60 H61 H62 K59 H63 K60 J61
XDP_OBS0_R XDP_OBS1_R XDP_OBS2_R XDP_OBS3_R XDP_OBS4_R XDP_OBS5_R XDP_OBS6_R XDP_OBS7_R
Place near JXDP1.48
SYS_PWROK_XDP
1
@ CC48 0.1U_0402_25V6
2
PU/PD for JTAG signals +3.3V_RUN
Place near JXDP1.47
RC116 2
1 1K_0402_5%
CPU_XDP_TMS
@ RC118 2
1 51_0402_1%
CPU_XDP_TDI
@ RC119 2
1 51_0402_1%
CPU_XDP_PREQ#
XDP_DBRESET#
+1.05V_RUN
BPM#0 BPM#1 BPM#2 BPM#3 BPM#4 BPM#5 BPM#6 BPM#7
DDR3
PAD~D PAD~D PAD~D PAD~D PAD~D PAD~D
T122 T126 T129 T130 T131 T132
@ @ @ @ @ @
@ RC120 2
1 51_0402_1%
CPU_XDP_TDO
RC122 2
1 51_0402_1%
CPU_XDP_TCLK
RC127 2
1 51_0402_1%
@ RC131 2
1 51_0402_1%
CPU_XDP_TRST#
A
Rev1p2
2 OF 19
DELL CONFIDENTIAL/PROPRIETARY PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
XDP@ CC68 0.1U_0402_25V6
PWR
DDR3 COMPENSATION SIGNALS 200_0402_1%
J62 K62 E60 E61 E59 F63 F62
1 51_0402_1%
XDP_DBRESET#
@
1
CC90
100P_0402_50V8J
RC115 10K_0402_5%
reference CRB
TDO_XDP @ RC280 2
+3.3V_ALW_PCH
H_CPUPWRGD
A
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59
CPU_XDP_PREQ# CPU_XDP_PRDY#
4A
+1.05V_RUN
JXDP1
reference Shark Bay ULT Validation Customer Debug Port Implementation Requirement Rev 1.0 <6>
RC114
1
@
3OE
GND PAD
1
3
CC11 0.1U_0402_25V6
2 TDI_XDP 0_0402_5%
1B
1OE CC10 0.1U_0402_25V6
1 RC96 XDP@
PCH_JTAG_TDI
1A
+1.05V_RUN
1
RUNPWROK <6>
VCC
4
3
2
Compal Electronics, Inc. Title
MCP(4/12) Size
Document Number
Date:
Friday, May 17, 2013
Rev 0.3
LA-9431P Sheet 1
9
of
59
5
4
3
UC1A
D
+3.3V_RUN 1
2
CONTACTLESS_DET# 10K_0402_5%
1
2
TOUCHPAD_INTR# 10K_0402_5%
1
2
TOUCH_RST_N_GYRO_INT1 10K_0402_5%
RC137
RC140
<23> <23> <23> <23> <23> <23> <23> <23>
DDI1_LANE_N0 DDI1_LANE_P0 DDI1_LANE_N1 DDI1_LANE_P1 DDI1_LANE_N2 DDI1_LANE_P2 DDI1_LANE_N3 DDI1_LANE_P3
<27> <27> <27> <27> <27> <27> <27> <27>
DDI2_LANE_N0 DDI2_LANE_P0 DDI2_LANE_N1 DDI2_LANE_P1 DDI2_LANE_N2 DDI2_LANE_P2 DDI2_LANE_N3 DDI2_LANE_P3
DDI1_LANE_N0 DDI1_LANE_P0 DDI1_LANE_N1 DDI1_LANE_P1 DDI1_LANE_N2 DDI1_LANE_P2 DDI1_LANE_N3 DDI1_LANE_P3
C54 C55 B58 C58 B55 A55 A57 B57
DDI2_LANE_N0 DDI2_LANE_P0 DDI2_LANE_N1 DDI2_LANE_P1 DDI2_LANE_N2 DDI2_LANE_P2 DDI2_LANE_N3 DDI2_LANE_P3
C51 C50 C53 B54 C49 B50 A53 B53
DDI1_TXN0 DDI1_TXP0 DDI1_TXN1 DDI1_TXP1 DDI1_TXN2 DDI1_TXP2 DDI1_TXN3 DDI1_TXP3
2
1
HASWELL_MCP_E
EDP_TXN0 EDP_TXP0 EDP_TXN1 EDP_TXP1
DDI
EDP_TXN2 EDP_TXP2 EDP_TXN3 EDP_TXP3
EDP
DDI2_TXN0 DDI2_TXP0 DDI2_TXN1 DDI2_TXP1 DDI2_TXN2 DDI2_TXP2 DDI2_TXN3 DDI2_TXP3
EDP_AUXN EDP_AUXP EDP_RCOMP EDP_DISP_UTIL
C45 B46 A47 B47
EDP_CPU_LANE_N0 EDP_CPU_LANE_P0 EDP_CPU_LANE_N1 EDP_CPU_LANE_P1
EDP_CPU_LANE_N0 EDP_CPU_LANE_P0 EDP_CPU_LANE_N1 EDP_CPU_LANE_P1
COMPENSATION PU FOR eDP
<22> <22> <22> <22>
follow intel feedback +VCCIOA_OUT
C47 C46 A49 B49
EDP_COMP 24.9_0402_1%
A45 B45 D20 A43
EDP_CPU_AUX# EDP_CPU_AUX
EDP_CPU_AUX# EDP_CPU_AUX
2
1 RC134 D
CAD Note:Trace width=20 mils ,Spacing=25mil, Max length=100 mils.
<22> <22>
EDP_COMP
Rev1p2
1 OF 19
+3.3V_RUN RC202
UC1I
Intel WW18 Strapping option
HASWELL_MCP_E
Intel WW18 Strapping option 1
2
2
1
@ RC152 @ RC154
<22> <22> <22,36>
ENVDD_PCH 100K_0402_5% CODEC_IRQ 1K_0402_5% <29>
C
<12>
EDP_BIA_PWM PANEL_BKLEN ENVDD_PCH
EDP_BIA_PWM PANEL_BKLEN ENVDD_PCH
CONTACTLESS_DET# <7> DGPU_PWROK PIRQ#_TPM @T13 @ T13
DGPU_PWROK PIRQ#_TPM HDD_FALL_INT PAD~D
TOUCHPAD_INTR# TOUCH_RST_N_GYRO_INT1 +3.3V_RUN
CODEC_IRQ
B8 A9 C6
U6 P4 N4 N2 AD4 U7 L1 L3 R5 L4
EDP_BKLCTL EDP_BKLEN EDP_VDDEN
PIRQA/GPIO77 PIRQB/GPIO78 PIRQC/GPIO79 PIRQD/GPIO80 PME
DDPB_CTRLCLK DDPB_CTRLDATA DDPC_CTRLCLK DDPC_CTRLDATA
eDP SIDEBAND
DDPB_AUXN DDPC_AUXN DDPB_AUXP DDPC_AUXP
DISPLAY
GPIO
B9 C9 D9 D11
CPU_DPB_CTRLCLK CPU_DPB_CTRLDAT CPU_DPC_CTRLCLK CPU_DPC_CTRLDAT
C5 B6 B5 A6
CPU_DPB_AUX# CPU_DPC_AUX# CPU_DPB_AUX CPU_DPC_AUX
C8 A8 D6
DPB_HPD DPC_HPD
1 CLKRUN# <29,36,37,9> LANCLK_REQ# <28,7>
Rev1p2
9 OF 19
<6> 2
PCH_GPIO36
C
<27>
DPC_HPD
2
1
2
1
2
1
100K_0402_5%
<27>
CPU_DPB_AUX
RC151
10K_8P4R_5%
reference PDG 0.9
1
2
RC153
100K_0402_5%
DPB_HPD <23> DPC_HPD <27> EDP_CPU_HPD <22>
RC155
CC450 0.1U_0402_25V6
CLKRUN# LANCLK_REQ# HDD_FALL_INT PCH_GPIO36
CPU_DPC_AUX
CPU_DPC_AUX DDPB_HPD DDPC_HPD EDP_HPD
RC158 100K_0402_5%
8 7 6 5
CPU_DPC_AUX#
<23> <23> <27> <27>
1 RC139 1 RC141 1 RC143 1 RC145 1 RC147 1 RC149
100K_0402_5%
GPIO55 GPIO52 GPIO54 GPIO51 GPIO53
RP6 1 2 3 4
CPU_DPB_CTRLCLK CPU_DPB_CTRLDAT CPU_DPC_CTRLCLK CPU_DPC_CTRLDAT
2 CPU_DPB_CTRLCLK 2.2K_0402_5% 2 CPU_DPB_CTRLDAT 2.2K_0402_5% 2 CPU_DPC_CTRLCLK 2.2K_0402_5% 2 CPU_DPC_CTRLDAT 2.2K_0402_5% 2 CPU_DPB_AUX# 100K_0402_5% 2 CPU_DPC_AUX# 100K_0402_5%
@
ESD solution for black screen issue
B
B
A
A
DELL CONFIDENTIAL/PROPRIETARY PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 5
4
3
2
Compal Electronics, Inc. Title
MCP(5/12) Size
Document Number
Rev 0.3
LA-9431P Date:
Friday, May 17, 2013
Sheet 1
10
of
59
5
4
3
2
1
D
D
HASWELL_MCP_E
PCIE_PRX_MMITX_N5 PCIE_PRX_MMITX_P5
<30> <30>
PCIE_PTX_MMIRX_N5 PCIE_PTX_MMIRX_P5
PCIE_PTX_MMIRX_N5 PCIE_PTX_MMIRX_P5
C23 C22 F8 E8 B23 A23 H10 G10 B21 C21 E6 F6
C
B22 A21
10/100/1G LAN --->
<28> <28>
WLAN (Mini Card 2)--->
<31> <31> <31> <31>
PCIE_PTX_GLANRX_N3 PCIE_PTX_GLANRX_P3 PCIE_PRX_WLANTX_N4 PCIE_PRX_WLANTX_P4 PCIE_PTX_WLANRX_N4 PCIE_PTX_WLANRX_P4
Ext USB Port 2 <----
PCIE_PRX_GLANTX_N3 PCIE_PRX_GLANTX_P3
G11 F11
PCIE_PTX_GLANRX_N3 PCIE_PTX_GLANRX_P3
C29 B30
PCIE_PRX_WLANTX_N4 PCIE_PRX_WLANTX_P4
F13 G13
PCIE_PTX_WLANRX_N4 PCIE_PTX_WLANRX_P4
B29 A29
<32> <32>
USB3RN3 USB3RP3
<32> <32>
USB3TN3 USB3TP3
G17 F17 C30 C31 F15 G15 B31 A31
reference CRB
3.01K 1%
B
+PCH_AUSB3PLL
RC161 @RC163 @ RC163
1 1
@ T16 PAD~D @ T17 PAD~D 2 3.01K_0402_1% PCH_PCIE_RCOMP 2 0_0402_5% PCH_PCIE_IREF
E15 E13 A27 B27
USB2N0 USB2P0
PETN5_L0 PETP5_L0
USB2N1 USB2P1
PERN5_L1 PERP5_L1
USB2N2 USB2P2
PETN5_L1 PETP5_L1
USB2N3 USB2P3
PERN5_L2 PERP5_L2
USB2N4 USB2P4
PETN5_L2 PETP5_L2
USB2N5 USB2P5
PERN5_L3 PERP5_L3
USB2N6 USB2P6
PETN5_L3 PETP5_L3
USB2N7 USB2P7
PERN3 PERP3 PETN3 PETP3
USB3RN1 USB3RP1 USB
PCIe
USB3TN1 USB3TP1
PERN4 PERP4
USB3RN2 USB3RP2
PETN4 PETP4
USB3TN2 USB3TP2
AN8 AM8
USBP0USBP0+
AR7 AT7
USBP1USBP1+
AR8 AP8
USBP2USBP2+
AR10 AT10
USBP3USBP3+
AM15 AL15
USBP4USBP4+
AM13 AN13
USBP5USBP5+
AP11 AN11
USBP6USBP6+
AR13 AP13
USBP7USBP7+
G20 H20 C33 B34 E18 F18 B33 A33
USBP0USBP0+
<33> <33>
----->Ext Port 1 and DOCK2 (USB SW)
USBP1USBP1+
<35> <35>
----->Ext Port 2 IO/B
USBP2USBP2+
<31> <31>
----->WLAN/BT
USBP3USBP3+
<22> <22>
USBP4USBP4+
<29> <29>
USBP5USBP5+
<32> <32>
USBP6USBP6+
<31> <31>
----->WWAN
USBP7USBP7+
<22> <22>
----->Touch
USB3RN1 USB3RP1
<35> <35>
USB3TN1 USB3TP1
<35> <35>
USB3RN2 USB3RP2
<33> <33>
USB3TN2 USB3TP2
<33> <33>
----->Camera ----->USH ----->Ext Port 3 and DOCK1(USB SW)
USBRBIAS
----->Ext USB3 Port 1
----->Ext USB3 Port 3 IO/B
PERN1/USB3RN3 PERP1/USB3RP3 PETN1/USB3TN3 PETP1/USB3TP3
USBRBIAS USBRBIAS RSVD RSVD
PERN2/USB3RN4 PERP2/USB3RP4 PETN2/USB3TN4 PETP2/USB3TP4
OC0/GPIO40 OC1/GPIO41 OC2/GPIO42 OC3/GPIO43
RSVD RSVD PCIE_RCOMP PCIE_IREF
AJ10 AJ11 AN10 AM10
AL3 AT1 AH2 AV3
CAD NOTE: Route single-end 50-ohms and max 500-mils length. Avoid routing next to clock pins or under stitching capacitors. Recommended minimum spacing to other signal traces is 15 mils.
USBRBIAS PAD~D T14 @ PAD~D T15 @
USB_OC0# USB_OC1# USB_OC2# USB_OC3#
USB_OC0# USB_OC1# USB_OC2# USB_OC3#
C
RC159 22.6_0402_1%
<28> <28>
PCIE_PRX_GLANTX_N3 PCIE_PRX_GLANTX_P3
PERN5_L0 PERP5_L0
1
<30> <30>
MMI -->
F10 E10
2
UC1K PCIE_PRX_MMITX_N5 PCIE_PRX_MMITX_P5
<33> <35> <33> <9>
+3.3V_ALW_PCH
USB_OC1#
1 10K_0402_5%
B
2 RC166
Rev1p2
11 OF 19
+3.3V_ALW_PCH RP5
<12,30>
<7> PCH_SMB_ALERT# MEDIACARD_PWREN
USB_OC2# USB_OC0# PCH_SMB_ALERT# MEDIACARD_PWREN
8 7 6 5
1 2 3 4 10K_8P4R_5%
A
A
DELL CONFIDENTIAL/PROPRIETARY PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 5
4
3
2
Compal Electronics, Inc. Title
MCP(6/12) Size
Document Number
Rev 0.3
LA-9431P Date:
Friday, May 17, 2013
Sheet 1
11
of
59
5
4
3
2
1
+3.3V_RUN
RP2 H_THERMTRIP#
+3.3V_RUN D
2
1
2
1
MPHYP_PWR_EN 100K_0402_5% SIO_EXT_SCI# 100K_0402_5%
RC170 RC199
1
2
1
P1 PCH_AUDIO_EN AU2 SIO_EXT_WAKE# PM_LANPHY_ENABLEAM7 AD6 PCH_GPIO15 Y1 T3 PCH_GPIO17 AD5 AN5 EC_WAKE# AD7 AN3 NFC_IRQ
<36,9> SIO_EXT_WAKE# PM_LANPHY_ENABLE <28> LAN_RST# @ T139 PAD~D
PM_LANPHY_ENABLE 10K_0402_5%
<37> EC_WAKE# <20> PCH_NFC_RST <20> NFC_IRQ
EC_WAKE# 10K_0402_5%
RC206
<30> <11,30>
+3.3V_ALW_PCH suppoer DSW mode
MEDIACARD_RST# AG6 MEDIACARD_PWRENAP1 AL4 SLATE_MODE_R AT5 NFC_DET# AK4 PCH_GPIO44 AB6 U4 PCH_GPIO48 Y3 PCH_GPIO49 TOUCH_PANEL_INTR# P3 Y2 MPHYP_PWR_EN AT3 KB_DET# AH4 PCH_GPIO14 AM4 3.3V_CAM_EN# AG5 SIO_EXT_SMI# AG3 PCH_GPIO46
MEDIACARD_RST# MEDIACARD_PWREN <20>
NFC_DET#
<30>
2
1
2
1
MEDIACARD_IRQ# @ T140 PAD~D @ T141 PAD~D <22> TOUCH_PANEL_INTR# <39> MPHYP_PWR_EN <38,9> KB_DET# @ T138 PAD~D <22> 3.3V_CAM_EN# <37> SIO_EXT_SMI#
PCH_GPIO44 10K_0402_5% MEDIACARD_IRQ# 10K_0402_5%
RC200 RC205
C
<31> 2
1
2
1
2
1
2
1
3.3V_CAM_EN# 100K_0402_5% NFC_IRQ 100K_0402_5% MPHYP_PWR_EN 10K_0402_5% PCH_AUDIO_EN 10K_0402_5%
RC211
@
RC210 RC169 R C169 RC215
<25> <37>
PCH_GPIO9 PCH_GPIO10
@ T137 PAD~D mSATA_DEVSLP HDD_DEVSLP SIO_EXT_SCI# <26> SPKR
SIO_EXT_SCI# SPKR
AM3 AM2 P2 C4 L2 N5 V2
BMBUSY/GPIO76 GPIO8 LAN_PHY_PWR_CTRL/GPIO12 GPIO15 GPIO16 GPIO17 GPIO24 GPIO27 GPIO28 GPIO26 GPIO56 GPIO57 GPIO58 GPIO59 GPIO44 GPIO47 GPIO48 GPIO49 GPIO50 HSIOPC/GPIO71 GPIO13 GPIO14 GPIO25 GPIO45 GPIO46
CPU/ MISC
10K_8P4R_5% RP8
D60 V4 T4 AW15 AF20 AB21
THERMTRIP RCIN/GPIO82 SERIRQ PCH_OPI_RCOMP RSVD RSVD
1 0_0402_5% H_THERMTRIP#_R @ RC172 2 SIO_RCIN# SIO_RCIN# <37> IRQ_SERIRQ IRQ_SERIRQ <29,36,37> PCH_OPI_COMP @ T18 PAD~D @ T19 PAD~D
H_THERMTRIP#
GPIO
LPIO
GPIO9 GPIO10 DEVSLP0/GPIO33 SDIO_POWER_EN/GPIO70 DEVSLP1/GPIO38 DEVSLP2/GPIO39 SPKR/GPIO81
10 OF 19
PCH_GPIO83 PCH_GPIO84 PCH_GPIO85 BBS_BIT PCH_GPIO87 3.3V_TP_EN
PCH_GPIO83 100_0402_5%
8 7 6 5
MEDIACARD_RST# PCH_GPIO46 SUSACK# SIO_EXT_SMI#
PCH_BATLOW# AC_PRESENT
1
LCD_CBL_DET#
LCD_CBL_DET#
I2C0_SDA I2C0_SCL I2C1_SDA_TCH_PAD I2C1_SCL_TCH_PAD USH_DET# CAM_MIC_CBL_DET# PCH_GPIO66 TPM_ID0 TPM_ID1 SLP_ME_CSW_DEV#
2 2
USH_DET# <29> CAM_MIC_CBL_DET#
SLP_ME_CSW_DEV#
<36>
1 0_0402_5% 1 0_0402_5%
1
<21> <38>
<38>
1
1
2 2
2
1
2
RC180 @ 10K_0402_5%
IRQ_SERIRQ 10K_0402_5% USH_DET# 10K_0402_5% LCD_CBL_DET# 10K_0402_5% CPPE# 100K_0402_5% CAM_MIC_CBL_DET# 10K_0402_5% CPUSB# 100K_0402_5% I2C1_SDA_TCH_PAD 2.2K_0402_5% I2C1_SCL_TCH_PAD 2.2K_0402_5% TPM_ID0 10K_0402_5% TPM_ID1 20K_0402_5% SLP_ME_CSW_DEV# 10K_0402_5% 3.3V_HDD_EN 10K_0402_5% I2C0_SDA 2.2K_0402_5% I2C0_SCL 2.2K_0402_5% PCH_GPIO87 10K_0402_5%
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
RC178 RC282 RC189 RC185 RC193 RC191 RC201 RC203 RC284 RC285 RC289 B
RC295 RC204 2
1
1
2
RC208 RC216
2
1 2
I2C1_SCL_VMM
<21>
1
1
I2C1_SDA_VMM
TOUCH_PANEL_INTR#
SPKR
RC168
+3.3V_RUN
RC181 10K_0402_5%
@ RC222 1K_0402_5%
RC190 1K_0402_5%
@ RC287 1K_0402_5%
@ RC288 1K_0402_5% GPIO66
PCH_GPIO15
2
<22>
I2C1_SCL_TCH_PAD
BBS_BIT
1 R24
C
<36,9>
+3.3V_RUN
1
PCH_OPI_COMP 49.9_0402_1%
<22>
+3.3V_RUN
RC218 10K_0402_5%
PCH_GPIO66
+PCH_VCCDSW3_3
1 2 3 4
+1.05V_VCCST
I2C1_SDA_TCH_PAD
+3.3V_ALW_PCH
8 7 6 5
2 H_THERMTRIP# 1K_0402_5%
Rev1p2
@
+3.3V_RUN
@RC283 @ RC283 1K_0402_5%
+3.3V_RUN
PCH_GPIO9 SLATE_MODE_R PCH_BATLOW# AC_PRESENT
2 7@RC292
3.3V_TS_EN <22> 3.3V_HDD_EN <31> CPPE# <31> CPUSB# <31>
CPPE# CPUSB#
I2C1_SCL_TCH_PAD @ RC176 SUSACK#
+3.3V_ALW_PCH
<37>
reference PDG0.9
10K_8P4R_5%
2
D
10K_8P4R_5% R6 L6 N6 L8 R7 L5 N7 K2 J1 K3 J2 G1 K4 G2 J3 J4 F2 F3 G4 F1 E3 F4 D3 E4 C3 E2
GSPI0_CS/GPIO83 GSPI0_CLK/GPIO84 GSPI0_MISO/GPIO85 GSPI0_MOSI/GPIO86 GSPI1_CS/GPIO87 GSPI1_CLK/GPIO88 GSPI1_MISO/GPIO89 GSPI_MOSI/GPIO90 UART0_RXD/GPIO91 UART0_TXD/GPIO92 UART0_RTS/GPIO93 UART0_CTS/GPIO94 UART1_RXD/GPIO0 UART1_TXD/GPIO1 UART1_RST/GPIO2 UART1_CTS/GPIO3 I2C0_SDA/GPIO4 I2C0_SCL/GPIO5 I2C1_SDA/GPIO6 I2C1_SCL/GPIO7 SDIO_CLK/GPIO64 SDIO_CMD/GPIO65 SDIO_D0/GPIO66 SDIO_D1/GPIO67 SDIO_D2/GPIO68 SDIO_D3/GPIO69
I2C1_SDA_TCH_PAD @ RC174
1
1 2 3 4
RP9
RP7
2
8 7 6 5
3.3V_TS_EN PCH_GPIO84 PCH_GPIO85 3.3V_TP_EN
ESD request
<9> <37,9>
+3.3V_ALW_PCH
1 2 3 4
B
1 2 3 4
10K_8P4R_5%
<28> 2
2
HASWELL_MCP_E
UC1J
+PCH_VCCDSW3_3
RC197
1
CC91
2 EC_WAKE# 0_0402_5%
@RC301 @ RC301
8 7 6 5
PIRQ#_TPM PCH_GPIO83 SIO_RCIN#
PIRQ#_TPM
@
1
LAN_WAKE#
100P_0402_50V8J
<28,37>
<10>
GPIO15
GPIO86
GPIO81
TOP-BLOCK SWAP OVERRIDE
BOOT BIOS STRAP BIT BBS
TLS CONFIDENTIALITY
NO REBOOT STRAP
Low depop RC288 (DEFAULT) :Enable High pop RC288:Diable
HIGH LOW(DEFAULT)
HIGH LOW(DEFAULT)
HIGH LOW(DEFAULT)
LPC SPI
503118_503118_LPT_LP_PCH_EDS_Rev1_0
non use GPIO: GPIO0 GPIO3 GPIO10 GPIO14 GPIO17 GPIO21 GPIO22 GPIO24 GPIO36 GPIO38 GPIO48 GPIO49 GPIO51 GPIO54 GPIO59 GPIO60 GPIO66 GPIO70 GPIO73 GPIO79 GPIO87 GPIO93 GPIO94
A
A
DELL CONFIDENTIAL/PROPRIETARY PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 5
4
3
2
Compal Electronics, Inc. Title
MCP(7/12) Size
Document Number
Rev 0.3
LA-9431P Date:
Friday, May 17, 2013
Sheet 1
12
of
59
5
4
3
2
1
CFG STRAPS for CPU D
D
2 UC1S
EAR-STALL/NOT STALL RESET SEQUENCE AFTER PCU PLL IS LOCKE
HASWELL_MCP_E
CFG0
CFG16 CFG18 CFG17 CFG19
CFG8 CFG9 CFG10
AA62 U63 AA61 U62 CFG_RCOMP
A5
@ T33 PAD~D @ T35 @ T37 @ T38 @ T39
V63
E1 D1 J20 H18 B12
PAD~D PAD~D PAD~D PAD~D TDI_IREF
CFG0 CFG1 CFG2 CFG3 CFG4 CFG5 CFG6 CFG7 CFG8 CFG9 CFG10 CFG11 CFG12 CFG13 CFG14 CFG15
RSVD_TP RSVD_TP RSVD_TP RSVD_TP RSVD RSVD_TP RSVD_TP RSVD_TP
RESERVED
RSVD RSVD RSVD PROC_OPI_RCOMP
CFG16 CFG18 CFG17 CFG19
RSVD RSVD
CFG_RCOMP
VSS VSS
RSVD RSVD RSVD
RSVD RSVD RSVD RSVD TD_IREF 19 OF 19
2 RC235 1 RC236
1 2
CFG_RCOMP 49.9_0402_1% TDI_IREF 8.2K_0402_1%
PAD~D T20 @ PAD~D T21 @
C63 C62 B43
PAD~D T22 @ PAD~D T23 @ PAD~D T24 @
A51 B51
PAD~D T25 @ PAD~D T26 @
L60
PAD~D T27 @
N60
PAD~D T28 @
W23 Y22 AY15
CFG1 1
<9> <9> <9> <9>
CFG3 CFG4
1:(Default) Normal Operation; No stall 0:Lane Reversed
2
CFG0 CFG1 CFG2 CFG3 CFG4 CFG5 CFG6 CFG7 CFG8 CFG9 CFG10 CFG11 CFG12 CFG13 CFG14 CFG15
AV63 AU63
@ RC233 1K_0402_1%
C
<9> <9> <9> <9> <9> <9> <9> <9> <9> <9> <9> <9> <9> <9> <9> <9>
AC60 AC62 AC63 AA63 AA60 Y62 Y61 Y60 V62 V61 V60 U60 T63 T62 T61 T60
CFG0 CFG1
@ RC232 1K_0402_1%
1
CFG0
C
PAD~D T29 @ PAD~D T30 @ PROC_OPI_RCOMP
AV62 D58
PAD~D T31 PAD~D T32
@ @
PCH/PCH LESS MODE SELECTION
P22 N21
CFG1
P20 R20
PAD~D T34 PAD~D T36
1:(Default) Normal Operation 0:Lane Reversed
@ @
Rev1p2
PROC_OPI_RCOMP 1 49.9_0402_1%
2 RC237
B
B
CFG4 1 2
1 2
2
1 2
@ RC241 1K_0402_1%
@ RC239 1K_0402_1%
@ RC240 1K_0402_1%
1
CFG8
RC238 1K_0402_1%
CFG9 CFG10
Display Port Presence Strap
A
SAFE MODE BOOT 1: POWER FEATURES ACTIVATED DURING RESET CFG10 0: POWER FEATURES (ESPECIALLY CLOCK GATINE ARE NOT ACTIVATED
NO SVID PROTOCOL CAPABLE VR CONNECTED 1: VRS support SVID protocol are present 0:No VR support SVID is present CFG9 The chip will not generate(OR Respond to) SVID activity
ALLOW THE USE OF NOA ON LOCKED UNITS 1: Enable(Default): Noa will be disable in locked units and enable in un-locked units CFG8 0: Enable Noa will be available pegardless of the locking of the unit
CFG4
1 : Disabled; No Physical Display Port attached to Embedded Display Port 0 : Enabled; An external Display Port device is connected to the Embedded Display Port
A
DELL CONFIDENTIAL/PROPRIETARY PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 5
4
3
2
Compal Electronics, Inc. Title
MCP(8/12) Size
Document Number
Rev 0.3
LA-9431P Date:
Friday, May 17, 2013
Sheet 1
13
of
59
5
4
3
D
2
1
0_0402_5%
1
D
1 @ RC254
HASWELL_MCP_E
UC1Q AY2 DC_TEST_AY2_AW2 AY3 DC_TEST_AY3_AW3 AY60 DC_TEST_AY60 DC_TEST_AY61_AW61 AY61 DC_TEST_AY62_AW62 AY62 B2 TP_DC_TEST_B2 B3 DC_TEST_A3_B3 B61 DC_TEST_A61_B61 B62 B63 DC_TEST_B62_B63 C1 C2 DC_TEST_C1_C2
2
DAISY_CHAIN_NCTF_AY2 DAISY_CHAIN_NCTF_AY3 DAISY_CHAIN_NCTF_AY60 DAISY_CHAIN_NCTF_AY61 DAISY_CHAIN_NCTF_AY62 DAISY_CHAIN_NCTF_B2 DAISY_CHAIN_NCTF_B3 DAISY_CHAIN_NCTF_B61 DAISY_CHAIN_NCTF_B62 DAISY_CHAIN_NCTF_B63 DAISY_CHAIN_NCTF_C1 DAISY_CHAIN_NCTF_C2
DAISY_CHAIN_NCTF_A3 DAISY_CHAIN_NCTF_A4 DAISY_CHAIN_NCTF_A60 DAISY_CHAIN_NCTF_A61 DAISY_CHAIN_NCTF_A62 DAISY_CHAIN_NCTF_AV1 DAISY_CHAIN_NCTF_AW1 DAISY_CHAIN_NCTF_AW2 DAISY_CHAIN_NCTF_AW3 DAISY_CHAIN_NCTF_AW61 DAISY_CHAIN_NCTF_AW62 DAISY_CHAIN_NCTF_AW63 17 OF 19 Rev1p2
A3 A4
DC_TEST_A3_B3 DC_TEST_A4
A60 A61 A62 AV1 AW1 AW2 AW3 AW61 AW62 AW63
DC_TEST_A60 DC_TEST_A61_B61 DC_TEST_A62 DC_TEST_AV1 DC_TEST_AW1 DC_TEST_AY2_AW2 DC_TEST_AY3_AW3 DC_TEST_AY61_AW61 DC_TEST_AY62_AW62 DC_TEST_AW63
2
2 0_0402_5% 2 0_0402_5%
1 @ RC266 1 @ RC268
4
3 2 0_0402_5%
1 @ RC269
C
C
Package Daisy Chain: 1.B2-PKG-C1-PCB-C2-PKG-B3-PCB-A3-PKG-A4 2.A62-PKG-A61-PCB-B61-PKG-B62-PCB-B63-PKG-A60 3.AY60-PKG-AW61-PCB-AY61-PKG-AW62-PCB-AY62-PKG-AW63 4.AW1-PKG-AW3-PCB-AY3-PKG-AW2-PCB-AY2-PKG-AV1
UC1R
@T50 @T52 @T54 @T55
PAD~D PAD~D PAD~D PAD~D
AT2 RSVD_AT2 RSVD_AU44 AU44 RSVD_AV44 AV44 D15 RSVD_D15
@T58 @T60 @T62
PAD~D PAD~D PAD~D
RSVD_F22 RSVD_H22 RSVD_J21
F22 H22 J21
HASWELL_MCP_E
RSVD RSVD RSVD RSVD
RSVD RSVD RSVD RSVD
RSVD RSVD RSVD RSVD RSVD RSVD RSVD
RSVD RSVD RSVD
N23 R23 T23 U10
RSVD_N23 RSVD_R23 RSVD_T23 RSVD_U10
PAD~D PAD~D PAD~D PAD~D
T48 T49 T51 T53
AL1 AM11 AP7 AU10 AU15 AW14 AY14
RSVD_AL1 RSVD_AM11 RSVD_AP7 RSVD_AU10 RSVD_AU15 RSVD_AW14 RSVD_AY14
PAD~D PAD~D PAD~D PAD~D PAD~D PAD~D PAD~D
T56 T57 T59 T61 T63 T64 T65
@ @ @ @ @ @ @ @ @ @ @
B
B
Rev1p2
18 OF 19
A
A
DELL CONFIDENTIAL/PROPRIETARY PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 5
4
3
2
Compal Electronics, Inc. Title
MCP(9/12) Size
Document Number
Rev 0.3
LA-9431P Date:
Friday, May 17, 2013
Sheet 1
14
of
59
5
4
3
2
1
+1.05V_RUN
2 22U_0603_6.3V6M
+3.3V_RUN 1
1
@
2
+VCC_CORE
@
+1.05V_RUN 1 C458
2 22U_0603_6.3V6M
1 C459
2 22U_0603_6.3V6M
1 C460
2 22U_0603_6.3V6M
+VCC_CORE +3.3V_RUN
1
@
@
@
+1.05V_VCCST
2 2
1 0_0402_5%
2 3
NC
VCC
A Y
5
1 @ CC24
4
2 0.1U_0402_25V6
H_VCCST_PWRGD
+1.05V_RUN 1 C461
@ T66 +1.35V_MEM @ T67
2 22U_0603_6.3V6M
GND
1
2
@ T68 @ T69
+VCC_CORE PAD~D PAD~D VCCSENSE
74AUP1G07GW_TSSOP5
RC244 75_0402_1%
<46>
CAD Note: Place the PU resistors close to CPU RC224 close to CPU 300 - 1500mils
<9> <46> <46>
H_VCCST_PWRGD H_VR_EN H_VR_READY
1 1 1
H_VCCST_PWRGD @RC245 @ RC245 H_VR_EN @RC246 @ RC246 H_VR_READY @RC247 @ RC247
<46>
2
VIDALERT_N
H_CPU_SVIDALRT# RC248
<9>
@ T74 @ T75 @ T76 @ T77 @ T78 @ T79 @ T80 @ T81 @ T82 @ T83 @ T84 @ T85 @ T86
1 2
RC249 110_0402_1%
B
CAD Note: Place the PU resistors close to CPU RC249close to CPU 300 - 1500mils VIDSOUT
VIDSOUT
PAD~D PAD~D PAD~D PAD~D PAD~D PAD~D PAD~D PAD~D PAD~D PAD~D PAD~D PAD~D PAD~D
+1.05V_VCCST
+VCC_CORE
+VCC_CORE reference ULT CRB 1 2
RC250 100_0402_1%
VCC_SENSE
E63 AB23 A59 E20 AD23 AA23 AE59
H_CPU_SVIDALRT# L62 N63 VIDSCLK L63 VIDSOUT 2 0_0402_5% VCCST_PWRGD B59 2 0_0402_5% VR_EN F60 2 0_0402_5% VR_READY C59
CPU_PWR_DEBUG#
CPU_PWR_DEBUG#
+1.05V_VCCST
SVID DATA
<46>
1
43_0402_5%
F59 N58 AC58
VIDSCLK
2
1
@ T70 PAD~D +VCCIO_OUT +VCCIOA_OUT @ T71 PAD~D @ T72 PAD~D @ T73 PAD~D
ESD Request
+1.05V_VCCST
SVID ALERT
L59 J58
PAD~D PAD~D
AH26 AJ31 AJ33 AJ37 AN33 AP43 AR48 AY35 AY40 AY44 AY50
CC22
@ RC263
1K_0402_5% RC243 1
1 RESET_OUT#
2
1
2
1
2
@
1
2
D
HASWELL_MCP_E
UC1L
H_VCCST_PWRGD 100P_0402_50V8J
UC4
<37,9>
2
1
+1.35V_MEM
+1.35V_MEM
H_VR_READY RC256 +3.3V_ALW
C
2
@
+VCC_CORE
RC259 10K_0402_5% 2
2 1
2
1
+3.3V_RUN
+VCC_CORE
RC255 10K_0402_5%
H_VR_EN 2 10K_0402_5%
2
1
@
1
@
2
@
+1.05V_VCCST
2
2 22U_0603_6.3V6M
1
CC21 10U_0603_6.3V6M
1 C454
1
CC20 10U_0603_6.3V6M
@
1
CC13 2.2U_0402_6.3V6M
RC258 10K_0402_5%
D
+1.35V_MEM
CC12 2.2U_0402_6.3V6M
1 +VCC_CORE
RESISTOR STUFFING OPTIONS ARE PROVIDED FOR TESTING PURPOSES
CC19 10U_0603_6.3V6M
2 22U_0603_6.3V6M
CC18 10U_0603_6.3V6M
1 C453
CC17 10U_0603_6.3V6M
EMC@
CPU_PWR_DEBUG#
CC16 10U_0603_6.3V6M
0_0603_5%
Reference ULT DDRDG_080912 change to10uX6 2.2uX4 CC52 2.2U_0402_6.3V6M
2 @ RC242
VDDQ DECOUPLING
+1.35V_MEM
+5V_ALW
@
+VCCIO_OUT
+3.3V_ALW 1 C452
@
+1.05V_RUN
EMC@
CC81 2.2U_0402_6.3V6M
2
RC253 150_0402_1%
1
+1.35V_MEM
D63 H59 P62 P60 P61 N59 N61 T59 AD60 AD59 AA59 AE60 AC59 AG58 U59 V59 AC22 AE22 AE23 AB57 AD57 AG57 C24 C28 C32
RSVD RSVD
VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC
VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VCC RSVD RSVD VCC_SENSE RSVD VCCIO_OUT VCCIOA_OUT RSVD RSVD RSVD VIDALERT VIDSCLK VIDSOUT VCCST_PWRGD VR_EN VR_READY
HSW ULT POWER
VSS PWR_DEBUG VSS RSVD_TP RSVD_TP RSVD_TP RSVD_TP RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD VCCST VCCST VCCST VCC VCC VCC VCC VCC VCC
C
B
Rev1p2
12 OF 19 +1.05V_RUN
C36 C40 C44 C48 C52 C56 E23 E25 E27 E29 E31 E33 E35 E37 E39 E41 E43 E45 E47 E49 E51 E53 E55 E57 F24 F28 F32 F36 F40 F44 F48 F52 F56 G23 G25 G27 G29 G31 G33 G35 G37 G39 G41 G43 G45 G47 G49 G51 G53 G55 G57 H23 J23 K23 K57 L22 M23 M57 P57 U57 W57
+1.05V_VCCST PJP11 1
VCCSENSE
VCCSENSE
2
1
2
1
2
CC26 1U_0402_6.3V6K
CAD Note: RC250 SHOULD BE PLACED CLOSE TO CPU
CC50 22U_0603_6.3V6M
PAD-OPEN1x1m
@
<46>
A
A
DELL CONFIDENTIAL/PROPRIETARY PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 5
4
3
2
Compal Electronics, Inc. Title
MCP(10/12) Size
Document Number
Rev 0.3
LA-9431P Date:
Friday, May 17, 2013
Sheet 1
15
of
59
5
4
+1.05V_MODPHY 1
2
+1.05V_M
0_0805_5%
2
1
+ 2
@
1 + 2
@
1 + 2
CC72 330U_D3_2.5VY_R6M
1
CC71 330U_D3_2.5VY_R6M
2
+1.05V_RUN
CC73 330U_D3_2.5VY_R6M
2
1
CC29 1U_0402_6.3V6K
2
1
CC27 1U_0402_6.3V6K
1
CC74 1U_0402_6.3V6K
CC29 place near K9; CC27 place near L10 CC74 place near M9 VCCHSIO S0 Iccmax = 1.838A
@
@ RC262
D
3
+1.05V_MODPHY_PCH
@
D
+1.05V_MODPHY +PCH_AUSB3PLL
AC9 AA9 AH10 V8 W9
VCCSUS3_3 VCCSUS3_3 VCCDSW3_3 VCC3_3 VCC3_3
GPIO/LCC
+PCH_DCPSUS1
1
2
1
2
2
@
CC46 CC47 place near AE9
1
2
1
2
2
1
2
VCCSDIO VCCSDIO
CC59 place near K14 1
CC45 place near U8
U8 T9
1
LPT LP POWER SUS OSCILLATOR
DCPSUS4
AB8
+PCH_DCPSUS4
2 +1.05V_RUN
USB2
RSVD VCC1_05 VCC1_05
AC20 AG16 AG17
@
2
1 RC275
CC60 place near AG16
2
2
2
CC65 place near AG19
+PCH_RTC_VCCSUS3_3
+3.3V_ALW_PCH 2
1 @ RC261
0_0402_5%
+3.3V_ALW 2
1 @ RC264
0_0402_5% 1
2
+PCH_VCCDSW3_3
CC30 1U_0402_6.3V6K
1
Rev1p2
C
1
CC60 1U_0402_6.3V6K
+3.3V_ALW_PCH
SDIO/PLSS
2
1
+3.3V_RUN
+1.5V_THERMAL
CC45 1U_0402_6.3V6K
1
CC63 close to Pin J17 CC64 close to Pin R21
VCCCLK VCCCLK VCCACLKPLL VCCCLK VCCCLK VCCCLK RSVD RSVD RSVD VCCSUS3_3 VCCSUS3_3
1
2
+PCH_VCCDSW 5.11_0402_1%
CC59 0.1U_0402_10V7K
+PCH_VCC1P05
J18 K19 A20 J17 R21 T21 K18 M20 V21 AE20 AE21
13 OF 19
+3.3V_ALW_PCH
VCCTS1_5 VCC3_3 VCC3_3
J15 K14 K16
+PCH_VCCDSW
1
2
2
@
CC65 1U_0402_6.3V6K +PCH_VCCDSW_R
CORE
+1.05V_M
+1.05V_RUN
+3.3V_RUN +1.05V_RUN
CC64 1U_0402_6.3V6K
2
VRM/USB2/AZALIA
THERMAL SENSOR
CC63 1U_0402_6.3V6K
1
@ CC62 10U_0603_6.3V6M
2
@ CC61 1U_0402_6.3V6K
@ CC66 1U_0402_6.3V6K
2
1
AXALIA/HDA
J11 H11 H15 AE8 AF22 AG19 AG20 AE9 AF9 AG8 AD10 AD8
CC34 10U_0603_6.3V6M
1
+PCH_VCCDSW3_3
+PCH_VCCACLKPLL 1
VCC1_05 VCC1_05 VCC1_05 VCC1_05 VCC1_05 DCPSUSBYP DCPSUSBYP VCCASW VCCASW VCCASW DCPSUS1 DCPSUS1
CC47 22U_0805_6.3V6M
CC43 place near V8 CC43 22U_0603_6.3V6M
@
2
CC66 place near AH13 CC61 CC62 place near J13 DcpSus2 S0 Iccmax = 25mA DcpSus3 S0 Iccmax = 10mA
1
+3.3V_RUN
2
0_0603_5%
DCPSUS2
CC34 and CC33 place near J11; CC37 place near AE8
USB3
2
1
+PCH_DCPSUS 1
B
AH13
+3.3V_ALW_PCH
VCCHDA
1 +1.05V_M
CC33 1U_0402_6.3V6K
CC44 place near AH14
DCPSUS3
AG14 AG13
1
+3.3V_M
CC40 place near Y8
Y8
CC37 1U_0402_6.3V6K
1
CC28 place near AC9
RC276
J13 AH14
2 +1.05V_M
VCCSPI
OPI
CC35,CC38, CC39 place near AG10 CC35 1U_0402_6.3V6K
+PCH_DCPSUS
CC28 22U_0603_6.3V6M
2
SPI
AH11 +PCH_RTC_VCCSUS3_3 AG10 AE7 +DCPRRTC 1 2 CC36 0.1U_0402_10V7K
CC46 1U_0402_6.3V6K
CC44 0.1U_0402_10V7K
2
1
VCCSUS3_3 VCCRTC DCPRTC
RTC
CC39 0.1U_0402_10V7K
+3.3V_ALW_PCH
CC56 1U_0402_6.3V6K
1
CC56 place near AA21 VCCAPLL S0 Iccmax = 57mA
CC55 100U_1206_6.3V6M
1 2 2.2UH_LQM2MPN2R2NG0L_30%
RSVD VCCAPLL VCCAPLL
+RTC_CELL mPHY
VCCASW VCCASW
+V1.05S_APLLOPI
LC5
+V1.05S_APLLOPI
Y20 AA21 W21
VCCHSIO VCCHSIO VCCHSIO VCC1_05 VCC1_05 VCCUSB3PLL VCCSATA3PLL
CC38 0.1U_0402_10V7K
2
+PCH_AUSB3PLL +PCH_ASATA3PLL
K9 L10 M9 N8 P9 B18 B11
+1.05V_MODPHY_PCH
CC40 0.1U_0402_10V7K
2
1
CC31 1U_0402_6.3V6K
2
1
HASWELL_MCP_E
UC1M +1.05V_RUN
CC49 22U_0603_6.3V6M
CC49 place near B11 VCCSATA3PLL S0 Iccmax = 42mA
CC77 22U_0603_6.3V6M
1
+1.05V_RUN
2
+PCH_ASATA3PLL
LC2
1 2 2.2UH_LQM2MPN2R2NG0L_30%
C
1
CC42 22U_0603_6.3V6M
+1.05V_MODPHY
2
CC76 22U_0603_6.3V6M
1
CC42 place near B18 VCCUSB3PLL S0 Iccmax = 41mA
@
LC1 1 2 2.2UH_LQM2MPN2R2NG0L_30%
CC30 place near AH11 VCCSUS3_3 S0 Iccmax = 63mA
B
2
@ RC265
0_0402_5%
+PCH_DCPSUS1
+1.05V_M
+3.3V_ALW
1
2
+1.05V_RUN
@
0_0402_5%
CC32 place near AH10 VCCDSW3_3 S0 Iccmax = 114mA
2 1U_0402_6.3V6K @ CC54
@ RC267
2
CC32 1U_0402_6.3V6K
1
1 @ RC272
0_0402_5% 1
CC54 place near AD10 DCPSUS1 S0 Iccmax = 109mA
2
+PCH_VCC1P05 +PCH_DCPSUS4
A
2
1
1
2
2
@
@
@
+1.05V_M
LC4
2 1 2.2UH_LQM2MPN2R2NG0L_30% CC75 100U_1206_6.3V6M
2
1
1U_0402_6.3V6K CC53
CC51 place near J18 VCCCLK S0 Iccmax = 200mA
CC79 100U_1206_6.3V6M
1
CC51 1U_0402_6.3V6K
LC3 1 2 2.2UH_LQM2MPN2R2NG0L_30%
CC53 place near AB8 DCPSUS4 S0 Iccmax = 1mA
+PCH_VCCACLKPLL +1.05V_RUN
DELL CONFIDENTIAL/PROPRIETARY
LC6
2
5
CC78 100U_1206_6.3V6M
1
CC58 place near A20 VCCACLKPLL S0 Iccmax = 31mA
1
2
CC58 1U_0402_6.3V6K
1 2 2.2UH_LQM2MPN2R2NG0L_30%
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 4
3
2
Compal Electronics, Inc. Title
MCP(11/12) Size
Document Number
Date:
Friday, May 17, 2013
Rev 0.3
LA-9431P Sheet 1
16
of
59
A
5
4
3
2
1
D
D
14 OF 19
AJ35 AJ39 AJ41 AJ43 AJ45 AJ47 AJ50 AJ52 AJ54 AJ56 AJ58 AJ60 AJ63 AK23 AK3 AK52 AL10 AL13 AL17 AL20 AL22 AL23 AL26 AL29 AL31 AL33 AL36 AL39 AL40 AL45 AL46 AL51 AL52 AL54 AL57 AL60 AL61 AM1 AM17 AM23 AM31 AM52 AN17 AN23 AN31 AN32 AN35 AN36 AN39 AN40 AN42 AN43 AN45 AN46 AN48 AN49 AN51 AN52 AN60 AN63 AN7 AP10 AP17 AP20
AP22 AP23 AP26 AP29 AP3 AP31 AP38 AP39 AP48 AP52 AP54 AP57 AR11 AR15 AR17 AR23 AR31 AR33 AR39 AR43 AR49 AR5 AR52 AT13 AT35 AT37 AT40 AT42 AT43 AT46 AT49 AT61 AT62 AT63 AU1 AU16 AU18 AU20 AU22 AU24 AU26 AU28 AU30 AU33 AU51 AU53 AU55 AU57 AU59 AV14 AV16 AV20 AV24 AV28 AV33 AV34 AV36 AV39 AV41 AV43 AV46 AV49 AV51 AV55
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
HASWELL_MCP_E
UC1P
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS 15 OF 19 Rev1p2 VSS
AV59 AV8 AW16 AW24 AW33 AW35 AW37 AW4 AW40 AW42 AW44 AW47 AW50 AW51 AW59 AW60 AY11 AY16 AY18 AY22 AY24 AY26 AY30 AY33 AY4 AY51 AY53 AY57 AY59 AY6 B20 B24 B26 B28 B32 B36 B4 B40 B44 B48 B52 B56 B60 C11 C14 C18 C20 C25 C27 C38 C39 C57 D12 D14 D18 D2 D21 D23 D25 D26 D27 D29 D30 D31
D33 D34 D35 D37 D38 D39 D41 D42 D43 D45 D46 D47 D49 D5 D50 D51 D53 D54 D55 D57 D59 D62 D8 E11 E17 F20 F26 F30 F34 F38 F42 F46 F50 F54 F58 F61 G18 G22 G3 G5 G6 G8 H13
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
HASWELL_MCP_E
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS_SENSE 16 OF 19 Rev1p2 VSS
H17 H57 J10 J22 J59 J63 K1 K12 L13 L15 L17 L18 L20 L58 L61 L7 M22 N10 N3 P59 P63 R10 R22 R8 T1 T58 U20 U22 U61 U9 V10 V3 V7 W20 W22 Y10 Y59 Y63
C
V58 AH46 V23 E62 AH16
VSSSENSE
<46>
RC260 100_0402_1%
B
UC1O VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
1
C
HASWELL_MCP_E
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
2
UC1N A11 A14 A18 A24 A28 A32 A36 A40 A44 A48 A52 A56 AA1 AA58 AB10 AB20 AB22 AB7 AC61 AD21 AD3 AD63 AE10 AE5 AE58 AF11 AF12 AF14 AF15 AF17 AF18 AG1 AG11 AG21 AG23 AG60 AG61 AG62 AG63 AH17 AH19 AH20 AH22 AH24 AH28 AH30 AH32 AH34 AH36 AH38 AH40 AH42 AH44 AH49 AH51 AH53 AH55 AH57 AJ13 AJ14 AJ23 AJ25 AJ27 AJ29
CAD Note: RC260 SHOULD BE PLACED CLOSE TO CPU
B
Rev1p2
A
A
DELL CONFIDENTIAL/PROPRIETARY PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 5
4
3
2
Compal Electronics, Inc. Title
MCP(12/12) Size
Document Number
Rev 0.3
LA-9431P Date:
Friday, May 17, 2013
Sheet 1
17
of
59
Reverse Type
+DIMM1_VREF_DQ +1.35V_MEM
+1.35V_MEM
DDR_A_D[0..63]
<8>
DDR_A_DQS[0..7]
<8>
DDR_A_D44 DDR_A_D41 DDR_A_DQS#5 DDR_A_DQS5
DDR_A_MA[0..15]
DDR_A_D43 DDR_A_D47
Note: Check voltage tolerance of VREF_DQ at the DIMM socket
DDR_A_D51 DDR_A_D50
2
1
2
1
2
CD11 1U_0402_6.3V6K
2
1
CD10 1U_0402_6.3V6K
2
1
CD9 1U_0402_6.3V6K
2
1
CD8 1U_0402_6.3V6K
1
CD7 1U_0402_6.3V6K
2
CD6 1U_0402_6.3V6K
1
CD5 1U_0402_6.3V6K
2
CD4 1U_0402_6.3V6K
1 C
<8>
DDR_CKE0_DIMMA <8>
DDR_A_BS2
DDR_CKE0_DIMMA DDR_A_BS2 DDR_A_MA12 DDR_A_MA9 DDR_A_MA8 DDR_A_MA5 DDR_A_MA3 DDR_A_MA1
+1.35V_MEM <8> <8>
2
2
+ 2
<8>
DDR_A_BS0
<8> <8>
DDR_A_WE# DDR_A_CAS#
DDR_CS1_DIMMA#
DDR_A_MA10 DDR_A_BS0 DDR_A_WE# DDR_A_CAS# DDR_A_MA13 DDR_CS1_DIMMA#
DDR_A_D2 DDR_A_D6
Layout Note: Place near JDIMM1.203,204
DDR_A_D21 DDR_A_D20
DDR_A_D17 DDR_A_D16 +0.675V_DDR_VTT DDR_A_D36 DDR_A_D33
2
1
2
DDR_A_DQS#4 DDR_A_DQS4
CD31 10U_0603_6.3V6M
2
1
CD30 10U_0603_6.3V6M
2
1
CD29 0.1U_0402_25V6
2
1
CD28 0.1U_0402_25V6
1
CD27 0.1U_0402_25V6
2
CD26 0.1U_0402_25V6
1
DDR_A_D34 DDR_A_D38 DDR_A_D62 DDR_A_D58
DDR_A_D60 DDR_A_D61 @RD5 @ RD5
2 0_0402_5%
1
2
+3.3V_RUN 1
1
@
2
2
CD24 0.1U_0402_25V6
0_0402_5%
CD25 2.2U_0402_6.3V6M
@RD6 @ RD6
A
1
+0.675V_DDR_VTT
205
G1
G2
1 2
DDR3_DRAMRST#_CPU
<9>
+1.35V_MEM DDR_A_D42 DDR_A_D46 DDR_A_D52 DDR_A_D53
CAD NOTE PLACE THE CAP NEAR TO DIMM RESET PIN
+SM_VREF_DQ0_DIMM1
DDR_A_DQS#6 DDR_A_DQS6
DDR_CKE1_DIMMA
+SM_VREF_DQ0
RC173
DDR_A_D54 DDR_A_D55
DDR_CKE1_DIMMA
<8>
1
2 1
2_0402_1%
CC70 0.022U_0402_16V7K
2
RC195 24.9_0402_1%
DDR_A_MA15 DDR_A_MA14
C
DDR_A_MA11 DDR_A_MA7 DDR_A_MA6 DDR_A_MA4 DDR_A_MA2 DDR_A_MA0 M_CLK_DDR1 M_CLK_DDR#1 DDR_A_BS1 DDR_A_RAS# DDR_CS0_DIMMA# M_ODT0
M_CLK_DDR1 M_CLK_DDR#1
<8> <8>
DDR_A_BS1 DDR_A_RAS#
<8> <8>
DDR_CS0_DIMMA#
M_ODT1 1 @ RD12
+SM_VREF_CA_DIMM1 DDR_A_D5 DDR_A_D4
DDR_A_D3 DDR_A_D7
DDR3L SODIMM ODT GENERATION
+5V_ALW +1.35V_MEM
<8>
+SM_VREF_CA_DIMM
1
2
1
2
CD13 0.1U_0402_25V6
B
D
@
CD12
DDR_A_DQS#0 DDR_A_DQS0
74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204
2
2.2U_0402_6.3V6M
DDR_A_D0 DDR_A_D1
CKE1 VDD2 A15 A14 VDD4 A11 A7 VDD6 A6 A4 VDD8 A2 A0 VDD10 CK1 CK1# VDD12 BA1 RAS# VDD14 S0# ODT0 VDD16 ODT1 NC2 VDD18 VREF_CA VSS28 DQ36 DQ37 VSS30 DM4 VSS31 DQ38 DQ39 VSS33 DQ44 DQ45 VSS35 DQS#5 DQS5 VSS38 DQ46 DQ47 VSS40 DQ52 DQ53 VSS42 DM6 VSS43 DQ54 DQ55 VSS45 DQ60 DQ61 VSS47 DQS#7 DQS7 VSS50 DQ62 DQ63 VSS52 EVENT# SDA SCL VTT2
DDR_A_D45 DDR_A_D40
2 0_0402_5%
@RC279 @ RC279
2 0_0402_5%
QD1 BSS138-G_SOT23-3 1
3
R28
<8>
M_CLK_DDR0 M_CLK_DDR#0
CKE0 VDD1 NC1 BA2 VDD3 A12/BC# A9 VDD5 A8 A5 VDD7 A3 A1 VDD9 CK0 CK0# VDD11 A10/AP BA0 VDD13 WE# CAS# VDD15 A13 S1# VDD17 NCTEST VSS27 DQ32 DQ33 VSS29 DQS#4 DQS4 VSS32 DQ34 DQ35 VSS34 DQ40 DQ41 VSS36 DM5 VSS37 DQ42 DQ43 VSS39 DQ48 DQ49 VSS41 DQS#6 DQS6 VSS44 DQ50 DQ51 VSS46 DQ56 DQ57 VSS48 DM7 VSS49 DQ58 DQ59 VSS51 SA0 VDDSPD SA1 VTT1
1
1
DDR3_DRAMRST#
220K_0402_5%~D
2
1 1
CD22 330U_D3_2.5VY_R6M
2
1
CD21
2
1
10U_0603_6.3V6M CD20
2
1@
10U_0603_6.3V6M CD19
2
1
10U_0603_6.3V6M CD18
1
10U_0603_6.3V6M CD17
1@
10U_0603_6.3V6M CD16
10U_0603_6.3V6M CD15
2
10U_0603_6.3V6M CD14
10U_0603_6.3V6M
1
M_CLK_DDR0 M_CLK_DDR#0
73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 201 203
DDR_A_D27 DDR_A_D26
<19>
RC221 1.8K_0402_1%
DDR_A_D49 DDR_A_D48
+1.35V_MEM
DDR3_DRAMRST#
RC217 1.8K_0402_1%
Layout Note: Place near JDIMM1
RD3 470_0402_5%
DDR_A_D25 DDR_A_D24
1
<8>
DDR_A_D15 DDR_A_D11
2
DDR_A_D30 DDR_A_D31
DDR_A_DQS#[0..7]
+1.35V_MEM
S
<8>
DDR_A_DQS#3 DDR_A_DQS3
DDR_A_D9 DDR_A_D12 DDR_A_DQS#1 DDR_A_DQS1
CD3 0.1U_0402_25V6
All VREF traces should have 10 mil trace width
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72
1 2 G
DDR_A_D29 DDR_A_D28
VSS1 DQ4 DQ5 VSS3 DQS#0 DQS0 VSS6 DQ6 DQ7 VSS8 DQ12 DQ13 VSS10 DM1 RESET# VSS12 DQ14 DQ15 VSS14 DQ20 DQ21 VSS16 DM2 VSS17 DQ22 DQ23 VSS19 DQ28 DQ29 VSS21 DQS#3 DQS3 VSS24 DQ30 DQ31 VSS26
1
DDR_A_D14 DDR_A_D10
VREF_DQ VSS2 DQ0 DQ1 VSS4 DM0 VSS5 DQ2 DQ3 VSS7 DQ8 DQ9 VSS9 DQS#1 DQS1 VSS11 DQ10 DQ11 VSS13 DQ16 DQ17 VSS15 DQS#2 DQS2 VSS18 DQ18 DQ19 VSS20 DQ24 DQ25 VSS22 DM3 VSS23 DQ26 DQ27 VSS25
2
2
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71
1
1
CD2 0.1U_0402_25V6
2
D
CD1 2.2U_0402_6.3V6M
1
DDR_A_D13 DDR_A_D8
2-3A to 1 DIMMs/channel
CONN@
2
JDIMM1
D
2 0_0402_5%
Populate RD1, De-Populate RD7 for Intel DDR3 VREFDQ multiple methods M1 Populate RD7, De-Populate RD1 for Intel DDR3 VREFDQ multiple methods M3
1
1
1 @ RD1
2
0.675V_DDR_VTT_ON
1 1 R31 1
@R32 2M_0402_5%
DDR_A_D18 DDR_A_D19
2 M_ODT0 66.5_0402_1% 2 M_ODT1 66.5_0402_1% 2 66.5_0402_1% 2 66.5_0402_1%
R29 R30
2
+SM_VREF_DQ0_DIMM1
3
H=4mm
2
4
R33
M_ODT2
<19>
M_ODT3
<19> B
1
5
DDR_A_DQS#2 DDR_A_DQS2 +1.35V_MEM
DDR_A_D22 DDR_A_D23 DDR_A_D37 DDR_A_D32
@CD23 @ CD23 0.1U_0402_25V6 2
U5 1 <9>
2
DDR_PG_CTRL
3
DDR_A_D35 DDR_A_D39 DDR_A_D63 DDR_A_D59
NC
VCC
A Y
5
1
4
0.675V_DDR_VTT_ON
0.675V_DDR_VTT_ON
74AUP1G07GW_TSSOP5
DDR_A_DQS#7 DDR_A_DQS7 DDR_A_D56 DDR_A_D57
DDR_XDP_WAN_SMBDAT DDR_XDP_WAN_SMBCLK
<19,31,7,9> <19,31,7,9>
+0.675V_DDR_VTT
A
206
FOX_AS0A621-U4R6-7H
DELL CONFIDENTIAL/PROPRIETARY Compal Electronics, Inc. Title PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
DDRIII-SODIMM SLOT1 Size
4
3
2
Document Number
Rev 0.3
LA-9431P Date:
5
<43>
GND
Friday, May 17, 2013
Sheet 1
18
of
59
3
2
H=4mm +1.35V_MEM
+1.35V_MEM
<8>
DDR_B_DQS#[0..7] DDR_B_D[0..63]
<8>
DDR_B_DQS[0..7]
<8>
All VREF traces should have 10 mil trace width
DDR_B_D26 DDR_B_D27 DDR_B_D40 DDR_B_D41
DDR_B_MA[0..15]
DDR_B_DQS#5 DDR_B_DQS5 DDR_B_D46 DDR_B_D42
Layout Note: Place near JDIMM2
DDR_B_D56 DDR_B_D57
DDR_B_D59 DDR_B_D58
+1.35V_MEM
DDR_B_D13 DDR_B_D15 DDR_B_D25 DDR_B_D24
+SM_VREF_CA_DIMM DDR3_DRAMRST# DDR_B_D30 DDR_B_D31
1
DDR_B_D45 DDR_B_D44
DDR_B_D47 DDR_B_D43 DDR_B_D61 DDR_B_D60
2
DDR3_DRAMRST#
<18>
CAD NOTE PLACE THE CAP NEAR TO DIMM RESET PIN
DDR_B_MA3 DDR_B_MA1
+1.35V_MEM <8> <8>
2
1
2
1
2
1 + 2
<8> <8> <8> <8>
DDR_B_MA10 DDR_B_BS0
DDR_B_BS0
DDR_B_WE# DDR_B_CAS#
DDR_B_WE# DDR_B_CAS#
DDR_B_MA13 DDR_CS3_DIMMB#
DDR_CS3_DIMMB#
DDR_B_DQS#0 DDR_B_DQS0 DDR_B_D3 DDR_B_D7 B
Layout Note: Place near JDIMM2.203,204
DDR_B_D21 DDR_B_D20
DDR_B_D22 DDR_B_D23 DDR_B_D36 DDR_B_D33
+0.675V_DDR_VTT
DDR_B_DQS#4 DDR_B_DQS4
2
1
2
CD59 10U_0603_6.3V6M
2
1
CD58 10U_0603_6.3V6M
2
1
CD57 0.1U_0402_25V6
2
1
CD56 0.1U_0402_25V6
1
CD55 0.1U_0402_25V6
2
CD54 0.1U_0402_25V6
1
DDR_B_D35 DDR_B_D39 DDR_B_D52 DDR_B_D49
DDR_B_D48 DDR_B_D53 @ RD11 2 +3.3V_RUN
1 0_0402_5% 1
+3.3V_RUN 0_0402_5%
+0.675V_DDR_VTT
2
@
1
2
CD60 0.1U_0402_25V6
1
CD61 2.2U_0402_6.3V6M
A
2 @ RD10
205
G1
G2
<8> +SM_VREF_DQ1_DIMM2
DDR_B_MA11 DDR_B_MA7
RC126
DDR_B_MA6 DDR_B_MA4 DDR_B_MA2 DDR_B_MA0 M_CLK_DDR3 M_CLK_DDR#3 DDR_B_BS1 DDR_B_RAS# DDR_CS2_DIMMB# M_ODT2 M_ODT3
M_CLK_DDR3 M_CLK_DDR#3 DDR_B_BS1 DDR_B_RAS#
<8> <8>
DDR_CS2_DIMMB# M_ODT2 <18> M_ODT3
1
2
1
2_0402_1%
2
CC69 0.022U_0402_16V7K
RC128 24.9_0402_1%
+SM_VREF_CA_DIMM 1
DDR_B_D2 DDR_B_D6
C
2
<8>
<18>
+SM_VREF_CA_DIMM2 DDR_B_D5 DDR_B_D0
+SM_VREF_DQ1
1
<8> <8>
2 0_0402_5%
@ RD13
1
2
CD44 0.1U_0402_25V6
DDR_B_D4 DDR_B_D1
DDR_CKE3_DIMMB
DDR_B_MA15 DDR_B_MA14
CD43 2.2U_0402_6.3V6M
CD53 330U_D3_2.5VY_R6M
2
1
CD52 10U_0603_6.3V6M
1
CD51 10U_0603_6.3V6M
2
@
CD50 10U_0603_6.3V6M
2
1
CD49 10U_0603_6.3V6M
1
CD48 10U_0603_6.3V6M
2
@
CD47 10U_0603_6.3V6M
1
CD46 10U_0603_6.3V6M
2
CD45 10U_0603_6.3V6M
1
M_CLK_DDR2 M_CLK_DDR#2
M_CLK_DDR2 M_CLK_DDR#2
DDR_CKE3_DIMMB
RC132 1.8K_0402_1%
DDR_B_MA8 DDR_B_MA5
CKE1 VDD2 A15 A14 VDD4 A11 A7 VDD6 A6 A4 VDD8 A2 A0 VDD10 CK1 CK1# VDD12 BA1 RAS# VDD14 S0# ODT0 VDD16 ODT1 NC2 VDD18 VREF_CA VSS28 DQ36 DQ37 VSS30 DM4 VSS31 DQ38 DQ39 VSS33 DQ44 DQ45 VSS35 DQS#5 DQS5 VSS38 DQ46 DQ47 VSS40 DQ52 DQ53 VSS42 DM6 VSS43 DQ54 DQ55 VSS45 DQ60 DQ61 VSS47 DQS#7 DQS7 VSS50 DQ62 DQ63 VSS52 EVENT# SDA SCL VTT2
RC83 24.9_0402_1%
2
DDR_B_MA12 DDR_B_MA9
CKE0 VDD1 NC1 BA2 VDD3 A12/BC# A9 VDD5 A8 A5 VDD7 A3 A1 VDD9 CK0 CK0# VDD11 A10/AP BA0 VDD13 WE# CAS# VDD15 A13 S1# VDD17 NCTEST VSS27 DQ32 DQ33 VSS29 DQS#4 DQS4 VSS32 DQ34 DQ35 VSS34 DQ40 DQ41 VSS36 DM5 VSS37 DQ42 DQ43 VSS39 DQ48 DQ49 VSS41 DQS#6 DQS6 VSS44 DQ50 DQ51 VSS46 DQ56 DQ57 VSS48 DM7 VSS49 DQ58 DQ59 VSS51 SA0 VDDSPD SA1 VTT1
CC67 0.022U_0402_16V7K
+1.35V_MEM
74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204
2
DDR_B_BS2
DDR_B_BS2
2
DDR_B_D63 DDR_B_D62
1
DDR_CKE2_DIMMB <8>
1
DDR_B_DQS#7 DDR_B_DQS7
2
2
<8>
2
2_0402_1%
RC130 1.8K_0402_1%
2
1
CD42 1U_0402_6.3V6K
2
1
CD41 1U_0402_6.3V6K
2
1
CD40 1U_0402_6.3V6K
2
1
CD39 1U_0402_6.3V6K
2
1
CD38 1U_0402_6.3V6K
2
1
CD37 1U_0402_6.3V6K
2
1
CD36 1U_0402_6.3V6K
C
CD35 1U_0402_6.3V6K
1
73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 201 203
DDR_CKE2_DIMMB
D
+SM_VREF_CA
RC68 1
@
1
+1.35V_MEM
DDR_B_DQS#1 DDR_B_DQS1
RC69 1.8K_0402_1%
<8>
Note: Check voltage tolerance of VREF_DQ at the DIMM socket
Reverse Type
DDR_B_D12 DDR_B_D9
CD34 0.1U_0402_25V6
DDR_B_DQS#3 DDR_B_DQS3
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72
RC67 1.8K_0402_1%
DDR_B_D28 DDR_B_D29
VSS1 DQ4 DQ5 VSS3 DQS#0 DQS0 VSS6 DQ6 DQ7 VSS8 DQ12 DQ13 VSS10 DM1 RESET# VSS12 DQ14 DQ15 VSS14 DQ20 DQ21 VSS16 DM2 VSS17 DQ22 DQ23 VSS19 DQ28 DQ29 VSS21 DQS#3 DQS3 VSS24 DQ30 DQ31 VSS26
1
DDR_B_D10 DDR_B_D11
CONN@
2
2
DDR_B_D8 DDR_B_D14
VREF_DQ VSS2 DQ0 DQ1 VSS4 DM0 VSS5 DQ2 DQ3 VSS7 DQ8 DQ9 VSS9 DQS#1 DQS1 VSS11 DQ10 DQ11 VSS13 DQ16 DQ17 VSS15 DQS#2 DQS2 VSS18 DQ18 DQ19 VSS20 DQ24 DQ25 VSS22 DM3 VSS23 DQ26 DQ27 VSS25
1
1
CD33 0.1U_0402_25V6
D
2
CD32 2.2U_0402_6.3V6M
1
Populate RD4, De-Populate RD8 for Intel DDR3 VREFDQ multiple methods M1 Populate RD8, De-Populate RD4 for Intel DDR3 VREFDQ multiple methods M3
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71
1
JDIMM2 2 0_0402_5%
@RD7 @ RD7
2
+DIMM2_VREF_DQ 1
+SM_VREF_DQ1_DIMM2
1
2-3A to 1 DIMMs/channel
1
4
2
5
B
DDR_B_D16 DDR_B_D17 DDR_B_DQS#2 DDR_B_DQS2 DDR_B_D19 DDR_B_D18 DDR_B_D37 DDR_B_D32
DDR_B_D34 DDR_B_D38 DDR_B_D51 DDR_B_D55 DDR_B_DQS#6 DDR_B_DQS6 DDR_B_D54 DDR_B_D50
DDR_XDP_WAN_SMBDAT DDR_XDP_WAN_SMBCLK
<18,31,7,9> <18,31,7,9>
+0.675V_DDR_VTT
206 A
FOX_AS0A621-U4R6-7H
DELL CONFIDENTIAL/PROPRIETARY Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
Title
DDRIII-SODIMM SLOT2 Size
4
3
2
Rev 0.3
LA-9431P Date:
5
Document Number Friday, May 17, 2013
Sheet 1
19
of
59
5
4
3
2
1
D
D
+3.3V_ALW_PCH 0.1U_0402_25V6
@ C388 2
PLTRST_NFC# PCH_NFC_RST
1 2
TC7SH08FU_SSOP5~D
B
U29
O A
C
4
NFC_RST
G
<9> <12>
+3.3V_ALW_PCH
3
C
P
5
1
CONN@ JNFC1
@T87 @T88
1
2 NFC_DET# 100K_0402_5%
R38
<7> <7>
NFC_SMBCLK NFC_SMBDATA <12> @T89 <12>
1 @ R37
PAD~D PAD~D
TP_NFC_SWP_PWR_RSVD TP_NFC_RSVD4 NFC_RST NFC_SMBCLK NFC_SMBDATA TP_NFC_RSVD3
NFC_IRQ PAD~D NFC_DET#
2 TP_NFC_RSVD3 0_0402_5%
TP_NFC_RSVD1 NFC_DET#
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 GND GND
+3.3V_ALW_PCH
1
2
C1 0.1U_0402_16V4Z
+3.3V_ALW_PCH
@
C1 close to JNFC1 16 17
E-T_6718K-Y15N-01L
ST change to 6718K-Y15N-01L
B
B
A
A
DELL CONFIDENTIAL/PROPRIETARY PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 5
4
3
2
Compal Electronics, Inc. Title
NFC/Sensor Hub Conn Size
Document Number
Date:
Friday, May 17, 2013
Rev 0.3
LA-9431P Sheet 1
20
of
59
2
1
+1.05V_RUN_VMM
+3.3V_RUN_VMM
L4 1
2
2
B
1
2
C24 .01U_0402_16V7K
2
1
C23 .01U_0402_16V7K
2
1
C22 0.1U_0402_25V6
1
C21 1U_0603_10V6K
BLM18AG102SN1D_2P
+1.05V_VMM_VDDTX
E10 C7 C6 H11 E12 D12 J10 K8 K9 K10
+3.3V_RUN_VMM J2
L5 1
2
2
1
2
C3 C4 C11 C12 K3 K4 K11 K12 J4
C29 .01U_0402_16V7K
2
1
C28 .01U_0402_16V7K
2
1
C27 0.1U_0402_25V6
+3.3V_RUN_VDDIO
1
C26 1U_0603_10V6K
BLM18AG102SN1D_2P
1V Digital
VDDXT1V VDDLP VDDRXA0 VDDRXA1 VDDRXA2 VDDTX0A0 VDDTX0A1 VDDTX0A2 VDDTX1A0 VDDTX1A1 VDDTX1A2 VGA_AVDD VGA_AVDD VGA_AVDD VGA_AVDD
2
2
1 1
2
1
BLM18AG102SN1D_2P VMM_SPI_CS# VMM_SPI_DIN VMM_SPI_WP#
0.1U_0402_10V7K 0.1U_0402_10V7K 0.1U_0402_10V7K 0.1U_0402_10V7K 0.1U_0402_10V7K 0.1U_0402_10V7K 0.1U_0402_10V7K 0.1U_0402_10V7K 0.1U_0402_10V7K 0.1U_0402_10V7K
DP12412_P0 DP12412_N0 DP12412_P1 DP12412_N1 DP12412_P2 DP12412_N2 DP12412_P3 DP12412_N3 DP12412_AUX DP12412_AUX#
1 1 1 1 1 1 1 1 1 1
2 2 2 2 2 2 2 2 2 2
DP12412_P0_C DP12412_N0_C DP12412_P1_C DP12412_N1_C DP12412_P2_C DP12412_N2_C DP12412_P3_C DP12412_N3_C DP12412_AUX_C DP12412_AUX#_C
C155 C156 C157 C158 C159 C160 C161 C162 C19 C20 SRCDET
<27>
DP12412_HPD
DP12412_HPD
<9>
R63
8 7 6 5
CS# VCC DO(IO1) HOLD#(IO3) WP#(IO2) CLK GND DI(IO0)
VMM_SPI_HOLD VMM_SPI_CLK VMM_SPI_DO
1 1M_0402_5%
VMM_MESCL VMM_MESDA VMM_SPI_WP#
B5 B6 B1
VMM_SPI_CS# VMM_SPI_CLK VMM_SPI_DIN VMM_SPI_DO
A4 B3 B4 A3
VMM_GPIO6 VMM_GPIO7 VMM_GPIO8 VMM_GPIO9 LP_CTL
RxP0 RxN0 RxP1 RxN1 RxP2 RxN2 RxP3 RxN3 RxAUXP RXAUXN RxSRCDET RxHPD
Tx0P0 Tx0N0 Tx0P1 Tx0N1 Tx0P2 Tx0N2 Tx0P3 Tx0N3 CAD0 Tx0AUXP Tx0AUXN Tx0DDCSCL Tx0DDCSDA Tx0HPD
RSTN_IN
Tx1P0 Tx1N0 Tx1P1 Tx1N1 Tx1P2 Tx1N2 Tx1P3 Tx1N3 CAD1 Tx1AUXP Tx1AUXN Tx1DDCSCL Tx1DDCSDA Tx1HPD
MESCL MESDA ROMWP SPICS SPICLK SPIDI SPIDO
D14 D13 C14 C13 B14 B13 C1 M12 M13 L3 B2 A5
GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6/INT GPIO7/MSCL GPIO8/MSDA GPIO9 LP_CTL LP_EN
VGA_VSYNC VGA_HSYNC VGA_RP VGA_RN VGA_GP VGA_GN VGA_BP VGA_BN VGA_SCL VGA_SDA
1
+1.05V_RUN_VMM
G1 G2 F1 F2 E1 E2 D1 D2 H1 H2 C2 J1
A13
PLTRST_VMM2320#
2
2 0_0402_5%
DOCKED
DOCKED
+5V_ALW DOCKED +3.3V_RUN
3 4 5 6 7
ON1
CT1
VBIAS
GND
ON2
CT2
VIN2 VIN2
VOUT2 VOUT2 GPAD
14 13
+1.05V_RUN_VMM_U31
12
C433 1
1 C432
2 0.1U_0402_10V7K
1
2 470P_0402_50V7K
2
11 10
C394 1
9 8
2 470P_0402_50V7K
IN GND
OUT GND
4
27MHZ_12PF_X1E000021042600
SSDA SSCL
1
2
CLK_27M_IN
K1
CLK_27M_OUT
L1
TRSTN TCK TMS TMS2 TDI TDO
XIN XOUT
2
TPS22966DPUR_SON14_2X3~D 1
PJP13
R65
2
1 2.2K_0402_5%
1
B7 A7 B8 A8 B9 A9 B10 A10 A14 B11 A11 B12 VMM_DPC_CTRLCLK A12 VMM_DPC_CTRLDAT A6 E13 E14 F13 F14 G13 G14 H13 H14 M14 J13 J14 K13 L14 K14
DPC_LANE_P0 <34> DPC_LANE_N0 <34> DPC_LANE_P1 <34> DPC_LANE_N1 <34> DPC_LANE_P2 <34> DPC_LANE_N2 <34> DPC_LANE_P3 <34> DPC_LANE_N3 <34> DPC_CA_DET <24,34> SW_DPC_AUX <24> SW_DPC_AUX# <24> VMM_DPC_CTRLCLK <24> VMM_DPC_CTRLDAT <24> DPC_DOCK_HPD <34>
VMM_DPB_CTRLCLK VMM_DPB_CTRLDAT
L9 M9 M6 L6 M7 L7 M8 L8 L4 M4
VMM2310_TX2P0 VMM2310_TX2N0 VMM2310_TX2N3
M3 M5 L5
VMM2310_HDP VMM2310_AUXN VMM2310_AUXP
VMM2310_TX2N1 VMM2310_SCL VMM2310_SDA
PAD~D
A1 A2
T40 @
I2C1_SDA_VMM I2C1_SCL_VMM
M11 M10 L12 L13 L11 L10
<12> <12>
I2C debug port to VMM2320 +3.3V_RUN_VMM
1
+3.3V_RUN_VMM
R40 1
VMM_MESDA R42
1
SW_DPB_AUX# VMM_DPC_CTRLCLK 1 R49 VMM_DPC_CTRLDAT 1 R46 1 SW_DPC_AUX# R91
PAD-OPEN1x1m
XB: non Vpro use A2 part Vpro use A3 part
2 2.2K_0402_5% 2 2.2K_0402_5% 2 1M_0402_5%
R44 1
VMM_GPIO6 R52
1
VMM_GPIO7 R53
1
VMM_GPIO8 R54
SW_DPC_AUX SW_DPB_AUX LP_CTL
1 @ R207
2 100K_0402_5%
RED_DOCK GREEN_DOCK BLUE_DOCK
A
1 VMM2310_TX2N3 @ R73
2 RED_DOCK 0_0402_5%
1 VMM2310_TX2N2 @ R75
2 GREEN_DOCK 0_0402_5%
GREEN_DOCK
1 VMM2310_TX2N1 @ R76
2 BLUE_DOCK 0_0402_5%
BLUE_DOCK
RED_DOCK
B
VMM2310_TX2N2
+3.3V_RUN_VMM
C392 0.1U_0402_10V7K
DPB_LANE_P0 <34> DPB_LANE_N0 <34> DPB_LANE_P1 <34> DPB_LANE_N1 <34> DPB_LANE_P2 <34> DPB_LANE_N2 <34> DPB_LANE_P3 <34> DPB_LANE_N3 <34> DPB_CA_DET <24,34> SW_DPB_AUX <24> SW_DPB_AUX# <24> VMM_DPB_CTRLCLK <24> VMM_DPB_CTRLDAT <24> DPB_DOCK_HPD <34>
VMM_MESCL IDTVMM2320BKG8_BGA168
2
+3.3V_RUN_VMM_U31
15
2
VGA_DET VGA_IREF VGA_NC
RX_STS TX0_STS TX1_STS TX2_STS
2
2 VOUT1 VOUT1
3
C43 22P_0402_50V8J
<27,28,32,36>
VIN1 VIN1
C42 22P_0402_50V8J
1 2
R66 1M_0402_5%
Y1 1
K2 L2 M1 M2
1
1 CLK_27M_IN_R @ R107
PJP12 PAD-OPEN1x1m +1.05V_RUN U31
2
0.1U_0402_25V6
U6A <27> <27> <27> <27> <27> <27> <27> <27> <27> <27>
IDTVMM2320BKG8_BGA168 +3.3V_RUN_VDDA
1 2 3 4
EEPROM
C34 1
U7
W25X10CLSNIG _SO8
J5 J11 J12 K5 H10 J6 J7 J8 J9
VSS VSS VSS VSS VGA_AVSS VGA_AVSS VGA_AVSS VGA_AVSS VGA_AVSS
+3.3V_RUN_VMM R64 10K_0402_5%
2
G6 G7 G8 G9 G10 G11 H4 D4
VSS VSS VSS VSS VSS VSS VSS VSS
VDDSA VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDXT3V
2
F8 F9 F10 F11 G4 G5
VSS VSS VSS VSS VSS VSS
1 V Analog
J3 E5 H3 F3 D3
VDDTX0 VDDTX0 VDDTX1 VDDTX1
1
C5 D5 D6 D7 D8 D9 D10 D11 E4 E11 F4 F5 F6 F7
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
3.3V IO
2
C8 C9 F12 G12
VDDRX VDDRX
VDDRX_33 VDDTX0_33 VDDTX1_33 VGA_AVDD33 VGA_AVDD33
+3.3V_RUN_VDDA 1 1
C16 1U_0603_10V6K
2
1
C18 .01U_0402_16V7K
1
C17 0.1U_0402_25V6
2 +1.05V_RUN_VMM
C25 1U_0603_10V6K
1
VDD VDD VDD VDD VDD VDD VDD VDD
H5 C10 H12 K6 K7
C15 0.1U_0402_25V6
E3 G3
3.3V Analog
C14 .01U_0402_16V7K
2
E6 E7 E8 E9 H6 H7 H8 H9
C13 .01U_0402_16V7K
2
1
C12 .01U_0402_16V7K
2
1
C10 .01U_0402_16V7K
2
1
C11 0.1U_0402_25V6
2
1
C9 0.1U_0402_25V6
2
1
C8 1U_0603_10V6K
1
C132 10U_0603_6.3V6M
BLM18AG102SN1D_2P
+1.05V_VMM_VDD
+3.3V_RUN_VMM
L2
U6B 2
2
L1 1
1 R92 1 R47
2 1M_0402_5% 2 1M_0402_5%
1 R311 1 R312 1 R351
2 150_0402_1% 2 150_0402_1% 2 150_0402_1%
1 R69 VMM_DPB_CTRLCLK 1 R70 VMM_DPB_CTRLDAT 1 R72 SRCDET
<34>
2 2.2K_0402_5% 2 2.2K_0402_5% 2 1M_0402_5% 2 2.2K_0402_5% 2 2.2K_0402_5% 2 2.2K_0402_5% 2 1M_0402_5% 2 2.2K_0402_5% 2 2.2K_0402_5%
+3.3V_RUN_VMM
VMM2310_HDP R74
<34>
2
1 10K_0402_5%
A
<34>
1 VMM2310_SCL @ R77
2 CLK_DDC2_DOCK 0_0402_5%
1 VMM2310_SDA @ R81
2 DAT_DDC2_DOCK 0_0402_5%
VMM2310_TX2N0 1 @ R84
2 HSYNC_DOCK 0_0402_5%
HSYNC_DOCK
<34>
VMM2310_TX2P0 1 @ R88
2 VSYNC_DOCK 0_0402_5%
VSYNC_DOCK
<34>
CLK_DDC2_DOCK
<34>
DAT_DDC2_DOCK
VMM2310_AUXN 1 R85
2 3.74K_0402_1%
<34>
DELL CONFIDENTIAL/PROPRIETARY Compal Electronics, Inc. Title PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
2
1
IDT VMM2320 DP and VGA SW Size
Document Number
Date:
Friday, May 17, 2013
Rev 0.3
LA-9431P Sheet
21
of
59
5
4
3
2
1
+3.3V_TSP
2 0.1U_0603_50V7K
EMC@LE1 EMC@ LE1 1 DISP_ON
2
2
3
2
1
2
1
ESD depop location(EMC)
D
BIA_PWM BLM15BB221SN1D_2P~D
EDP_CPU_HPD LCD_TST
1
@
<12>
+BL_PWR_SRC 1 C52
<10>
<36>
+LCDVDD C54 2 C55 2 C59 2 C56 2 C60 2 C57 2
EDP_CPU_AUX#_C EDP_CPU_AUX_C EDP_CPU_LANE_P0_C EDP_CPU_LANE_N0_C EDP_CPU_LANE_P1_C EDP_CPU_LANE_N1_C
0.1U_0402_10V7K 0.1U_0402_10V7K 0.1U_0402_10V7K 0.1U_0402_10V7K 0.1U_0402_10V7K 0.1U_0402_10V7K
<12> Pin Pin Pin Pin
+3.3V_CAM
2
@ 2
Close to JEDP1.40
JLED1
+3.3V_RUN
1
@
2
Close to JEDP1.2
1 2 3 4 5 6 7 8
+5V_ALW <40> BATT_WHITE_LED# <40> BATT_YELLOW_LED# <40> PANEL_HDD_LED# <40> BREATH_WHITE_LED# <12> TOUCH_PANEL_INTR#
@
1 2 3 4 5 6 GND GND
For LCDVDD 2
1
VIN 2
D2 <36>
LCD_VCC_TEST_EN
ENVDD_PCH
2
BIA_PWM_EC
EDP_BIA_PWM
3
BIA_PWM_EC
<37>
2 R96 100K_0402_5%
1
APL3512ABI-TRG_SOT23-5
2
<10>
PANEL_BKEN_EC
<36>
BAT54CW_SOT323-3
2
2
BAT54CW_SOT323-3
4
EN
1
1
1 R95 10K_0402_5% B
PANEL_BKLEN
1
DISP_ON
5
R104 100K_0402_5%
BAT54CW_SOT323-3
<10>
3
EN_LCDPWR
3
D21
1
BIA_PWM
GND SS
1 <10,36>
EDP_BIA_PWM
VOUT
2
D10 3
+3.3V_ALW U9
1
10U_0603_6.3V6M
ACES_50450-0067N-P01 check
+LCDVDD
@ C431
@ C430 0.01U_0402_16V7K
Close to JLED1.1
CONN@
C64 0.1U_0402_25V6
2
1
C62 0.1U_0402_25V6
Close to JEDP1.33
1
+3.3V_TSP
C3 C 3 0.1U_0402_16V4Z
1
@
C
29 for cable detact GND 17 ~20 for BL_GND 3, 10 for eDP High speed GND 14,15 for LCD_GND
+5V_ALW
C68 0.1U_0402_25V6
@
EDP_CPU_AUX# <10> EDP_CPU_AUX <10> EDP_CPU_LANE_P0 <10> EDP_CPU_LANE_N0 <10> EDP_CPU_LANE_P1 <10> EDP_CPU_LANE_N1 <10>
2
LCD_CBL_DET# +3.3V_RUN
1 1 1 1 1 1
CONN@
C63 0.1U_0402_25V6
Close to 2 JEDP1.11,12
CAM_MIC_CBL_DET#
2 1K_0402_5%
@
<26>
@
IO_LOOP 1 R108
<11> <11>
D8 L30ESDL5V0C3-2_SOT23-3
USBP3_DUSBP3_D+
+LCDVDD
1
<26>
DMIC_CLK
CE2
JEDP1
DMIC0 +3.3V_CAM
100P_0402_50V8J CE1
C
USBP7USBP7+
100P_0402_50V8J
D
ACES_50398-04071-001 45 40 40 39 44 G5 39 38 43 G4 G3 38 42 37 37 36 41 G2 G1 36 35 35 34 34 33 33 32 32 31 31 30 30 29 29 28 28 27 27 26 26 25 25 24 24 23 23 22 22 21 21 20 20 19 19 18 18 17 17 16 16 15 15 14 14 13 13 12 12 11 11 10 10 9 9 8 8 7 7 6 6 5 5 4 4 3 3 2 2 1 1
B
Touch Screen Connector +3.3V_CAM
1
S
D
1 2
2 G
3
6 1
S
Q17A DMN66D0LDW-7_SOT363-6
2 G
4
D
3
S
D
2
2 G
1 2
5
A
2
4
3
2 3
USBP3_D+
<37>
EN_INVPWR
EN_INVPWR
FDC654P: P CHANNAL
DELL CONFIDENTIAL/PROPRIETARY
USBP3_D-
Panel backlight power control by EC
DLW21HN900SQ2L_4P 1 2 @ R100 0_0402_5%
5
Q17B DMN66D0LDW-7_SOT363-6
L8
1
1 @ R101
3
S
4
2
3.3V_TS_EN
G
USBP3-
<12>
S
<11>
1
1
D
2 1 47K_0402_5%
check Resistor
USBP3+
3
G
Q4 L2N7002WT1G_SC-70-3
2 0_0402_5%
change back to CCD_OFF at Goliad project <11>
+3.3V_TSP_Q 1
2
R99
EMC@
2
+3.3V_RUN Q1 LP2301ALT1G_SOT23-3
C65 0.1U_0603_50V7K
PWR_SRC_ON
1
A
1
R97 100K_0402_5%
PJP10 PAD-OPEN1x1m
D
2
+BL_PWR_SRC
C61 0.1U_0402_25V6
1 @ R106
3.3V_CAM_EN#
2
R94 10K_0402_5%
2 0_0402_5%
40mil
6 5 2 FDC654P-G_SSOT-6 1
G
1 @ R102
1
4
S
3
C66 1000P_0402_50V7K
<12>
40mil
C67 0.1U_0402_25V6
1
1
CCD_OFF
+PWR_SRC
+3.3V_RUN
Q3 LP2301ALT1G_SOT23-3
D
PJP9 PAD-OPEN1x1m
+3.3V_CAM_Q
<36>
+3.3V_RUN
Q2
2
1
+3.3V_TSP
For Webcam
Compal Electronics, Inc. PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
2 0_0402_5%
4
3
2
Title
eDP & CAM &TS Conn Size
Document Number
Date:
Friday, May 17, 2013
Rev 0.3
LA-9431P Sheet 1
22
of
59
5
4
3
2
1
EMC@ L9 EMC@L9 1 2 9NH_0402HS-9N0EJTS_5% L10 @
4
1
2
4
3
2
TMDSB_CON_CLK
3
TMDSB_CON_CLK#
DLW21SN900HQ2L-0805_4P
1
EMC@ L11 EMC@L11 1 2 9NH_0402HS-9N0EJTS_5%
D
2
1
2
L13 @
<10>
DDI1_LANE_N2
2 C209
1 TMDS_N0_C 0.1U_0402_10V7K
4
1
2
4
3
2
TMDSB_CON_P0
3
TMDSB_CON_N0
DLW21SN900HQ2L-0805_4P
1
EMC@L14 EMC@ L14 1 2 9NH_0402HS-9N0EJTS_5%
2
EMC@L15 EMC@ L15 1 2 9NH_0402HS-9N0EJTS_5%
1
2
2
U48
+VHDMI_VCC
1 GND
1
1
AP2330W-7_SC59-3
2
C
<10>
JHDMI1 CONN@
2
TMDSB_CON_P1
CPU_DPB_CTRLDAT_R CPU_DPB_CTRLCLK_R
1 TMDS_P1_C 0.1U_0402_10V7K
1
DDI1_LANE_N1
2 C270
1 TMDS_N1_C 0.1U_0402_10V7K
4
1
2
3
4
3
TMDSB_CON_N1
HDMI_CEC TMDSB_CON_CLK#
DLW21SN900HQ2L-0805_4P
1
EMC@L17 EMC@ L17 1 2 9NH_0402HS-9N0EJTS_5%
2
EMC@L18 EMC@ L18 1 2 9NH_0402HS-9N0EJTS_5%
1
2
@C278 @ C278 1.8P_0402_50V8
2 C269
2
HDMI_HPD_SINK
@C277 @ C277 1.8P_0402_50V8
DDI1_LANE_P1
1
EMI depop location(EMC)
L16 @ <10>
@
C88 10U_0603_6.3V6M
1 TMDS_P0_C 0.1U_0402_10V7K
@
C87 0.1U_0402_10V7K
2 C199
@ C276 1.8P_0402_50V8
DDI1_LANE_P2
@ C275 1.8P_0402_50V8
<10>
C333 0.1U_0402_16V4Z
EMI depop location(EMC)
EMC@L12 EMC@ L12 1 2 9NH_0402HS-9N0EJTS_5%
D
+5V_RUN
1
1 TMDS_CLK#_C 0.1U_0402_10V7K
IN
DDI1_LANE_N3
2 C191
OUT
1
@ C274 1.8P_0402_50V8
1 TMDS_CLK_C 0.1U_0402_10V7K
@ C273 1.8P_0402_50V8
2 C103
3
<10>
DDI1_LANE_P3
2
<10>
TMDSB_CON_CLK TMDSB_CON_N0 TMDSB_CON_P0 TMDSB_CON_N1 TMDSB_CON_P1 TMDSB_CON_N2
EMI depop location(EMC)
TMDSB_CON_P2
19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
HP_DET +5V DDC/CEC_GND SDA SCL Reserved CEC CKGND CK_shield GND CK+ GND D0GND D0_shield D0+ D1D1_shield D1+ D2D2_shield D2+
C
20 21 22 23
LCN_AUF05-1922S10-0019 L19 @ 2 C271
1 TMDS_P2_C 0.1U_0402_10V7K
1
<10>
DDI1_LANE_N0
2 C272
1 TMDS_N2_C 0.1U_0402_10V7K
4
1
2
4
3
2
TMDSB_CON_P2
3
TMDSB_CON_N2
DLW21SN900HQ2L-0805_4P
1
EMC@ L20 EMC@L20 1 2 9NH_0402HS-9N0EJTS_5%
2
1
2
@ C382 1.8P_0402_50V8
DDI1_LANE_P0
@ C279 1.8P_0402_50V8
<10>
EMI depop location(EMC) +3.3V_RUN
B
B
+5V_RUN HDMI_CEC
2
1 10K_0402_5%
1 1 1 1 1 1 1 1
2 2 2 2 2 2 2 2
2 +5V_HDMI_DDC 2.2K_0402_5%
CPU_DPB_CTRLDAT_R
1 R470
2 2.2K_0402_5%
G
4
3 D
CPU_DPB_CTRLDAT
S
<10>
Q120A DMN66D0LDW-7_SOT363-6
TMDS_P2_C TMDS_N2_C TMDS_P1_C TMDS_N1_C TMDS_P0_C TMDS_N0_C TMDS_CLK_C TMDS_CLK#_C
+3.3V_RUN
R465 R468 R467 R469 R462 R463 R464 R466
R460
1
470_0402_1% 470_0402_1% 470_0402_1% 470_0402_1% 470_0402_1% 470_0402_1% 470_0402_1% 470_0402_1%
2 10K_0402_5%
HDMI_OB
1
1 R471
D
S
CPU_DPB_CTRLCLK
CPU_DPB_CTRLCLK_R
5
<10>
6
2
1
G
2
Q120B DMN66D0LDW-7_SOT363-6
1
@
D
3
2
@
R472 0_0402_5%
D65 RB751VM-40TE-17_SOD323-2
+3.3V_RUN
1
@ R473
S
2 G
Q29 L2N7002WT1G_SC-70-3
G
2
A
DELL CONFIDENTIAL/PROPRIETARY
1
A
R475 1M_0402_5%
2
+3.3V_RUN
3
1
1
HDMI_HPD_SINK
D
DPB_HPD
S
<10>
R474
2 20K_0402_5%
Compal Electronics, Inc. Q121 L2N7002WT1G_SC-70-3
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
Title
HDMI Conn Size
Document Number
Rev 0.3
LA-9431P Date:
Friday, May 17, 2013
Sheet
23
of
59
5
4
3
2
1
+3.3V_RUN_VMM
AUX/DDC SW for DPB to E-DOCK
1
2 C93 0.1U_0402_25V6
U11 D
<21>
2
SW_DPB_AUX
C94 <34>
<21>
DPB_DOCK_AUX 2
SW_DPB_AUX# <34>
C95 DPB_DOCK_AUX#
1 2
1 SW_DPB_AUX_C 0.1U_0402_10V7K DPB_DOCK_AUX
BE0 A0
3
B0
4 5
1 SW_DPB_AUX#_C 0.1U_0402_10V7K DPB_DOCK_AUX#
7
A2
GND
B2
VMM_DPB_CTRLCLK
<21>
VMM_DPB_CTRLDAT
<21>
11 10
B3 BE2
B1
D
12
A3
BE1 A1
6
14 13
VCC BE3
9 8
PI3C3125LEX_TSSOP14~D
+3.3V_RUN_VMM
2
1
R60 100K_0402_5%
DPB_CA_DET
1 <21,34>
D
3
DPB_CA_DET#
S
2 G
DPB_CA_DET
Q10 BSS138W-7-F_SOT323-3
C
AUX/DDC SW for DPC to E-DOCK
C
+3.3V_RUN_VMM 1
2 C97 0.1U_0402_25V6
U13 <21>
SW_DPC_AUX <34>
<21>
SW_DPC_AUX# <34>
2 C98 DPC_DOCK_AUX 2 C99 DPC_DOCK_AUX#
1 SW_DPC_AUX_C 0.1U_0402_10V7K DPC_DOCK_AUX 1 SW_DPC_AUX#_C 0.1U_0402_10V7K DPC_DOCK_AUX#
1 2 3 4 5 6 7
B
BE0 A0
VCC BE3
B0
A3
BE1 A1
B3 BE2
B1
A2
GND
B2
14 13 12
VMM_DPC_CTRLCLK
<21>
11 10 9
VMM_DPC_CTRLDAT
<21>
8 B
PI3C3125LEX_TSSOP14~D
1
S
1 2
R56 100K_0402_5% D
3
+3.3V_RUN_VMM
DPC_CA_DET#
<21,34>
DPC_CA_DET
DPC_CA_DET
2 G
Q6 BSS138W-7-F_SOT323-3
A
A
DELL CONFIDENTIAL/PROPRIETARY 1 R120 1 R121
5
2 DPB_CA_DET 1M_0402_5% 2 DPC_CA_DET 1M_0402_5%
Compal Electronics, Inc. PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
4
3
2
Title
DP SW_DP125 Size
Document Number
Date:
Friday, May 17, 2013
Rev 0.3
LA-9431P Sheet 1
24
of
59
5
4
3
+3.3V_HDD
2
Mini mSATA H=4 1 @ R155
2 HDD_DEVSLP 10K_0402_5%
+3.3V_HDD
+3.3V_HDD JMINI3 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51
D
<29,31,36,37,9> <7>
PCH_PLTRST#_EC CLK_PCI_LPDEBUG
<6> <6>
SATA_PRX_DTX_P1_C SATA_PRX_DTX_N1_C
<6> <6>
SATA_PTX_DRX_N1_C SATA_PTX_DRX_P1_C
PCH_PLTRST#_EC 2 C108 2 C109
1 1 .01U_0402_16V7K .01U_0402_16V7K
SATA_PRX_DTX_P1 SATA_PRX_DTX_N1
C106 2 C105 2
1 .01U_0402_16V7K 1 .01U_0402_16V7K
SATA_PTX_DRX_N1 SATA_PTX_DRX_P1
+3.3V_HDD
1
2
C114 0.1U_0402_25V6
2
C113 0.1U_0402_25V6
1
1
@
<6>
HDD_DET#
HDD_DET#
53
CONN@
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52
GND1
GND2
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52
LPC_LFRAME# LPC_LAD3 LPC_LAD2 LPC_LAD1 LPC_LAD0
LPC_LFRAME# LPC_LAD3 LPC_LAD2 LPC_LAD1 LPC_LAD0
HDD_DEVSLP
D
<29,36,37,7> <29,36,37,7> <29,36,37,7> <29,36,37,7> <29,36,37,7>
HDD_DEVSLP
<12>
54
LCN_DAN08-52406-0500
C
C
Place near JMINI3
RING2 ,RING2_L AUD_HP_OUT_L ,AUD_HP_OUT_L1 AUD_HP_OUT_R ,AUD_HP_OUT_R1 SLEEVE ,EXT_MIC Trace width to 15mils.
1
+3.3V_RUN
Combo Jack
R480 10K_0402_5%
JHP1 CONN@
2 <26> <26>
B
RING2 AUD_HP_OUT_L
RING2 AUD_HP_OUT_L
@ R491 2 EMC@L51 2
7 3
1 0_0402_5% 1 BLM18AG221SN1D_2P
RING2_L AUD_HP_OUT_L1
B
1
Normal Open
5
<26> <26>
AUD_HP_OUT_R SLEEVE
AUD_HP_OUT_R SLEEVE
EMC@L52 2 2 @ R492
1 BLM18AG221SN1D_2P 1 0_0402_5%
AUD_HP_NB_SENSE
6
AUD_HP_OUT_R1 SLEEVE_L
2 4
2
3
2
3
EMC@ D32
1
1
AUD_HP_NB_SENSE
<26,36>
1
L03ESDL5V0CC3-2_SOT23-3
1
AUD_HP_NB_SENSE
R481 100K_0402_5% 2
@
EMI depop location(EMC)
EMC@ D31 L03ESDL5V0CC3-2_SOT23-3
2
EMC@ D30 L03ESDL5V0CC3-2_SOT23-3
2
@
1
C443 220P_0402_50V7K
2
@
1
C442 220P_0402_50V7K
@
1
C441 220P_0402_50V7K
2
C440 220P_0402_50V7K
1
2
3
SINGA_2SJ3080-003111F
A
A
DELL CONFIDENTIAL/PROPRIETARY Compal Electronics, Inc. Title PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 5
4
3
2
Min Card/mSATA/Combo Jack Size
Document Number
Date:
Friday, May 17, 2013
Rev 0.3
LA-9431P Sheet 1
25
of
59
1
+5V_RUN_AUDIO
9
<6>
PCH_AZ_CODEC_SDOUT
PCH_AZ_CODEC_SDOUT
<6>
PCH_AZ_CODEC_SYNC
5 10
Place R136 close to codec 1 R136
PCH_AZ_CODEC_SDIN0
<6>
6
2 33_0402_5%
8
PCH_AZ_SDIN0_R PCH_AZ_CODEC_RST#
PCH_AZ_CODEC_RST#
11
AVDD1 AVDD2/HVDD(3.3)
DVDD-IO
PVDD2 PVDD1
DVDD
Sense A Sense B LINE1-L/RING2 LINE1-R/SLEEVE LINE1-VREFO
BIT-CLK SDATA-OUT
HPOUT-L/MIC-CAP AVSS2/HPOUT-L HP-OUT-R
SYNC SDATA-IN
SPK-L+ SPK-L-
RESET#
Close to U17
EMI depop location(EMC)
<34> <34> <34>
DAI_BCLK# DAI_DO#
<34> <34>
Close to U17 pin6
16 17 18 24
19
1
BCLK: Audio serial data bus bit clock input/output LRCK: Audio serial data bus word clock input/output @ R149 33_0402_5%
<36>
AUD_NB_MUTE#
AUD_NB_MUTE# +3.3V_RUN_AUDIO
2 1
1
1
49
Place closely to Pin 13.
1
1 R152 39.2K_0402_1%
MIC1-L
CBN
1 2
1
2
1 R187 1 R197
RING2 RING2 SLEEVE
+VREFOUT
40 41
1 2 C385 10U_0603_6.3V6M 1 2 AUD_OUT_L 2 18_0402_5% AUD_OUT_R R162 1 R166 18_0402_5% INT_SPK_L+ INT_SPK_L-
44 43
INT_SPK_R+ INT_SPK_R-
31 33 32
12
AUD_PC_BEEP
2 4 46 48
1 DMIC_CLK_L EMC@ R170
37
1
35
2
2 C145 2 C146
SLEEVE
2 2.2K_0402_5%
2 2.2K_0402_5%
SLEEVE/RING2/AUD_HP_OUT_R/AUD_HP_OUT_L please keep 15mils trace AUD_HP_OUT_L AUD_HP_OUT_L <25> AUD_HP_OUT_R AUD_HP_OUT_R <25>
1 @ R194 1 @ R153 1 R147 1 R151
1 0.1U_0402_25V6 1 0.1U_0402_25V6 2 DMIC_CLK 33_0402_5%
1 @ R186 C134 2.2U_0603_6.3V6K
<25> <25>
2 10K_0402_5% 2 10K_0402_5% 2 1K_0402_5% 2 1K_0402_5%
+VREFOUT
1
SPKR
<12>
BEEP
<37>
2
DMIC_CLK <22> DMIC0 <22>
2 0_0402_5% EN_I2S_NB_CODEC#
DMIC_CLK
<36>
1
Place C134 close to Codec
MIC1-R
2 CBP/AVSS2
EAPD/PD LDO-CAP JDREF CPVEE VREF
DVSS PVSS
MIC1-VREFO AVSS1
GND
36 21 22 34 25
B
+ALC290_LDO_CAP
@
Place close to Codec place close to pin2
+ALC3226_CPVEE +ALC3226_VREF
30 26
2
1
1
2
1
2
EMI depop location(EMC) 1
2
place at Codec bottom side @ PJP4 1 2
C142 0.1U_0402_25V6 1 2
2
PAD-OPEN1x1m
3
C144 0.1U_0402_25V6
5
AUD_HP_NB_SENSE
2
D S
4
<25,36>
EMI Request(EMC) +5V_RUN_AUDIO
@
1
G
2
1
C408 10U_0603_6.3V6M
1
C137 0.1U_0402_25V6
Q20A DMN66D0LDW-7_SOT363-6
DMN66D0LDW-7_SOT363-6 Q20B
6
MONO-OUT/CBP
RING2 SLEEVE
Notes: Keep PVDD supply and speaker traces routed on the DGND plane. Keep away from AGND and other analog signals
2
C141 0.1U_0402_25V6 1 2
AUD_SENSE_A
D
G
S
1
I2S_DIN
28 29 23
ALC3226-CG_QFN48_7X7 place at AGND and DGND plane
2
I2S_LRCK
2
1
C140 10U_0603_6.3V6M
2
EMI depop location(EMC)
GPIO0/DMIC-CLK GPIO1/DMIC-DATA DMIC1/GPIO2 GPIO3
I2S_DOUT
AUD_SENSE_A AUD_SENSE_B
R39 20K_0402_1%
R150
42
I2S_SCLK
1
+VREFOUT
13 14
C138 2.2U_0603_6.3V6K
2 10K_0402_5%
7
PCBEEP
+VDDA_PVDD
C169 2.2U_0603_6.3V6K
2
1
@ C136 10P_0402_50V8J
47
SPK-R+ SPK-RI2S_MCLK
1
2
45 39
C167 0.1U_0402_25V6
@C135 @C135 0.1U_0402_10V7K
20
C410 1U_0603_10V6K
2
@ R148 47_0402_5%
2
DAI_DI
15
PCH_AZ_CODEC_BITCLK
1
PCH_AZ_CODEC_SDOUT
DAI_LRCK#
2 I2S_MCLK 22_0402_5% 2 I2S_BCLK 22_0402_5% Place R142 close to codec 2 I2S_DO 33_0402_5% 2 I2S_LRCLK 0_0402_5% 2 I2S_DI# 0_0402_5%
2
C130 22P_0402_50V8J
Close to U17 pin5
1 R137 1 R139 1 R142 1 @ R143 1 @ R144
DAI_12MHZ#
27 38
C131 1U_0603_10V4Z
<6>
B
PCH_AZ_CODEC_BITCLK
PCH_AZ_CODEC_BITCLK
DREG_OUT
@
3
<6>
2
U17
1
1
2
2
2
C122 10U_0603_6.3V6M
2
1
C123 0.1U_0402_25V6
2
2
1
@ R130 0_0805_5%
place close to pin45
C128 10U_0603_6.3V6M
1
1000P_0402_50V7K
2
C127
1
1000P_0402_50V7K
2
1000P_0402_50V7K
1
GND GND ACES_50209-0040N-001
@
C126
1000P_0402_50V7K
2
C125
C124
1
@
1
@
place close to pin39 C129 0.1U_0402_25V6
@
1
2
C116 10U_0603_6.3V6M
2
5 6
@
1
2
@ R140 0_0603_5%
+VDDA_AVDD2 C150 0.1U_0402_25V6
1
+DVDD_CORE 1
1
C117 10U_0603_6.3V6M
1 2 3 4
C121 10U_0603_6.3V6M
1 2 3 4
INT_SPKR_L+ INT_SPKR_LINT_SPKR_R+ INT_SPKR_R-
C120 0.1U_0402_25V6
BLM18PG330SN1_2P BLM18PG330SN1_2P BLM18PG330SN1_2P BLM18PG330SN1_2P
C405 1U_0603_10V6K
2 2 2 2
1
C119 0.1U_0402_25V6
1 1 1 1
+3.3V_RUN_AUDIO
CONN@ JSPK1 C118 1U_0603_10V6K
EMC@ L22 EMC@ L23 EMC@ L24 EMC@ L25
INT_SPK_L+ INT_SPK_LINT_SPK_R+ INT_SPK_R-
DVDD_IO should match with HDA Bus level
C115 0.1U_0402_25V6
+3.3V_RUN_AUDIO
40 mils trace keep 10 mil spacing
+5V_RUN_AUDIO
1 2 PBY160808T-600Y-N_2P place close to pin38
+VDDA_AVDD1
2
Internal Speakers Header
+3.3V_RUN_AUDIO
L21
1
place close to pin27
2
2
SLEEVE
PJP24 PAD-OPEN1x1m
+RTC_CELL
Add for solve pop noise and detect issue
1 2 3
6
4
S
S
G
1
D
D
2
Q21B DMN66D0LDW-7_SOT363-6
G
DOCK_HP_DET
5
DOCK_MIC_DET
DMN66D0LDW-7_SOT363-6 Q123B 1 6
1
1
R159 100K_0402_5%
2
2
2
1
+3.3V_RUN_AUDIO
S
R157 20K_0402_1%
D
<36>
RUN_ON
2 0_0402_5%
3 4 5 6 7
2
1 @ R213
VIN1 VIN1 ON1 VBIAS
VOUT1 VOUT1 CT1 GND
ON2
CT2
VIN2 VIN2
VOUT2 VOUT2
2 PCH_AZ_CODEC_RST# 0_0402_5%
GPAD
2
1 2
+3.3V_ALW G
R156 39.2K_0402_1% R158 100K_0402_5%
5
<36,37,39>
1 @ R154
+5V_ALW
S
+3.3V_RUN_AUDIO
2
DMN66D0LDW-7_SOT363-6 Q123A 4 3
D
AUD_SENSE_B
G
Place closely to Pin 14
R202 100K_0402_5%
1
U18 A
14 13
2 0.1U_0402_10V7K A
C147 1
2 470P_0402_50V7K
10
C148 1
2 1000P_0402_50V7K
9 8
+3.3V_RUN_AUDIO_U18
11
2 1
15
TPS22966DPUR_SON14_2X3~D
1 @ R220
1 @ C188
+5V_RUN_AUDIO_U18
12
2
2 AUD_NB_MUTE# 0_0402_5%
1
+3.3V_RUN_AUDIO
PJP25 PAD-OPEN1x1m @ C139 0.1U_0402_10V7K
Realtek feedback Prevent the Noise from Combo Jack while system entry into S3 / S4 /S
DELL CONFIDENTIAL/PROPRIETARY
<36>
Compal Electronics, Inc.
Q21A DMN66D0LDW-7_SOT363-6 PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
2
1
Title
Azalia (HD) Codec-ALC3226 Size
Document Number
Date:
Friday, May 17, 2013
Rev 0.3
LA-9431P Sheet
26
of
59
5
4
3
2
1
D
D
XB use SA00006ZP00 (S IC AP2337SA-7 SOT-23 3P LOAD SWITCH) +3.3V_RUN
2 R167 1 R168
<10> <10>
CPU_DPC_AUX# CPU_DPC_AUX
<10>
DOCKED
DPC_HPD
2
C451 0.1U_0402_25V6
1
@
ESD solution for black screen issue
13 14 5 18 1 17 22 43
GPU_SEL D0D0+ D1D1+ D2D2+ D3D3+
D0-B D0+B D1-B D1+B D2-B D2+B D3-B D3+B AUX-B AUX+B HPD_B
AUXAUX+ AUX_HPD_SEL HPD GND GND GND HGND
OE
1 1 1 1 1 1 1 1
2 2 2 2 2 2 2 2
0.1U_0402_10V7K 0.1U_0402_10V7K 0.1U_0402_10V7K 0.1U_0402_10V7K 0.1U_0402_10V7K 0.1U_0402_10V7K 0.1U_0402_10V7K 0.1U_0402_10V7K
mDP_LANE_N0_C mDP_LANE_P0_C mDP_LANE_N1_C mDP_LANE_P1_C mDP_LANE_N2_C mDP_LANE_P2_C mDP_LANE_N3_C mDP_LANE_P3_C
Dock
0
mini DP
DP12412_N0 DP12412_P0 DP12412_N1 DP12412_P1 DP12412_N2 DP12412_P2 DP12412_N3 DP12412_P3 DP12412_AUX# DP12412_AUX DP12412_HPD
25
2 R161
1 4.7K_0402_5%
<21> <21> <21> <21> <21> <21> <21> <21> <21> <21> <21>
JmDP1 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
mDP_AUX#_C mDP_LANE_N2_C mDP_AUX_C mDP_LANE_P2_C
+3.3V_RUN
mDP_LANE_N3_C mDP_LANE_N1_C mDP_LANE_P3_C mDP_LANE_P1_C DPB_MB_P14 mDP_LANE_N0_C mDP_CA_DET mDP_LANE_P0_C mDP_HPD
+3.3V_RUN 1
1
2
B
AUX/DDC SW for DPC to Mini DP
C
+VDISPLAY_VCC
1
33 32 31 30 29 28 27 26 19 20 15
function
1
U50
AP2337SA-7 SOT-23
PI3VDP12412ZHEX_TQFN42_9X3P5~D
DOCKED
2
OUT
2 3 4 6 7 8 9 10 11
D0-A D0+A D1-A D1+A D2-A D2+A D3-A D3+A AUX-A AUX+A HPD_A
C163 C164 C165 C166 C168 C170 C172 C173
GND
DOCKED
DOCKED DDI2_LANE_N0 DDI2_LANE_P0 DDI2_LANE_N1 DDI2_LANE_P1 DDI2_LANE_N2 DDI2_LANE_P2 DDI2_LANE_N3 DDI2_LANE_P3
VDD VDD VDD
mDP_LANE_N0 mDP_LANE_P0 mDP_LANE_N1 mDP_LANE_P1 mDP_LANE_N2 mDP_LANE_P2 mDP_LANE_N3 mDP_LANE_P3 mDP_AUX# mDP_AUX mDP_HPD
2 C411 0.1U_0402_25V6
C174 0.1U_0402_10V7K 2 1 mDP_AUX SW_mDP_AUX_C mDP_AUX_C 2 mDP_AUX# C175
1 SW_mDP_AUX#_C 0.1U_0402_10V7K mDP_AUX#_C
C171 .01U_0402_16V7K
1 R165
<21,28,32,36> <10> <10> <10> <10> <10> <10> <10> <10>
2 mDP_HPD 100K_0402_5% 2 mDP_AUX_C 100K_0402_5% 1 mDP_CA_DET 1M_0402_5% 2 DPB_MB_P14 5.1M_0402_5%
2
42 41 40 39 38 37 36 35 24 23 16
3
1 R164
2
U19 12 21 34
1
2
C
2
@
1
C154 0.1U_0402_25V6
2 mDP_AUX#_C 100K_0402_5%
1
C153 0.1U_0402_25V6
2 1 R163
1
C152 0.1U_0402_25V6
1
C151 4.7U_0603_6.3V6K
+3.3V_RUN
IN
@
C383 0.1U_0402_16V4Z
+3.3V_RUN
CONN@
DP_PWR GND AUX_CH_N LANE2_N AUX_CH_P LANE2_P GND GND LANE3_N LANE1_N LANE3_P LANE1_P GND GND CONFIG2 LANE0_N CONFIG1 LANE0_P HOT-PLUG GND
GND4 GND3 GND2 GND1
24 23 22 21
B
ACON_MAR2C-20K1800
U49 1 2
BE0 A0
3
VCC BE3
B0
4 5
A3
BE1 A1
6 7
B3 BE2
B1
A2
GND
B2
14 13 12
CPU_DPC_CTRLCLK
<10>
11 10 9
CPU_DPC_CTRLDAT
<10>
8
PI3C3125LEX_TSSOP14~D
D
1 2
R67 100K_0402_5%
1
+3.3V_RUN
A
A
mDP_CA_DET#
2 G
5
DELL CONFIDENTIAL/PROPRIETARY Compal Electronics, Inc.
Q31 BSS138W-7-F_SOT323-3 3
mDP_CA_DET
Title
S PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 4
3
2
mDP/DP12412 Size
Document Number
Date:
Friday, May 17, 2013
Rev 0.3
LA-9431P Sheet 1
27
of
59
5
4
3
2
1
+3.3V_RUN
<11>
PCIE_PTX_GLANRX_P3
<11>
PCIE_PTX_GLANRX_N3 <7>
LAN_SMBCLK
2
LAN_WAKE#
28 31 2 3
MDI_PLUS3 MDI_MINUS3
SMB_CLK SMB_DATA LANWAKE_N LAN_DISABLE_N
LOM_ACTLED_YEL# LOM_SPD100LED_ORG# LOM_SPD10LED_GRN#
2 0_0402_5%
26 27 25
LED0 LED1 LED2
RES_BIAS
1
1
1 2
2
25MHZ_18PF_7V25000034
1
2
2
GND
LAN_TEST_EN
30 12
JTAG_TDI JTAG_TDO JTAG_TMS JTAG_TCK
VDD3P3_15 VDD3P3_19 VDD3P3_29
XTAL_OUT XTAL_IN
20 21
LAN_TX2+ LAN_TX2-
23 24
LAN_TX3+ LAN_TX3-
6
VCT_LAN_R1
1
+RSVD_VCC3P3_1
5
2
D
+0.9V_LAN @ R175 2
1 0_0402_5%
R178 2
VDD0P9_43 VDD0P9_11 VDD0P9_40 VDD0P9_22 VDD0P9_16 VDD0P9_8
Pin 6 is SVR_EN in Clarkville
1 4.7K_0402_5%
+3.3V_LAN 1
reference INTEL r217 circuit version1.7
4
2 @ R181
+3.3V_LAN_OUT
15 19 29
1 +0.9V_LAN
47 46 37
1 0_0603_5%
+3.3V_LAN
2
1
2
1
2
1
2
1
2
Note: +1.0V_LAN will work at 0.95V to 1.15V
43 11 40 22 16 8
+3.3V_LAN
TEST_EN RBIAS
2
Place C117, C180 and L26 close to U21
2
PJP20 PAD-OPEN1x1m
+3.3V_ALW CTRL0P9 VSS_EPAD
R185 3.01K_0402_1%
GND
1
R184 1K_0402_5%
2
IN
C190 33P_0402_50V8J
C189 33P_0402_50V8J
4
OUT
9 10
XTALO XTALI
2
3
32 34 33 35
TP_LAN_JTAG_TDI TP_LAN_JTAG_TDO TP_LAN_JTAG_TMS TP_LAN_JTAG_TCK
R206 1M_0402_5% Y3
C
VDD3P3_IN
VDD0P9_47 VDD0P9_46 VDD0P9_37
JTAG
PAD~D PAD~D
1
1 @ R183
RSVD_VCC3P3_1
LAN_DISABLE#_R
Pin 2 is WAKE_EN in Clarkville
@ T92 @ T93
XTALO_R
SVR_EN_N
VDD3P3_4
2
TP_LAN_JTAG_TMS 10K_0402_5% 2 TP_LAN_JTAG_TCK 10K_0402_5% 1 LAN_WAKE#_R 4.7K_0402_5%
PERp PERn
MDI_PLUS2 MDI_MINUS2
LAN_TX1+ LAN_TX1-
C182 1U_0603_10V6K
2
<36>
@ R182 10K_0402_5%
1
SMBus Device Address 0xC8
PETp PETn
17 18
C187 22U_0805_6.3V6M
LAN_SMBDATA
41 42
MDI_PLUS1 MDI_MINUS1
C186 0.1U_0402_10V7K
<7> <12,37>
38 39
MDI_PLUS0 MDI_MINUS0
PE_CLKP PE_CLKN
C185 0.1U_0402_10V7K
2 0_0402_5%
2 C179 2 C176 1 C178 1 C181 1 @ R174 1 @ R177 1 @ R179
CLK_REQ_N PE_RST_N
1
PCIE_PRX_GLANTX_N3
44 45
1
7
REGCTL_PNP10
C
49
U22 1 2
WGI218LM-SLK3A-B1_QFN48_6X6~D <36,9>
SIO_SLP_LAN#
2 @ R196
1 0_0402_5%
3 4
+5V_ALW <36>
MCARD_WWAN_PWREN
VOUT1 VOUT1
ON1
CT1
VBIAS
5
MCARD_WWAN_PWREN
VIN1 VIN1
6 7
GND
ON2
CT2
VIN2 VIN2
VOUT2 VOUT2 GPAD
1 R50
LAN ANALOG SWITCH
2
MCARD_WWAN_PWREN 100K_0402_5%
2
<11>
CLK_PCIE_LAN CLK_PCIE_LAN# 1 PCIE_PRX_GLANTX_P3_C 0.1U_0402_10V7K 1 PCIE_PRX_GLANTX_N3_C 0.1U_0402_10V7K 2 PCIE_PTX_GLANRX_P3_C 0.1U_0402_10V7K 2 PCIE_PTX_GLANRX_N3_C 0.1U_0402_10V7K 2 LAN_SMBCLK_R 0_0402_5% 2 LAN_SMBDATA_R 0_0402_5% 2 LAN_WAKE#_R 0_0402_5% LAN_DISABLE#_R
LAN_TX0+ LAN_TX0-
C184 0.1U_0402_10V7K
1 @ R180
+3.3V_LAN 1 @ R171 1 @ R172 2 @ R176
1 13 14
C183 0.1U_0402_10V7K
PM_LANPHY_ENABLE
@ R173 10K_0402_5%
1
+3.3V_LAN
CLK_PCIE_LAN CLK_PCIE_LAN# PCIE_PRX_GLANTX_P3
48 36
MDI
2
2 0_0402_5%
LANCLK_REQ#
<7> <7> <11>
2 LANCLK_REQ#_R 0_0402_5% PLT_LAN_RST#
PCIE
1 3
1 @ R145
<10,7>
@
1 @ R169
SMBUS
PLT_LAN_RST#
LED
4
D
<12>
L26
P
1
5 A
TC7SH08FU_SSOP5~D
2
U21
G
O
2
PLTRST_LAN#
1
REGCTL_PNP10 4.7UH_CBC2012T4R7M_20%
C180 10U_0603_6.3V6M
B
@
R25 100K_0402_5%
<9>
1
LAN_RST#
U20
XB use SA000066W3L(S IC WGI218LM SLK3A B1 QFN 48P PHY )
C177 0.1U_0402_10V7K
<12>
2 1 @ C406 0.1U_0402_10V7K
R331 10K_0402_5%
2
+0.9V_LAN
14 13
1 C426
+3.3V_LAN_U22
12
1
2 470P_0402_50V7K
1
2 470P_0402_50V7K
C407
2 0.1U_0402_10V7K
11 10 C427 9 8
2
+3.3V_mSATA_WWAN_U22
15
1 +3.3V_mSATA_WWAN
1 PJP21
TPS22966DPUR_SON14_2X3~D 2
PAD-OPEN1x1m
@ C425 0.1U_0402_10V7K
+3.3V_LAN
LOM_ACTLED_YEL# LOM_SPD100LED_ORG# LOM_SPD10LED_GRN#
13 15 16 42 5
DOCKED
1: TO DOCK
43
A3+
C0+ C0-
A3-
C1+ C1-
SEL
C2+ C2-
LEDA0 LEDA1 LEDA2
C3+ C3LEDC0 LEDC1 LEDC2
PD
17 18 41
LOM_SPD10LED_GRN#
2
SW_ACTLED_YEL# SW_100_ORG# SW_10_GRN#
36 35
DOCK_LOM_TRD0+ DOCK_LOM_TRD0-
32 31
DOCK_LOM_TRD1+ DOCK_LOM_TRD1-
27 26
DOCK_LOM_TRD2+ DOCK_LOM_TRD2-
23 22
DOCK_LOM_TRD3+ DOCK_LOM_TRD3-
19 20 40
<35> <35>
1
DOCK_LOM_ACTLED_YEL# DOCK_LOM_SPD100LED_ORG# DOCK_LOM_SPD10LED_GRN#
B
0.1U_0402_10V7K
O A
DOCK_LOM_TRD0+ DOCK_LOM_TRD0-
<34> <34>
DOCK_LOM_TRD1+ DOCK_LOM_TRD1-
<34> <34>
DOCK_LOM_TRD2+ DOCK_LOM_TRD2-
<34> <34>
DOCK_LOM_TRD3+ DOCK_LOM_TRD3-
<34> <34>
DOCK_LOM_ACTLED_YEL# DOCK_LOM_SPD100LED_ORG# DOCK_LOM_SPD10LED_GRN#
SW_ACTLED_YEL#
Q32B DMN66D0LDW-7_SOT363-6 1 6 LAN_ACTLED_YEL#
4
WLAN_LAN_DISB#
<36>
U24 NL17SZ08DFT2G_SSOP5~D
LAN_ACTLED_YEL#
<35>
MASK_BASE_LEDS#
<40>
SW_10_GRN#
Q33B DMN66D0LDW-7_SOT363-6 1 6 LED_10_GRN# D
12
LEDB0 LEDB1 LEDB2
SW_LAN_TX3+ SW_LAN_TX3-
LOM_SPD100LED_ORG#
S
DOCKED
11
A2-
SW_LAN_TX3+ SW_LAN_TX3-
<35> <35>
MASK_BASE_LEDS# <34> <34> <34>
PAD_GND SW_100_ORG#
LED_10_GRN#
<35>
G
DOCKED
LAN_TX3+R 12NH_0603CS-120EJTS_5% LAN_TX3-R 12NH_0603CS-120EJTS_5%
A2+
25 24
SW_LAN_TX2+ SW_LAN_TX2-
B
@ C198 1 2
2
<21,27,32,36>
2
9 10
B3+ B3-
SW_LAN_TX2+ SW_LAN_TX2-
<35> <35>
MASK_BASE_LEDS# Q33A DMN66D0LDW-7_SOT363-6 4 3
Q32A DMN66D0LDW-7_SOT363-6 4 3 LED_100_ORG#
LED_100_ORG#
<35>
G
5
0: TO RJ45
D
2
LAN_TX2+R 12NH_0603CS-120EJTS_5% LAN_TX2-R 12NH_0603CS-120EJTS_5%
A1-
29 28
SW_LAN_TX1+ SW_LAN_TX1-
+3.3V_LAN
S
1 LAN_TX3+ EMC@ L33 1 LAN_TX3EMC@ L34
2
B2+ B2-
<35> <35>
G
2
A1+
SW_LAN_TX0+ SW_LAN_TX0-
5
1 LAN_TX2+ EMC@ L31 1 LAN_TX2EMC@ L32
7
A0-
SW_LAN_TX1+ SW_LAN_TX1-
P
6
LAN_TX1+R 12NH_0603CS-120EJTS_5% 2 LAN_TX1-R 12NH_0603CS-120EJTS_5%
SW_LAN_TX0+ SW_LAN_TX0-
34 33
G
2
B1+ B1-
38 37
3
1 LAN_TX1+ EMC@ L29 1 LAN_TX1EMC@ L30
3
B0+ B0-
A0+
D
2
S
LAN_TX0+R 12NH_0603CS-120EJTS_5% 2 LAN_TX0-R 12NH_0603CS-120EJTS_5%
G
2
2
1 LAN_TX0+ EMC@ L27 1 LAN_TX0EMC@ L28
D
VDD VDD VDD VDD VDD VDD VDD
U23
B
S
2
39 30 21 14 8 4 1
2
1
C194 0.1U_0402_25V6
1
C193 0.1U_0402_25V6
2
Layout Notice : Place bead as close PI3L500 as possible
C192 0.1U_0402_25V6
1
A
A
5
PI3L720ZHEX_TQFN42_9X3P5~D
MASK_BASE_LEDS#
DELL CONFIDENTIAL/PROPRIETARY PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 5
4
3
2
Compal Electronics, Inc. Title
LAN Lewisville / LAN SW Size
Document Number
Date:
Friday, May 17, 2013
Rev 0.3
LA-9431P Sheet 1
28
of
59
5
4
3
2
1
D
D
+3.3V_RUN
+3.3V_RUN_TPM @ PJP5 1
2 +3.3V_RUN_TPM
PAD-OPEN1x1m
28 26 23 20 17
LPCPD#
V_BAT NBO_13 NBO_14
LAD0 LAD1 LAD2 LAD3
GPIO6 <7> CLK_PCI_TPM_TCM <25,36,37,7> LPC_LFRAME# <25,31,36,37,9> PCH_PLTRST#_EC <12,36,37> IRQ_SERIRQ <10,36,37,9> CLKRUN#
LPC_LFRAME# IRQ_SERIRQ CLKRUN#
21 22 16 27 15
LCLK LFRAME# LRESET# SERIRQ CLKRUN#
TESTBI TESTI
ATEST_1 ATEST_2 ATEST_3
GND_4 GND_11 GND_18 GND_25
2
2
2
USH board conn
2 USH_SMBCLK 2.2K_0402_5% 2 USH_SMBDAT 2.2K_0402_5% 2 USH_PWR_STATE# 1M_0402_5% <11> <11> <37> <37> <36>
12 13 14
CONN@ JUSH1 USBP4USBP4+
USH_SMBCLK USH_SMBDAT BCM5882_ALERT#
USH_SMBCLK USH_SMBDAT
+3.3V_SUS 6 +3.3V_RUN +5V_RUN
9 8
<36> <10> NC_7
1 2 3
@
1 R190 1 R191 1 R195
<9> PLTRST_USH# USH_PWR_STATE# CONTACTLESS_DET#
7 <12>
4 11 18 25
USH_DET#
USH_PWR_STATE#
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
+5V_RUN
1
2
@
+3.3V_RUN +3.3V_SUS
1
2
@
1
2
C206 0.1U_0402_25V6
LPC_LAD0 LPC_LAD1 LPC_LAD2 LPC_LAD3
2 SP_TPM_LPC_EN_R 0_0402_5% LPC_LAD0 LPC_LAD1 LPC_LAD2 LPC_LAD3
2
1
C207 0.1U_0402_25V6
<25,36,37,7> <25,36,37,7> <25,36,37,7> <25,36,37,7>
2 10_0402_5%
10 19 24
1
C208 0.1U_0402_25V6
1 @ R193
VCC_0 VCC_1 VCC_2
SB3V
1
C204 0.1U_0402_25V6
SP_TPM_LPC_EN
5
1
C384 2200P_0402_50V7K
C
PCH_TPM_LPC_EN 1 @ R198
2
U25
C202 2200P_0402_50V7K
<36>
PCH_TPM_LPC_EN
1
C203 2200P_0402_50V7K
<7>
@
C201 4700P_0402_25V7K
2
C200 0.1U_0402_25V6
1
+3.3V_SUS
+3.3V_RUN_TPM
ATMEL TPM for E4
@
C
GND GND
21 22
E-T_6718K-Y20N-00L
AT97SC3204-X4A12-ABF _TSSOP28
ST change to 6718K-Y20N-00L
XB use SA00004WQ50(S IC AT97SC3204-X4A12-ABF TSSOP 28P TPM)
B
B
A
A
DELL CONFIDENTIAL/PROPRIETARY Compal Electronics, Inc. PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
USH board conn / TPM Size
Document Number
Date:
Friday, May 17, 2013
Rev 0.3
LA-9431P Sheet 1
29
of
59
A
B
C
D
E
+3.3V_RUN
<11> <11>
PCIE_PRX_MMITX_P5 PCIE_PRX_MMITX_N5 <7> <7>
<7>
2
2 1
R205 2 0.1U_0402_10V7K 2 0.1U_0402_10V7K
2 PE_REXT 191_0402_1% PCIE_PTX_MMIRX_P5_C PCIE_PTX_MMIRX_N5_C
4
C235 1 C236 1 C237 1 C238 1
2 0.1U_0402_10V7K 2 0.1U_0402_10V7K
PCIE_PRX_MMITX_P5_C PCIE_PRX_MMITX_N5_C
7 8
6 5
2 3
CLK_PCIE_MMI# CLK_PCIE_MMI
15 14
MEDIACARD_PWREN
<12>
AUX _33VIN
SD_SKT_33VOUT
MAIN_LDO_VIN
SD_SKT_18VOUT
22
+3.3V_RUN_CARD
24
+1.8V_RUN_CARD
2
2 1
SD_SKT_33VIN
1
2
SD_33VCCD
@
2
1
4
SD/MMCDAT1
1
4
3
1
2
16
MEDIACARD_IRQ#
17
MMICLK_REQ#
18
IO_LDOSEL
3
SD/MMCDAT0_D
2
DLW21SN900SQ2L-0805_4P 1
SD/MMCDAT1_D
2
@ R297
0_0402_5%
MAIN_LDO_12VOUT CORE_12VCCD SD_WPI SD_CD#
UHSII_12VCCAIN/NC UHSII_12VCCAIN/NC UHSII_12VCCAIN/NC
SD_CLK SD_CMD
PE_12VCCAIN MMC_D7 MMC_D6 MMC_D5 MMC_D4 SD_D3 SD_D2 SD_D1 SD_D0
PE_REXT PE_RXP PE_RXM PE_TXP PE_TXM
SD_RCLK_M/NC SD_RCLK_P/NC SD_D1P/NC SD_D1M/NC SD_D0M/NC SD_D0P/NC
PE_REFCLKM PE_REFCLKP PE_RST#_GATE# MAIN_LDO_EN
SD_REXT/NC
20 21
SDWP SD/MMCCD#
43 45
SD/MMCCLK_R SD/MMCCMD
39 40 44 46 47 48 37 38
EMC@ R230 1
2 10_0402_5%
2 0_0402_5% 2 0_0402_5%
SD/MMCDAT3_R SD/MMCDAT2_R
2
SD_UHS2_D1P SD_UHS2_D1N SD_UHS2_D0N SD_UHS2_D0P R211 1
SD_UHS2_D0N
1
4
3
1
2
3
SD_UHS2_D0P_D
2
SD_UHS2_D0N_D 2
DLW21SN900SQ2L-0805_4P 1
2
@ R315
0_0402_5%
@ R333 1
EMI depop location(EMC)
29 30 32 33 34 35 26
@ R410 1 @ R341 1
4
SD/MMCCLK
1
SD/MMCDAT3 SD/MMCDAT2 SD/MMCDAT1 SD/MMCDAT0
2 0_0402_5%
L47 @ SD_UHS2_D0P
@
2 1
2 1
2 1
36 31 28
PE_RST# <11,12>
2 0_0402_5%
L46 @ SD/MMCDAT0
C255 5P_0402_50V8C
PCIE_PTX_MMIRX_P5 PCIE_PTX_MMIRX_N5
@ R231 1
1
2 1
2 1
2 1
2 2 1
1
41
1 <11> <11>
+SD_IO_LDO
1
C228 C229 near U27.24
@ R306 1
C234 0.1U_0402_25V6
C233 0.1U_0402_25V6
C232 0.1U_0402_25V6
C231 0.1U_0402_25V6
2
+1.2V_LDO_AIN C230 4.7U_0603_6.3V6K
2
1
1
1 2
1 2
1 2
1
1 2
1 2
2
1
2
2 1
1
10
+AUX_LDO
25
C222 1U_0402_6.3V6K
11
12
C221 4.7U_0603_6.3V6K
23
L36
@
AUX_LDO_CAP
UHSII_33VCCAIN/NC SD_IO_LDO_CAP
42
13
1 2 BLM15AG601SN1D_2P
OZ777FJ2LN
PE_33VCCAIN
C216 0.1U_0402_25V6
C226 0.1U_0402_25V6
C225 4.7U_0603_6.3V6K
C219 0.1U_0402_25V6
C224 4.7U_0603_6.3V6K
1
9 27
@
please routing daisy chain 1. from U27.38 (SD_D0) -> U27.32 (SD_RCLK_P) -> L46.4 2. From U27.37 (SD_D1) -> U27.33 (SD_RCLK_N) -> L46.1
C220 4.7U_0603_6.3V6K
C218 0.1U_0402_25V6
C217 0.1U_0402_25V6
C223 4.7U_0603_6.3V6K
2
U27
@
C228 4.7U_0603_6.3V6K
homestay ES1(no SD4.0) SSI ES2(symbol should be update 26~36 pin swap)
use 3.3V
+1.2V_LDO
@
C227 near U27.22
+3.3V_RUN
C229 0.1U_0402_25V6
C215 0.1U_0402_25V6
+1.2V_LDO
C214 0.1U_0402_25V6
C210 close to U27.42 C211 C212 close to U27.23
+3.3V_RUN_AIN C213 4.7U_0603_6.3V6K
C212 0.1U_0402_25V6
C211 4.7U_0603_6.3V6K
C210 0.1U_0402_25V6
1
C227 0.1U_0402_25V6
L35
1 2 BLM15AG601SN1D_2P
+1.8V_RUN_CARD
1
+3.3V_RUN_CARD C215 close to U27.9 C213 C214 close to U27.35
2
+3.3V_RUN
2 0_0402_5%
L48 @ SD_UHS2_D1P
1
SD_UHS2_D1N
4
1
2
4
3
2
SD_UHS2_D1P_D
3
SD_UHS2_D1N_D
DLW21SN900SQ2L-0805_4P
2 4.7K_0402_1%
1
2
@ R337
0_0402_5%
DEV_WAKE# CLKREQ#
LED#
IO0_LDOSEL
GND
19 49
OZ777FJ2LN_QFN48_6X6 MMC+ need confirm
Near to JSD1 3
@ R443 1
+3.3V_RUN_CARD +1.8V_RUN_CARD
+3.3V_RUN_CARD
2 0_0402_5%
JSD1 CONN@ SD/MMCCMD SD/MMCCLK
4 14 2 5
SD/MMCCD# SDWP
18 19
SD/MMCDAT0_D SD/MMCDAT1_D SD/MMCDAT2_R SD/MMCDAT3_R SD_UHS2_D0P_D SD_UHS2_D0N_D SD_UHS2_D1P_D SD_UHS2_D1N_D
7 8 9 1 11 12 16 15
+3.3V_RUN
5
1
1
3
TC7SH08FU_SSOP5~D
2
1
2
@
3 6 10 13 17
+1.8V_RUN_CARD
2
2
@ R214 100K_0402_5%
2
1
PE_RST#
G
A
4
2
2
O
R493
MEDIACARD_RST#
B
R27 100K_0402_5%
<12> IO_LDOSEL
1
PLTRST_MMI#
@
1M_0402_5%
<9>
1
SD/MMCCD# C256 0.1U_0402_25V6
R212 100K_0402_5%
1
@U26 @ U26
P
1
@ C341 @C341 2
C240 4.7U_0603_6.3V6K
1
C239 0.1U_0402_25V6
0.1U_0402_25V6
2
+3.3V_RUN
O2 request 1
2
3
CARD DETECT WRITE PROTEC DAT0/RCLK+ DAT1/RCLKDAT2 CD/DAT3 D0+ DOD1+ D1VSS1 VSS2 VSS3 VSS4 VSS5
GND1 GND2 GND3 GND4 GND5 GND6 GND7
20 21 22 23 24 25 26
ALPS_SCDADA0101_NR
C247 4.7U_0603_6.3V6K
2
C246 0.1U_0402_25V6
1
VDD/VDD1 VDD2 CMD CLK
4
4
DELL CONFIDENTIAL/PROPRIETARY Compal Electronics, Inc. Title PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. A
B
C
D
Card Reader OZ777FJ2 Size
Document Number
Date:
Friday, May 17, 2013
Rev 0.3
LA-9431P Sheet E
30
of
59
5
4
3
2
1
+3.3V_WLAN
<6> <6>
SATA_PRX_mSATATX_P3 SATA_PRX_mSATATX_N3
<6> <6>
3@ C244 1 SATA_PTX_mSATARX_N3 1 SATA_PTX_mSATARX_P3 C245 3@
<36>
2 2
0.1U_0402_10V7K SATA_PTX_mSATARX_N3_C SATA_PTX_mSATARX_P3_C 0.1U_0402_10V7K
HW_GPS_DISABLE2#
53
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52
GND1
+3.3V_mSATA_WWAN
1
+3.3V_WLAN
GND2
JMINI1 PCIE_WAKE# +SIM_PWR
UIM_DATA UIM_CLK UIM_RESET UIM_VPP
WWAN_RADIO_DIS#
MINI_CARD_RST#
<36>
MINI2CLK_REQ#
<7> <7>
CLK_PCIE_MINI2# CLK_PCIE_MINI2
<36,37> <11> <11>
WWAN_SMBCLK WWAN_SMBDAT USBP6USBP6+
<7>
<11> <11>
<11> <11>
EC5048_TX <37> MSCLK PCIE_PRX_WLANTX_N4 PCIE_PRX_WLANTX_P4
PCIE_PTX_WLANRX_N4 PCIE_PTX_WLANRX_P4 <12>
LED_WWAN_OUT# mSATA_DEVSLP
mSATA_DEVSLP
C242 1 1 C243
0.1U_0402_10V7K 2PCIE_PTX_WLANRX_N4_C 2PCIE_PTX_WLANRX_P4_C 0.1U_0402_10V7K
CPPE#
<12> <7> PCH_CL_CLK1 <7> PCH_CL_DATA1 <7> PCH_CL_RST1#
@ R223 1
54
2 0_0402_5%
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51
BT_RADIO_DIS#_R 53
CONN@
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52
GND1
GND2
2
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52
1
1
2
1
2
2
1
2
1
1
2
C262 4.7U_0603_6.3V6K
CLK_PCIE_MINI1# CLK_PCIE_MINI1
CLK_PCIE_MINI1# CLK_PCIE_MINI1
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52
C261 0.1U_0402_25V6
<7> <7>
D
MINI1CLK_REQ#
MINI1CLK_REQ#
+3.3V_WLAN
CONN@
C260 0.1U_0402_25V6
<7>
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51
PCIE_WAKE#
C259 0.047U_0402_16V4Z
+3.3V_mSATA_WWAN JMINI2
PCIE_WAKE#
C258 0.047U_0402_16V4Z
+3.3V_mSATA_WWAN <37>
Mini WLAN/WIiGi/BT H=3.6
@ C257 0.1U_0402_25V6
Mini WWAN/GPS/LTE/mSATA H=3.6
2 D
MSDATA
C241 4700P_0402_25V7K HOST_DEBUG_TX
<37>
WLAN_RADIO_DIS#_R MINI_CARD_RST#
WIGIG60GHZ_DIS#_R USBP2USBP2+ CPUSB#
WIMAX_LED# WLAN_LED# BT_LED# 1 2 @ R222 0_0402_5%
<11> <11> <12>
MSDATA
<37>
WIMAX_LED# STUDY FOR DEBUG 54
LCN_DAN08-52216-0100 1 @R160 @ R160
2 mSATA_DEVSLP 10K_0402_5%
LCN_DAN08-52216-0100 +3.3V_mSATA_WWAN
1 @ R215
+3.3V_mSATA_WWAN
2 0_0402_5%
1 2
2
2
2
1 + 2
1 + 2
<36>
C254 150U_B2_6.3VM_R35M
2
1
3@ C253 150U_B2_6.3VM_R35M
2
1
3@ C252 33P_0402_50V8J
2
WWAN_SMBCLK
1
3@ C251 22U_0805_6.3V6M
DDR_XDP_WAN_SMBDAT
1 0_0402_5% 1 0_0402_5%
3@ C250 33P_0402_50V8J
<18,19,7,9>
2 @ R218 2 @ R219
1
3@ C249 0.047U_0402_16V4Z
DDR_XDP_WAN_SMBCLK
1
3@ C248 0.047U_0402_16V4Z
<18,19,7,9>
@ R217 2.2K_0402_5%
C
@ R216 2.2K_0402_5%
1
D12 1
WLAN_RADIO_DIS#
2
WLAN_RADIO_DIS#_R
RB751S40T1G_SOD523-2
C
@
1 @ R224
2 0_0402_5% D13
<36>
1
WIGIG60GHZ_DIS#
2
WIGIG60GHZ_DIS#_R
PWR Rail
Primary Power
Voltage Tolerance
Peak
Normal
+3.3V
+-9%
1000
750
+3.3Vaux
+-9%
330
250
Aux Power Normal
RB751S40T1G_SOD523-2
WWAN_SMBDAT 1 @ R225
2 0_0402_5%
250 (Wake enable) 5 (Not wake enable)
D14 <36>
1
BT_RADIO_DIS#
2
BT_RADIO_DIS#_R
RB751S40T1G_SOD523-2
LED control circuit
1
+3.3V_HDD
+3.3V_WLAN PJP22 PAD-OPEN1x1m
3.3V_ALW for LID power
UIM_CLK
<40,41>
+COINCELL
VOUT2 VOUT2 GPAD
1
2
4
2
+3.3V_WLAN_U3
15
PJP23
3
1
+3.3V_WLAN
1
WLAN_LED#
PAD-OPEN1x1m
1 @ C422 0.1U_0402_10V7K
WIRELESS_LED#
<36,40>
DMN66D0LDW-7_SOT363-6
2
9 8
S
WIMAX_LED# 10
Q22B 6
DMN66D0LDW-7_SOT363-6 Q30B
1
BT_LED#
2
AUX_EN_WOWL 100K_0402_5%
5
2 470P_0402_50V7K
G
1 C409
B
Q22A D
0.1U_0402_10V7K
11
TPS22966DPUR_SON14_2X3~D
R51
2
2 470P_0402_50V7K
G
VIN2 VIN2
1 @ C428
1 C429
D
6 7
CT2
+3.3V_HDD_U3
12
S
GND
ON2
14 13
2
CT1
VBIAS
5
AUX_EN_WOWL
AUX_EN_WOWL
ON1
4
+5V_ALW <36>
12 11 10 9 8 7 6 5 4 3 2 1 JSH1
VOUT1 VOUT1
G
UIM_DATA UIM_VPP UIM_RESET
3
6 D
+SIM_PWR
12 11 10 9 8 7 6 5 4 3 2 1
3.3V_HDD_EN
2 0_0402_5%
S
<36,40>
+3.3V_ALW LID_CL#
<12>
GND2 GND1
1 @R129 @ R129
R228 1 2 100K_0402_5%
14 13
R227 1 2 100K_0402_5%
VIN1 VIN1
CONN@
2
U3 1 2 B
R229 1 2 100K_0402_5%
+3.3V_ALW
DMN66D0LDW-7_SOT363-6 +3.3V_mSATA_WWAN
O
4
5
4
G D
DELL CONFIDENTIAL/PROPRIETARY
MINI_CARD_RST# 1
A
2
TC7SH08FU_SSOP5~D
B
@ U30 R26 100K_0402_5%
2
MPCIE_RST#
A
DMN66D0LDW-7_SOT363-6 5
1
PCH_PLTRST#_EC <6,7>
3 S
@ C338 2 1
P
<25,29,36,37,9>
Q30A
4
LED_WWAN_OUT# 0.1U_0402_25V6
G
2
+3.3V_RUN
@
3
A
C50 0.1U_0402_16V4Z
1
2 0_0402_5%
ST change to 6718K-Y12N-01L & swap pin
5
1 @R131 @ R131
+3.3V_ALW
R226 1 2 100K_0402_5%
E-T_6718K-Y12N-01L
Compal Electronics, Inc.
@
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
2
Title
Mini Card/SIM Card Size
Document Number
Date:
Friday, May 17, 2013
Rev 0.3
LA-9431P Sheet 1
31
of
59
5
4
3
2
1
D
D
C
C
SA000064200 +3.3V_SUS
1
Dock
0
M/B
1
2
1
2
@
1
2
C416 0.1U_0402_25V6
function
USB3TP3 USB3TN3 USB3RP3 USB3RN3 USBP5+ USBP5-
2
@
C414 0.1U_0402_25V6
DOCKED
<11> <11> <11> <11> <11> <11>
1
C417 0.1U_0402_25V6
check port mapping
2
@
C415 0.1U_0402_25V6
2
1
C418 0.1U_0402_25V6
2
1
C419 0.1U_0402_25V6
1
C420 4.7U_0603_6.3V6K
B
U33 3 9 12 16 20 29
1 2 4 5 6 7 8
VDD VDD VDD VDD VDD VDD
TX+ TXRX+ RXD+ DUSB_ID
TX+A TX-A RX+A RX-A D+A D-A USB_IDA TX+B TX-B RX+B RX-B D+B D-B USB_IDB
OE# <21,27,28,36>
DOCKED
10 32
SS_SEL HS_SEL
GND GND HGND
31 30 27 26 19 18 17
SW_USB3TP3 SW_USB3TN3 SW_USB3RP3 SW_USB3RN3 SW_USBP5+ SW_USBP5-
<33> <33> <33> <33> <33> <33>
25 24 23 22 15 14 13
DOCK_USB3TP3 DOCK_USB3TN3 DOCK_USB3RP3 DOCK_USB3RN3 DOCK_USBP5+ DOCK_USBP5-
<34> <34> <34> <34> <34> <34>
B
11 21 28 33
PI3USB3102ZLEX_TQFN32_6X3
A
A
DELL CONFIDENTIAL/PROPRIETARY Compal Electronics, Inc. PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Mini Card PWR Size
Document Number
Date:
Friday, May 17, 2013
Rev 0.3
LA-9431P Sheet 1
32
of
59
4
3
2
L37 EMC@
<32>
SW_USB3RN3 SW_USB3RP3
4
3
USB3RN3_D-
1
2
USB3RP3_D+
+USB_PWR D15 1
9
USB3RN3_D-
USB3RP3_D+
2
8
USB3RP3_D+
USB3TN3_D-
4
7
USB3TN3_D-
1
USB3TP3_D+
5
6
USB3TP3_D+
+
USBP5_DUSBP5_D+
SW_USB3TN3
<32>
SW_USB3TP3
2 C282 2 C283
1 SW_USB3TN3_C 0.1U_0402_10V7K
4
1 SW_USB3TP3_C 0.1U_0402_10V7K
1
3
2
USB3TN3_D3
2
USB3TP3_D+
TVWDF1004AD0_DFN9
2
USB3RN3_DUSB3RP3_D+
1 @ R239
1
DLW21SN670HQ2L_4P 1 2 @ R237 0_0402_5%
USB3TN3_DUSB3TP3_D+ EMC@D16 EMC@ D16 L30ESDL5V0C3-2_SOT23-3
L38 EMC@ <32>
1
C281 0.1U_0402_25V6
D
2 0_0402_5%
JUSB2 1 2 3 4 5 6 7 8 9
EMC@
USB3RN3_D-
C280 150U_B2_6.3VM_R35M
DLW21SN670HQ2L_4P 1 2 @ R235 0_0402_5% 1 @ R236
1
3
<32>
2
5
2 0_0402_5%
VBUS DD+ GND SSRXSSRX+ GND SSTXSSTX+
CONN@
GND GND GND GND
10 11 12 13 D
SANTA_373070-1
+USB_PWR
+5V_ALW L39 SW_USBP5+
<32>
SW_USBP5-
SW_USBP5+
1
SW_USBP5-
4
EMC@
1
2
4
3
2
USBP5_D+
3
USBP5_D-
U32
1
1 @ R240
2
2 0_0402_5%
C
C284 10U_0603_6.3V6M
DLW21HN900SQ2L_4P 1 2 @ R238 0_0402_5%
1
2
C285 0.1U_0402_25V6
<32>
<36>
1 2 3 4
ESATA_USB_PWR_EN#
GND VOUT VIN VOUT VIN VOUT EN FLG
8 7 6 5
USB_OC2#
<11>
G547I2P81U_MSOP8
C
2
+5V_ALW
R243 100K_0402_5% +5V_USB_CHG_PWR
1 2 0_0402_5%
PWRSHARE_EN#
USB_PWR_SHR_EN#
8 7 6 5
SB# SW_USBP0SW_USBP0+
+3.3V_ALW
<36> DOCKED_LIO_EN <11> USBP0+ <11> USBP0-
VCC S D+ DOE#
1D+ 1D2D+ 2DGND
1 2 3 4 5
SW_USBP0+ SW_USBP0-
1 DOCK_USBP0+ DOCK_USBP0-
<34> <34> 2
1 2 3 4 9
PWRSHARE_EN PS_USBP0_DPS_USBP0_D+ 1 SEL R244
2 +5V_ALW 10K_0402_5%
JUSB1
D
2 G S
1 +
SLG55594AVTR_TDFN8_2X2 2
1
2
USB3RN2_DUSB3RP2_D+
NX3DV221GM_XQFN10U10_2X1P55
DOCKED_LIO_EN
1
check port mapping B
function
1
Dock
0
M/B
1 2 3 4 5 6 7 8 9
USBP0_DUSBP0_D+
Q7 L2N7002WT1G_SC-70-3
USB3TN2_DUSB3TP2_D+
CONN@
VBUS DD+ GND SSRXSSRX+ GND SSTXSSTX+
EMC@ D18 L30ESDL5V0C3-2_SOT23-3
2
C322 0.1U_0402_25V6
1
10 9 8 7 6
C287 0.1U_0402_25V6
+5V_ALW
U36
CB CEN TDM DM TDP DP VddSMART-CDP Thermal-Pad
C291 0.1U_0402_25V6
2 0_0402_5%
C290 150U_B2_6.3VM_R35M
1 @ R242
2
U39 <36>
3
1
1 @R241 @ R241
USB_PWR_SHR_VBUS_EN
3
<36>
GND GND GND GND
10 11 12 13
SANTA_373070-1
B
D17
L40
USB3RP2
1
4
3
1
2
USB3RN2_D-
2
USB3RP2_D+
1
9
USB3RN2_D-
USB3RP2_D+
2
8
USB3RP2_D+
USB3TN2_D-
4
7
USB3TN2_D-
USB3TP2_D+
5
6
USB3TP2_D+
1 @ R247
3
2 0_0402_5%
USB3TN2
<11>
USB3TP2
2
1 USB3TN2_C 0.1U_0402_10V7K
4
2
1 USB3TP2_C 0.1U_0402_10V7K
1
C292 C293
A
4
3
1
2
2
TVWDF1004AD0_DFN9
L41 EMC@ <11>
U35
1
DLW21SN900HQ2L-0805_4P 1 2 @ R246 0_0402_5%
3
USB3TN2_D-
PS_USBP0_D+
EMC@ 4
2
USB3TP2_D+
PS_USBP0_D-
1
1
2
PWRSHARE_EN#
1 2 3 4
GND VOUT VIN VOUT VIN VOUT EN FLG
8 7 6 5
USB_OC0#
<11>
G547I2P81U_MSOP8
L42 3
USBP0_D+
2
USBP0_D-
DLW21SN900HQ2L-0805_4P 1 2 @ R248 0_0402_5%
CMM0805-120Y-N_4P 1 2 @R249 @ R249 0_0402_5%
1 @ R250
1 @R251 @ R251
2 0_0402_5%
+5V_USB_CHG_PWR
+5V_ALW
C289 0.1U_0402_25V6
USB3RN2
<11>
3
EMC@
USB3RN2_D-
C288 10U_0603_6.3V6M
<11>
4
EMC@
2 0_0402_5%
A
DELL CONFIDENTIAL/PROPRIETARY Compal Electronics, Inc. PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
Title
USB x2 Size
4
3
2
Rev 0.3
LA-9431P Date:
5
Document Number Friday, May 17, 2013
Sheet 1
33
of
59
3
<21> <21>
DPC_LANE_P0 DPC_LANE_N0
<21> <21>
DPC_LANE_P1 DPC_LANE_N1
<21> <21> <21> <21>
DPC_LANE_P2 DPC_LANE_N2 DPC_LANE_P3 DPC_LANE_N3
C302 2 C295 2
1 0.1U_0402_10V7KDPC_LANE_P0_C 1 0.1U_0402_10V7KDPC_LANE_N0_C
C297 2 C299 2
1 0.1U_0402_10V7KDPC_LANE_P1_C 1 0.1U_0402_10V7KDPC_LANE_N1_C
R253 1 R255 1
2 33_0402_5% 2 33_0402_5%
DPC_DOCK_LANE_P1 DPC_DOCK_LANE_N1
C304 2 C306 2
1 0.1U_0402_10V7KDPC_LANE_P2_C 1 0.1U_0402_10V7KDPC_LANE_N2_C
R257 1 R263 1
2 33_0402_5% 2 33_0402_5%
DPC_DOCK_LANE_P2 DPC_DOCK_LANE_N2
C300 2 C301 2
1 0.1U_0402_10V7KDPC_LANE_P3_C 1 0.1U_0402_10V7KDPC_LANE_N3_C
R265 1 R266 1
2 33_0402_5% 2 33_0402_5%
DPC_DOCK_LANE_P3 DPC_DOCK_LANE_N3
<24> <24> <21>
DPC_DOCK_AUX DPC_DOCK_AUX#
DPC_DOCK_HPD @
<21>
BLUE_DOCK
<21>
RED_DOCK
<21>
DPC_DOCK_HPD
RED_DOCK GREEN_DOCK
GREEN_DOCK
<21> <21>
HSYNC_DOCK VSYNC_DOCK
<37> <37>
CLK_MSE DAT_MSE
1
C
BLUE_DOCK
2
R268 100K_0402_5%
<26> <26>
DAI_BCLK# DAI_LRCK#
<26> <26>
DAI_DI DAI_DO#
<26>
DAI_12MHZ#
<36> <36>
D_LAD0 D_LAD1
<36> <36>
D_LAD2 D_LAD3
<36> <36>
D_LFRAME# D_CLKRUN#
<36> <36> <7>
D_SERIRQ D_DLDRQ1#
CLK_PCI_DOCK
<37> DOCK_SMB_CLK <37> DOCK_SMB_DAT <36,41,48> B
<37> <36,41,48>
DOCK_SMB_ALERT# <41> DOCK_PSID DOCK_PWR_BTN# SLICE_BAT_PRES#
SLICE_BAT_PRES#
145 146 147 2 1
2
@
151 152 153 154 155 156
GND1 PWR1 PWR1
GND2 PWR2 PWR2
Shield_G Shield_G Shield_G Shield_G Shield_G Shield_G
Shield_G Shield_G Shield_G Shield_G Shield_G Shield_G
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144
DOCK_AC_OFF
DOCK_AC_OFF <48> DOCK_LOM_SPD100LED_ORG# <28> DPB_CA_DET <21,24> 2 33_0402_5% DPB_LANE_P0_C R260 1 2 33_0402_5% DPB_LANE_N0_C R261 1
DPB_CA_DET DPB_DOCK_LANE_P0 DPB_DOCK_LANE_N0
R254 1 R256 1
2 33_0402_5% DPB_LANE_P1_C 2 33_0402_5% DPB_LANE_N1_C
C298 2 C303 2
1 0.1U_0402_10V7K 1 0.1U_0402_10V7K
DPB_DOCK_LANE_P2 DPB_DOCK_LANE_N2
R262 1 R264 1
2 33_0402_5% DPB_LANE_P2_C 2 33_0402_5% DPB_LANE_N2_C
C305 2 C307 2
1 0.1U_0402_10V7K 1 0.1U_0402_10V7K
DPB_DOCK_LANE_P3 DPB_DOCK_LANE_N3
R258 1 R267 1
2 33_0402_5% DPB_LANE_P3_C 2 33_0402_5% DPB_LANE_N3_C
C308 2 C309 2
1 0.1U_0402_10V7K 1 0.1U_0402_10V7K
DPB_DOCK_AUX DPB_DOCK_AUX#
DPB_DOCK_AUX DPB_DOCK_AUX#
<24> <24>
ACAV_DOCK_SRC#
<48>
DPB_LANE_P0 DPB_LANE_N0
<21> <21>
DPB_LANE_P1 DPB_LANE_N1
<21> <21>
DPB_LANE_P2 DPB_LANE_N2
<21> <21>
DPB_LANE_P3 DPB_LANE_N3
<21> <21>
DPB_DOCK_HPD DAT_DDC2_DOCK CLK_DDC2_DOCK
1
<21> <21> 2
SATA_PRX_DKTX_P0 SATA_PRX_DKTX_N0
C312 2 C313 2
1 .01U_0402_16V7K 1 .01U_0402_16V7K
SATA_PTX_DKRX_P0 SATA_PTX_DKRX_N0
C314 1 C315 1
2 .01U_0402_16V7K 2 .01U_0402_16V7K
SATA_PRX_DKTX_P0_C SATA_PRX_DKTX_N0_C
DOCK_USBP5+ DOCK_USBP5CLK_KBD DAT_KBD
<32> <32>
DOCK_USB3TN3 DOCK_USB3TP3
<32> <32>
4
4
<21>
ESD depop location(EMC) Close to DOCK Its for Enhance ESD on dock issue.
DOCK_USBP0+
<33>
DOCK_USBP0-
<33>
DLW21SN900SQ2L-0805_4P @ L43 2 1 @ R269 0_0402_5% 2 1 @ R270 0_0402_5%
<37> <37>
DOCK_USB3RN3 DOCK_USB3RP3
3
@
<6> <6>
2
3
<32> <32>
<6> <6>
SATA_PTX_DKRX_P0_C SATA_PTX_DKRX_N0_C 1 1
2
DOCK_USBP0_D+ DOCK_USBP0_D-
C
DPB_DOCK_HPD
EMI solution for E-Docking USB(EMC)
BREATH_LED# <36,40> DOCK_LOM_ACTLED_YEL#
R271 100K_0402_5%
<28>
DOCK_LOM_TRD0+ DOCK_LOM_TRD0-
<28> <28>
DOCK_LOM_TRD1+ DOCK_LOM_TRD1-
<28> <28>
+3.3V_ALW +LOM_VCT DOCK_DET# 1
+LOM_VCT DOCK_LOM_TRD2+ DOCK_LOM_TRD2-
<28> <28>
DOCK_LOM_TRD3+ DOCK_LOM_TRD3-
<28> <28>
DOCK_DCIN_IS+ DOCK_DCIN_ISDOCK_POR_RST#
2
1 R272
2 10K_0402_5%
@ C316 1U_0402_6.3V6K
<47> <47>
B
<37>
D19 1
DOCK_DET_R#
2
DOCK_DET#
<36,48>
RB751S40T1G_SOD523-2 +DOCK_PWR_BAR 1
2
DAI_BCLK#
CLK_PCI_DOCK @ R273 33_0402_5%
1
2
2
2
@ RE5 10_0402_1% 2
@ RE4 10_0402_1%
ESD depop location(EMC)
D
DPB_DOCK_HPD
DAI_12MHZ# WD2F144WB8 JAE_WD2F144WB8-DT
1 0.1U_0402_10V7K 1 0.1U_0402_10V7K
DPB_DOCK_LANE_P1 DPB_DOCK_LANE_N1
148 149 150 157 158 159 160 161 162
C294 2 C296 2
C318 0.1U_0603_50V7K
1
D20 PESD24VS2UT_SOT23-3
@
C317 0.1U_0603_50V7K
2
CE7 4.7U_0805_25V6-K
1
3
+DOCK_PWR_BAR
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144
C311 0.033U_0402_16V7K
+NBDOCK_DC_IN_SS
C310 0.033U_0402_16V7K
1
2
Close to DOCK Its for Enhance ESD on dock issue.
DPC_DOCK_LANE_P0 DPC_DOCK_LANE_N0
DPC_DOCK_AUX DPC_DOCK_AUX#
DPC_DOCK_HPD
ESD depop location(EMC)
DPC_CA_DET
1
D
DOCK_LOM_SPD10LED_GRN# <21,24> DPC_CA_DET 2 33_0402_5% R259 1 2 33_0402_5% R252 1
CONN@
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143
1
<28>
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143
1
1
JDOCK1 DOCK_DET_1
2
2
4
1
5
1 @CE8 @CE8 4.7P_0402_50V8C
2
1 @CE9 @CE9 4.7P_0402_50V8C
2
@ C319 12P_0402_50V8J
EMI depop location(EMC)
A
A
DELL CONFIDENTIAL/PROPRIETARY Compal Electronics, Inc. Title PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 5
4
3
2
E series Dock Connector Size
Document Number
Date:
Friday, May 17, 2013
Rev 0.3
LA-9431P Sheet 1
34
of
59
5
4
3
T94
<28>
SW_LAN_TX1-
<28>
SW_LAN_TX1+
SW_LAN_TX1-
1
SW_LAN_TX1+
2
1:1
TD1+
TX1+
TD1TX1-
D
C324 0.47U_0603_10V7K
2
SW_LAN_TX0-
SW_LAN_TX0-
4 5
SW_LAN_TX0+
6
TXCT1
TDCT2 TD2+
TXCT2 TX2+
1:1
23
NB_LAN_TX1+
22
RJ45 LOM circuit +3.3V_LAN D
Z2805
21 20
Z2807 NB_LAN_TX0-
19
NB_LAN_TX0+
1
2 <28>
SW_LAN_TX0+
TD2-
TX2-
TX3+
TD3TX3-
+3.3V_LAN:20mils
<28>
SW_LAN_TX2-
SW_LAN_TX2+
10 11
SW_LAN_TX2-
TDCT4 TD4+
12
SW_LAN_TX2+
TXCT3 TXCT4 TX4+
1:1
TD4-
TX4-
17 16 15 14
13
10
LAN_ACTLED_YEL_R#
9
NB_LAN_TX3NB_LAN_TX3-
8
NB_LAN_TX3+
7
NB_LAN_TX1-
6
NB_LAN_TX2-
5
NB_LAN_TX2+
4
NB_LAN_TX1+
3
NB_LAN_TX0-
2
NB_LAN_TX0+
1
NB_LAN_TX3+ Z2806 Z2808 NB_LAN_TX2-
NB_LAN_TX2+
<28>
1
TAIMA_IH-115-F
1
<28> 1
2
<28>
TDCT3
18
1
C326 0.47U_0603_10V7K
2
C325 0.47U_0603_10V7K
9
C
2
R274 1 2 150_0402_5%
LAN_ACTLED_YEL#
75_0402_1%
8
SW_LAN_TX3+
1:1
TD3+
75_0402_1%
SW_LAN_TX3+
7
SW_LAN_TX3-
75_0402_1%
<28>
SW_LAN_TX3-
75_0402_1%
<28>
1
1
JLOM1 <28>
1
1
C321 0.1U_0402_10V7K
2
1
<28>
TDCT1
NB_LAN_TX1-
C320 470P_0402_50V7K
1
C323 0.47U_0603_10V7K
3
24
2
LED_10_GRN# LED_100_ORG#
1 R275 1 R276
2 LED_10_GRN_R# 150_0402_5% 2 LED_100_ORG_R# 150_0402_5%
11 13 12
CONN@
Yellow LEDYellow LED+ PR4PR4+ PR2PR3PR3+ PR2+ PR1GND PR1+ GND
15 C
14
Green LEDOrange LEDGreen-Orange LED+
2
<11>
4
USB3RN1
4
USB3RN1_D-
2
USB3RP1_D+
D34
R280 2
+USB_SIDE_PWR
EMC@
DLW21SN900HQ2L-0805_4P
USB3TN1_D-
4
7
USB3TN1_D-
1 @ R484 1 @ R485
USB3TP1_D+
5
6
USB3TP1_D+
1
2
2 0_0402_5% 2 0_0402_5%
JUSB3
3 TVWDF1004AD0_DFN9
1 + 2
2
2 1 USB3TN1_RP_C C448 0.1U_0402_10V7K
4
<11>
USB3TP1
2 1 USB3TP1_RP_C C449 0.1U_0402_10V7K
1
4 1
3 2
3
USB3TN1_D-
2
USB3TP1_D+
1
USB3TN1
USB3RN1_DUSB3RP1_D+
1
L56 EMC@ <11>
1 2 3 4 5 6 7 8 9
USBP1_R_DUSBP1_R_D+
EMC@D33 EMC@ D33 L30ESDL5V0C3-2_SOT23-3
USB3RP1_D+
C445
USB3RN1_D-
8
0.1U_0402_25V6
9
2
C444
1
USB3RP1_D+
150U_B2_6.3VM_R35M
B
3
USB3RN1_D-
1
USB3RP1
3
R279 2
150P_1808_2.5KV8J use 40mil trace if necessary
L55 EMC@ <11>
Symbol update OK
+GND_CHASSIS
3
1 EMC@C327 EMC@ C327
2
GND CHASSIS
R278 2
R277 2
rev1 SANTA_130456-341
USB3TN1_DUSB3TP1_D+
CONN@
VBUS DD+ GND StdA-SSRXStdA-SSRX+ GND-DRAIN StdA-SSTXStdA-SSTX+
GND GND GND GND
B
10 11 12 13
TAITW_PUBAUE-09FLBS1FF4H0
ST change to PUBAUE-09FLBS1FF4H0
DLW21SN900HQ2L-0805_4P L54 1 @R486 @ R486 1 @R487 @ R487
2 0_0402_5% 2 0_0402_5%
<11> <11>
USBP1+ USBP1-
1 4
1 4
EMC@ 2 3
2
USBP1_R_D+
3
USBP1_R_D-
+USB_SIDE_PWR +5V_ALW
A
GND1 GND2
5 6
1
2
1
2
C447 0.1U_0402_25V6
WIRELESS_ON#/OFF
1 2 3 4
C446
<36>
1 2 3 4
10U_0603_10V6M
DLW21HN900SQ2L_4P 1 2 @ R482 0_0402_5% 1 2 @ R483 0_0402_5%
CONN@ JSF1
U52
<36>
ACES_50277-0040N-001
USB_SIDE_EN#
1 2 3 4
GND VOUT VIN VOUT VIN VOUT EN FLG
8 7 6 5
USB_OC1#
<11>
G547I2P81U_MSOP8
A
DELL CONFIDENTIAL/PROPRIETARY Compal Electronics, Inc. PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
To Sniffer Board 5
4
3
2
Title
RJ45 and USBx1 Size
Document Number
Date:
Friday, May 17, 2013
Rev 0.3
LA-9431P Sheet 1
35
of
59
5
4
3
2
1
+3.3V_ALW
1 R281 1 R282
2 ALS_INT# 10K_0402_5% 2 HW_GPS_DISABLE2# 100K_0402_5%
+3.3V_ALW
+3.3V_ALW_U37 PJP6
2 CPU_DETECT# 100K_0402_5% 2 SLICE_BAT_PRES# 100K_0402_5%
1
2
1 @ R304
U37
MCARD_MISC_PWREN PROCHOT_GATE LID_CL_SIO# DOCK_SMB_ALERT# TOUCH_SCREEN_PD#
B52 A49 B53 A50 B54 A51 B55 A52
USB_SIDE_EN# EN_I2S_NB_CODEC# USH_PWR_STATE# EN_DOCK_PWR_BAR PANEL_BKEN_EC ENVDD_PCH LCD_TST PSID_DISABLE# PBAT_PRES# DOCKED DOCK_DET# AUD_NB_MUTE# MCARD_WWAN_PWREN LCD_VCC_TEST_EN CCD_OFF AUD_HP_NB_SENSE ESATA_USB_PWR_EN#
A33 B36 A34 B37 A35 B38 A36 A37 B40 A38 B41 A39 B42 A40 B43 A41 B44
MODULE_ON SLICE_BAT_ON SLICE_BAT_PRES# MODULE_BATT_PRES#
B32 A31 B33 B15 A15 B16 A16
GPIOA0 GPIOA1 GPIOA2 GPIOA3 GPIOA4 GPIOA5 GPIOA6 GPIOA7 GPIOB0 GPIOB1 GPOC2 GPOC3 GPOC4 GPOC5 GPOC6/TACH4 GPIOC7 GPIOD0 GPIOC1 GPIOC0 GPIOB7 GPIOB6 GPIOB5 GPIOB4 GPIOB3 GPIOB2
10K_0402_5% @ T106 PAD~D <48> SLICE_BAT_ON <34,41,48> SLICE_BAT_PRES# @ T107 PAD~D
CHARGE_PBATT
@ T110 PAD~D
WIGIG60GHZ_DIS#
<31> WIGIG60GHZ_DIS# <31,37> EC5048_TX
1 R309 1 R310 1 R313
mCARD_PCIE_SATA# CPU_DETECT# XFR_ID_BIT#
mCARD_PCIE_SATA# <9> CPU_DETECT#
DP_HDMI_HPD
@ T115 PAD~D
2 LCD_TST 100K_0402_5% 2 SYS_LED_MASK# 10K_0402_5% 2 CHARGE_EN 100K_0402_5%
<29>
BCM5882_ALERT#
BCM5882_ALERT# <12,9> SUSACK# @ T118 PAD~D
EDID_SELECT# VGA_ID
<12>
<40>
<33>
SLP_ME_CSW_DEV#
SLP_ME_CSW_DEV#
<28>
B
SYS_LED_MASK#
WIRELESS_ON#/OFF BT_RADIO_DIS# WWAN_RADIO_DIS# SYS_PWROK DGPU_SELECT#
SIO_SLP_WLAN#
<9>
PCH_DPWROK
A59 B62 A58 B61 A56 B59 A55 B58
B47 A45 B48 A46 B49 A47 WIRELESS_LED# USB_PWR_SHR_VBUS_EN B50 A48 WLAN_RADIO_DIS#
WIRELESS_ON#/OFF BT_RADIO_DIS# WWAN_RADIO_DIS# <9> SYS_PWROK
@ T121 PAD~D <9>
A1 B2 A2 B3 A3 B45 A42 B4
LAN_DISABLE#_R CHARGE_EN SYS_LED_MASK# ALS_INT#
LAN_DISABLE#_R
<12,9> SIO_EXT_WAKE# <31,40> WIRELESS_LED# USB_PWR_SHR_VBUS_EN <31> WLAN_RADIO_DIS# <35> <31> <31>
CPU_VTT_ON 1 2 @ R319
0_0402_5%
B13 A13 A53 B57 B14 A14 B17 B18
GPIOD1 GPIOD2 GPIOD3 GPIOD4 GPIOD5 GPIOD6 GPIOD7 GPIOE0/RXD GPIOE1/TXD GPIOE2/RTS# GPIOE3/DSR# GPIOE4/CTS# GPIOE5/DTR# GPIOE6/RI# GPIOE7/DCD# GPIOF0 GPIOF1 GPIOF2 GPIOF3/TACH8 GPIOF4/TACH7 GPIOF5 GPIOF6 GPIOF7 GPIOG0/TACH5 GPIOG1 GPIOG2 GPIOG3 GPIOG4 GPIOG5 GPIOG6 GPIOG7/TACH6
GPIOI0 GPIOI1 GPIOI2/TACH0 GPIOI3 GPIOI4 GPIOI5 GPIOI6 GPIOI7 GPIOJ0 GPIOJ1/TACH1 GPIOJ2/TACH2 GPIOJ3 GPIOJ4 GPIOJ5 GPIOJ6 GPIOJ7 GPIOK0 GPIOK1/TACH3 GPIOK2 GPIOK3 GPIOK4 GPIOK5 GPIOK6 GPIOK7 GPIOL0/PWM7 GPIOL1/PWM8 GPIOL2/PWM0 GPIOL3/PWM1 GPIOL4/PWM3 GPIOL5/PWM2 GPIOL6 GPIOL7/PWM5 GPIOM1 GPIOM3/PWM4 GPIOM4/PWM6 LAD0 LAD1 LAD2 LAD3 LFRAME# LRESET# PCICLK CLKRUN# LDRQ1# SER_IRQ 14.318MHZ/GPIOM0 CLK32/GPIOM2 DLAD0 DLAD1 DLAD2 DLAD3 DLFRAME# DCLKRUN# DLDRQ1# DSER_IRQ BC_INT# BC_DAT BC_CLK
GPIOH0 GPIOH1 SYSOPT1/GPIOH2 SYSOPT0/GPIOH3 GPIOH4 GPIOH5 GPIOH6 GPIOH7
PWRGD OUT65 TEST_PIN CAP_LDO VSS EP DB Version 0.4 ECE5048-LZY_DQFN132_11X11~D
1
ME_FWP
2
@ R326 @R326 1K_0402_5%
5
@ R320 1 2 100K_0402_5%
ME_FWP PCH has internal 20K PD. (suspend power rail)
A23 B63 A60 A61 B65 A62 B66 A63 B67 A64 A5 B6 A6 B7 A7 B8
SIO_SLP_A#
SIO_SLP_A#
2
2
C332 0.1U_0402_25V6
AUX_EN_WOWL SIO_SLP_LAN# SIO_SLP_SUS# MODC_EN DOCK_HP_DET DOCK_MIC_DET
A8 B9 B10 A10 B11 A11 B12 A12
ME_FWP MASK_SATA_LED# USB_PWR_SHR_EN# LED_SATA_DIAG_OUT#
B60 A57 B64 B68 A9 B1 A18 A44
SUS_ON
B34 B39 B51
HW_GPS_DISABLE2# BREATH_LED#
RUN_ON
BAT1_LED# BAT2_LED#
LPC_LAD0 LPC_LAD1 LPC_LAD2 LPC_LAD3 LPC_LFRAME# PCH_PLTRST#_EC CLK_PCI_5048 CLKRUN#
A22 B21 A32 B35
LPC_LDRQ1# IRQ_SERIRQ
B29 B28 A25 A24 B23 A19 B24 A20
D_LAD0 D_LAD1 D_LAD2 D_LAD3 D_LFRAME# D_CLKRUN# D_DLDRQ1# D_SERIRQ
A29 B31 A30
BC_INT#_ECE5048 BC_DAT_ECE5048 BC_CLK_ECE5048
A4
RUNPWROK
B56
SP_TPM_LPC_EN
B19
1 R321 +CAP_LDO
B27 C1
+3.3V_ALW
8 7 6 5
PROCHOT_GATE XFR_ID_BIT# WWAN_RADIO_DIS# SUS_ON
1 2 3 4
100K_0804_8P4R_5%
ME_FWP <6> MASK_SATA_LED# <40> USB_PWR_SHR_EN# <33> LED_SATA_DIAG_OUT# <40>
+3.3V_RUN
RUN_ON <26,37,39> AC_DIS <41,48> SPI_WP#_SEL <7>
D_CLKRUN#
SUS_ON
D_SERIRQ
<39,43>
BAT1_LED#
<40>trace width 20 mils
BAT2_LED#
<40>trace width 20 mils
D_DLDRQ1# LPC_LDRQ1#
<39>
HW_GPS_DISABLE2# <31> BREATH_LED# <34,40> DIS_BAT_PROCHOT# <48>
RUN_ON CPU_VTT_ON
LPC_LAD0 <25,29,37,7> LPC_LAD1 <25,29,37,7> LPC_LAD2 <25,29,37,7> LPC_LAD3 <25,29,37,7> LPC_LFRAME# <25,29,37,7> PCH_PLTRST#_EC <25,29,31,37,9> CLK_PCI_5048 <7> CLKRUN# <10,29,37,9> IRQ_SERIRQ
SLICE_BAT_ON
2 R299 2 R300 2 R301 2 R296
1 100K_0402_5% 1 100K_0402_5% 1 100K_0402_5% 1 10K_0402_5%
2 R303 2 R305
1 100K_0402_5% 1 100K_0402_5%
2 R307
1 100K_0402_5%
C
<12,29,37>
EC_32KHZ_ECE5048
<37>
D_LAD0 <34> D_LAD1 <34> D_LAD2 <34> D_LAD3 <34> D_LFRAME# <34> D_CLKRUN# <34> D_DLDRQ1# <34> D_SERIRQ <34> BC_INT#_ECE5048 BC_DAT_ECE5048 BC_CLK_ECE5048 RUNPWROK
B
<37> <37> <37>
<37,9>
SP_TPM_LPC_EN
2 1K_0402_5%
<29>
+3.3V_ALW
+CAP_LDO trace width 20 mils CLK_PCI_5048
1
2
RP11
AUX_EN_WOWL <31> WLAN_LAN_DISB# <28> SIO_SLP_LAN# <28,9> SIO_SLP_SUS# <9> GPIO_PSID_SELECT <41> PAD~D T101 @ DOCK_HP_DET <26> DOCK_MIC_DET <26>
USH_PWR_ON PAD~D T100 @
FP_POA_EN
A27 A26 B26 B25 A21 B22 A28 B20
B46
<39,44,9>
SIO_SLP_S4# <39,43,9> SIO_SLP_S3# <39,43,9> IMVP_PWRGD <46> IMVP_VR_ON <46> DOCK_AC_OFF_EC <48>
C336 4.7U_0603_6.3V6K
R322 100K_0402_5%
@ R324 33_0402_5%
@ C339 33P_0402_50V8J
2 R325
LID_CL_SIO#
1 10_0402_1%
LID_CL#
<31,40>
1
2
R317 1 2 100K_0402_5%
+3.3V_ALW
A
2
1 C331 0.1U_0402_25V6
D
2 USB_PWR_SHR_EN# 100K_0402_5% 2 USB_SIDE_EN# 10K_0402_5% 2 WIGIG60GHZ_DIS# 100K_0402_5% 2 USB_PWR_SHR_VBUS_EN <33> DOCKED_LIO_EN 100K_0402_5% 2 DOCK_SMB_ALERT# @ T97 PAD~D 100K_0402_5% <47> PROCHOT_GATE 2 WIRELESS_ON#/OFF 100K_0402_5% DOCK_SMB_ALERT# 2 ESATA_USB_PWR_EN# <34,41,48> @ T98 PAD~D 100K_0402_5% 2 BT_RADIO_DIS# 100K_0402_5% <35> USB_SIDE_EN# <26> EN_I2S_NB_CODEC# <29> USH_PWR_STATE# <48> EN_DOCK_PWR_BAR <22> PANEL_BKEN_EC <10,22> ENVDD_PCH <22> LCD_TST <41> PSID_DISABLE# <41,48> PBAT_PRES# <21,27,28,32> DOCKED <34,48> DOCK_DET# <26> AUD_NB_MUTE# <28> MCARD_WWAN_PWREN <22> LCD_VCC_TEST_EN <22> CCD_OFF <25,26> AUD_HP_NB_SENSE <33> ESATA_USB_PWR_EN# 2 SP_TPM_LPC_EN
<6>
1 C334 0.1U_0402_10V7K
1
C
2
1 C330 0.1U_0402_25V6
2
+3.3V_RUN
2
1 C329 0.1U_0402_25V6
1
1 R287 1 R288 1 R289 1 R291 1 R292 1 R293 1 R295 1 R298
1 C328 PAD-OPEN1x1m 10U_0603_6.3V6M
B5 A17 B30 A43 A54
D
2
1
VCC1 VCC1 VCC1 VCC1 VCC1
1 R284 1 R285
1 2
C337 0.047U_0402_16V4Z A
2 VGA_ID
EMI depop location(EMC)
VGA_ID0 Discrete
0
UMA
1
DELL CONFIDENTIAL/PROPRIETARY Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
4
3
2
Title
SIO & GPIO ECE5048 Size
Document Number
Date:
Friday, May 17, 2013
Rev 0.3
LA-9431P Sheet 1
36
of
59
5
4
3
2
1
+RTC_CELL +RTC_CELL 2 0_0402_5%
1
2
DOCK_PWR_BTN#
+1.05V_RUN
D
1
2
R376
C
1
2
1
2
R366 R368 2
1
2
1
2
1
2
R371 R372 @ R373 1
2
R377
<12> SIO_EXT_SMI# <12> SIO_RCIN# <12,29,36> IRQ_SERIRQ <25,29,31,36,9> PCH_PLTRST#_EC <7> CLK_PCI_MEC <25,29,36,7> LPC_LFRAME# <25,29,36,7> LPC_LAD0 <25,29,36,7> LPC_LAD1 <25,29,36,7> LPC_LAD2 <25,29,36,7> LPC_LAD3 <10,29,36,9> CLKRUN# <12> SIO_EXT_SCI#
2
VOL_UP_R 0.1U_0402_25V6
1
2
VOL_DOWN_R 0.1U_0402_25V6
1
2
VOL_MUTE_R 0.1U_0402_25V6
EMC@ C456
A61 A62 B62
MEC_XTAL1 1 MEC_XTAL2_R 2 0_0402_5% 0_0402_5%
MEC_XTAL2 2 @ R378 1 @ R379
ESD Request
SYSPWR_PRES VCI_OVRD_IN VCI_OUT VCI_IN0# VCI_IN1# VCI_IN2# VCI_IN3#
GPIO011/nSMI/GANG_DATA0 GPIO061/LPCPD# SER_IRQ LRESET# PCI_CLK LFRAME# LAD0 LAD1 LAD2 LAD3 CLKRUN# GPIO100/NEC_SCI
VREF_PECI PECI_DAT
XTAL1 XTAL2 GPIO160/32KHZ_OUT
B66
EMC@ C457
EC_32KHZ_ECE5048
A6 A27 A28 B30 A29 B31 A30 B32 A31 B33 A32 A33
AGND
<36> 1 EMC@ C455
SIO_EXT_SMI# SIO_RCIN# IRQ_SERIRQ PCH_PLTRST#_EC CLK_PCI_MEC LPC_LFRAME# LPC_LAD0 LPC_LAD1 LPC_LAD2 LPC_LAD3 CLKRUN# SIO_EXT_SCI#
GPIO123/BCM_A_CLK GPIO122/BCM_A_DAT GPIO121/BCM_A_INT# GPIO032/BCM_E_CLK GPIO031/GPTP-OUT2/BCM_E_DAT GPIO030/GPTP-IN2/BCM_E_INT# GPIO047/LSBCM_D_CLK GPIO046/LSBCM_D_DAT GPIO045/LSBCM_D_INT#
15mil
2 MEC_XTAL1
1 2
1
2
MEC_XTAL2
Y4 32.768KHZ_12.5PF_Q13FC1350000~D
1
2
C365 22P_0402_50V8J
2
R380 100K_0402_5%
B
1
C364 22P_0402_50V8J
+3.3V_ALW
USH_SMBDAT USH_SMBCLK
B51 A48
ACAV_IN <47,48> ALWON <42>
1
2
PECI_EC
43_0402_5%
C358 1
2 2200P_0402_50V7K
C359 1
2 2200P_0402_50V7K
REM_DIODE4_N REM_DIODE4_P
C361 1
2 2200P_0402_50V7K
VCP THERMATRIP2# THERMATRIP3# THSEL_STRAP PROCHOT#_EC 1 2 V_SYS R381 4.7K_0402_5%
1
2
1
2
1
R453 R452 R353 R364 R365 R401 1 2 3 4
C
1
2
1
+3.3V_ALW
1
+1.05V_RUN
1 R403
2 2.2K_0402_5%
2 B
C
Q12 1 MMST3904-7-F_SOT323-3
2
CHIPSET_ID for BID function
E
2 Q13 B MMBT3904WT1G_SC70-3~D
<12>
H_THERMTRIP#
REM_DIODE2_N
VSET_5075
1
REM_DIODE4_P 2
1 THSEL_STRAP R383
2 1K_0402_5% A
1
1
2
C
2
1
C
E
2 Q14 B MMBT3904WT1G_SC70-3~D
2 2
2
1
3
2
THERMATRIP2# REM_DIODE1_N
REM_DIODE4_N
FWP#
1
1 SYSTEM_ID
1
+5V_RUN @
1
2 Q11 B MMBT3904WT1G_SC70-3~D
+3.3V_ALW
2
BOARD_ID
FAN1_PWM FAN1_TACH
C
E
B
1
1 1
+3.3V_ALW
2
1
1 2
2
1 2
1
2
3
G
S
2
V.R
3
4 6 D
+3.3V_ALW
BOARD_ID rise time is measured from 5%~68%.
4
DP4/DN4
3
1 2
1 1
2
@
1
1 1 2
S
X00 X01 *** X02 *** *** *** A00
DIMM
2 G
2
3 D
2
2
R387
C371 0.1U_0402_25V6
4700p 4700p 4700p 4700p 4700p 4700p 4700p 4700p
DP2/DN2
4 3 2 1
ACES_50277-0040N-001
R394 1.58K_0402_1%
240K 130K 62K 33K 8.2K 4.3K 2K 1K
4 3 2 1
CPU
C367 0.1U_0402_25V6
1
1
Align E5,P5 Fan module pin define then swap pin define
GND2 GND1
DP4/DN4 for Skin on Q14, place Q14 close to Vcore VR choke. @C373 @ C373 100P_0402_50V8J
2
1
2
R402 8.2K_0402_5%
@ C372 100P_0402_50V8J
REV
6 5
1: Channel 1 will provide Thermistor Readings 0: Channel 1 will provide Diode Readings Rest=1.58K , Tp=96 degree
@ R399 10K_0402_5%
C368
<31,36>
pin define different with original part
5
2
R451
+1.05V_RUN
REM_DIODE2_P
R393 10K_0402_5%
EC5048_TX
1
R363
8 7 6 5
E
C369 4700P_0402_25V7K
*
HOST_DEBUG_TX
Pin8 5075_TXD for EC Debug pin9 5048_TXD for SBIOS debug
ACES_50521-01041-P01
2
R361
<47>
DP2/DN2 for SODIMM on Q13, place Q13 close to SODIMM and C372 close to Q13
R386 1K_0402_5%
2 0_0402_5%
R392
C368 4700P_0402_25V7K
@ R398 100K_0402_5%
R397 10K_0402_5%
5048_TX should be change Host_debug_tx 1 @ R400
2 0_0402_5%
RB751V40_SC76-2 D1
@ C370 100P_0402_50V8J
2
R392 1K_0402_5%
R391 10K_0402_5%
R385 10K_0402_5%
+3.3V_ALW
JTAG_TDI JTAG_TMS JTAG_CLK JTAG_TDO MSCLK MSDATA HOST_DEB_TX
2
1 @ R374
REM_DIODE1_P
+3.3V_ALW
R388 49.9_0402_1%
10 9 8 7 6 5 4 3 2 1
1
Place under CPU Place C266 close to the Q11 as possible
driven low when +3.3V_RUN is OFF; driven high when +3.3V_RUN is ON
JTAG_TDI JTAG_CLK MSCLK HOST_DEBUG_TX
A
10 9 8 7 6 5 4 3 2 1
1
<47>
DP1/DN1
10K_8P4R_5%
GND2 GND1
1
2
CARD_SMBDAT GPU_SMBDAT GPU_SMBCLK CARD_SMBCLK
+3.3V_ALW2
22U_0805_6.3V6M C7
5
Q5B DMN66D0LDW-7_SOT363-6
RUN_ON
RP1
12 11
<9>
5075 Channel Location
RUNPWROK
RUN_ON#
+3.3V_ALW
CONN@ JDEG1
1
2
MEC5075-LZY_DQFN132_11X11~D
Q5A DMN66D0LDW-7_SOT363-6
Place close pin A21
<26,36,39>
H=0.98
1
2
C283, C285, C286, C287 Place near U51
VSET_5075
R35 10K_0402_5%
R36 100K_0402_5%
2
+3.3V_ALW
EMI depop location(EMC)
8 7 6 5
2
R866 close to U51 at least 250mils
+PECI_VREF PECI_EC_R REM_DIODE1_N REM_DIODE1_P REM_DIODE2_N REM_DIODE2_P
+3.3V_RUN
C357 0.1U_0402_25V6
@ C363 4.7P_0402_50V8C
@ R382 10_0402_1%
R384 100_0402_1%
C362 1U_0402_6.3V6K
@SHORT PADS~D JTAG1 CONN@
1
Place close pin A29
R359
5075 Setting for Thermal Design
DOCK_POR_RST#
2
1
2.2K_0804_8P4R_5%
CONN@ JFAN1
1
R347
ESR <2ohms
CLK_PCI_MEC
1 2 3 4
2 1K_0402_5%
R367
Thermal diode mapping
2
2
R346
RP3
JTAG_RST#
1
DOCK_SMB_DAT 2.2K_0402_5% DOCK_SMB_CLK 2.2K_0402_5% DYN_TUR_CURRNT_SET# 100K_0402_5% LCD_SMBDAT 2.2K_0402_5% LCD_SMBCLK 2.2K_0402_5% BAY_SMBDAT 2.2K_0402_5% BAY_SMBCLK 2.2K_0402_5% DDR_HVREF_RST_GATE 100K_0402_5% THERMATRIP3# 100K_0402_5% DEVICE_DET# 100K_0402_5% HOST_DEBUG_RX 10K_0402_5%
<29> <29> 1
ACAV_IN ALWON POWER_SW_IN# DOCK_PWR_SW# VCI_IN2# POA_WAKE#
R375 B13 A13 B14 A14 A15 B16 A16 B17 B15 A17 A12 B34 A2 B29 A46 B61
2
<47> <47>
A59 A64 A60 B67 A63 B63 B68
2 1
<34> <34>
CHARGER_SMBDAT CHARGER_SMBCLK
1
XB use SA00005IH1L(S IC MEC5075-LZY-SAL00 DQFN 132P EC) 1
C366 4.7U_0603_6.3V6K
32 KHz Clock
DN1-THERM DP1-VREF_T DN2 DP2 DN3 DP3 DN4 DP4 VIN VSET VCP THERMTRIP2# GPIO002/THERMTRIP3# GPIO024/THSEL_STRAP PROCHOT_IN#/PROCHOT_IO# V_ISYS
DOCK_SMB_DAT DOCK_SMB_CLK
1
2
+3.3V_ALW
C360 0.1U_0402_25V6
1 R369
MSDATA 10K_0402_5% PCH_ALW_ON 100K_0402_5% DOCK_POR_RST# 100K_0402_5% EN_INVPWR 100K_0402_5% A_ON 100K_0402_5% RESET_OUT# 8.2K_0402_5% PCH_RSMRST# 10K_0402_5%
A43 B45 A42 B20 A18 B19 A20 B21 A19
DOCK_SMB_DAT DOCK_SMB_CLK LCD_SMBDAT LCD_SMBCLK BAY_SMBDAT BAY_SMBCLK GPU_SMBDAT GPU_SMBCLK CHARGER_SMBDAT CHARGER_SMBCLK CARD_SMBDAT CARD_SMBCLK USH_SMBDAT USH_SMBCLK
R370 100K_0402_5%
<36> BC_CLK_ECE5048 <36> BC_DAT_ECE5048 <36> BC_INT#_ECE5048 <47,48> ACAV_IN_NB <9> SIO_SLP_S5# <26> BEEP <38> BC_CLK_ECE1117 <38> BC_DAT_ECE1117 <38> BC_INT#_ECE1117
BC_CLK_ECE5048 BC_DAT_ECE5048 BC_INT#_ECE5048 ACAV_IN_NB SIO_SLP_S5# BEEP BC_CLK_ECE1117 BC_DAT_ECE1117 BC_INT#_ECE1117
GPIO003/I2C1A_DATA/GANG_MODE GPIO004/I2C1A_CLK/GANG_START GPIO005/I2C1B_DATA/BCM_B_DAT/GANG_STROBE GPIO006/I2C1B_CLK/BCM_B_CLK/GANG_FULL GPIO012/I2C1H_DATA/I2C2D_DATA/GANG_DATA1 GPIO013/I2C1H_CLK/I2C2D_CLK/GANG_DATA2 GPIO130/I2C2A_DATA/BCM_C_DAT GPIO131/I2C2A_CLK/BCM_C_CLK GPIO132/I2C1G_DATA GPIO140/I2C1G_CLK GPIO141/I2C1F_DATA/I2C2B_DATA GPIO142/I2C1F_CLK/I2C2B_CLK GPIO143/I2C1E_DATA GPIO144/I2C1E_CLK
2 10K_0402_5% VOL_DOWN_R R349 1 VOL_DOWN <40> DEVICE_DET# PS_ID PS_ID <41> ALW_PWRGD_3V_5V ALW_PWRGD_3V_5V <42> 1.05V_A_PWRGD 1.05V_A_PWRGD <44> 2 10K_0402_5% VOL_MUTE_R R352 1 VOL_MUTE <40> ME_SUS_PWR_ACK <9> 1.35V_SUS_PWRGD 1.35V_SUS_PWRGD <43> PM_APWROK PM_APWROK <9> RESET_OUT# RESET_OUT# <15,9> PCH_PCIE_WAKE# PCH_PCIE_WAKE# <9> PCH_RSMRST# PCH_RSMRST# <38> AC_PRESENT AC_PRESENT <12,9> SIO_PWRBTN# SIO_PWRBTN# <9>
2
1
2
R408
GPIO050/FAN_TACH1/GTACH GPIO051/FAN_TACH2 GPIO052/FAN_TACH3 GPIO053/PWM0 GPIO054/PWM1 GPIO055/PWM2 GPIO056/PWM3/GPWM
+RTC_CELL POA_WAKE# 100K_0402_5% VCI_IN2# 100K_0402_5%
2
1
@ R362
A_ON PCH_ALW_ON BIA_PWM_EC FAN1_PWM
Q9 @ L2N7002WT1G_SC-70-3
1
2
DOCK_POR_RST# <12> EC_WAKE# <39,44> A_ON <39> PCH_ALW_ON <22> BIA_PWM_EC
A3 B4 A4 B5 B7 A7 B48 B49 A47 B50 B52 A49 B53 A50
<47>
S
3
1
<34>
B22 A21 B23 B24 A23 B25 A24
<46,47,48,9>
1
2
@ R360
FAN1_TACH
D
2
1
@ R358
VOL_MUTE 100K_0402_5% VOL_DOWN 100K_0402_5% VOL_UP 100K_0402_5% FAN1_PWM 10K_0402_5% FAN1_TACH 10K_0402_5%
2 0_0402_5%
H_PROCHOT# D
2 G
FWP#
1
2
DYN_TUR_CURRNT_SET# SIO_SLP_S0# <9> MSDATA <31> MSCLK <31>
MSDATA MSCLK
1 @ R334
PROCHOT#_EC
2
1
A51 B55 B56 A53 A57
B57 B1 A55 A1 B28 B2 A8 B9 A9 B39 A44 B47 A54 B58
SYSTEM_ID BOARD_ID 2 10K_0402_5% VOL_UP_R R338 1 VOL_UP <40> LAN_WAKE# LAN_WAKE# <12,28> HOST_DEBUG_TX HOST_DEBUG_TX <31> HOST_DEBUG_RX RUNPWROK RUNPWROK <36,9> EN_INVPWR EN_INVPWR <22> PCH_SATA_MOD_EN# PAD~D T123 @ SLICE_PERF_EN <48> PCIE_WAKE# PCIE_WAKE# <31> DDR_HVREF_RST_GATE
1
+3.3V_RUN
JTAG_TDI JTAG_TDO JTAG_CLK JTAG_TMS JTAG_RST#
A10 B10 B8 B27 B44 B46 B26 A25 B36 B37 B38 A34 A35 A36 A40 B43 A45 B65
2
CLK_KBD 4.7K_0402_5% DAT_KBD 4.7K_0402_5% CLK_MSE 4.7K_0402_5% DAT_MSE 4.7K_0402_5%
EP
SML1_SMBDATA SML1_SMBCLK <38> CLK_TP_SIO <38> DAT_TP_SIO <34> CLK_KBD <34> DAT_KBD <34> CLK_MSE <34> DAT_MSE <41> PBAT_SMBDAT <41> PBAT_SMBCLK
A5 B6 A37 B40 A38 B41 A39 B42 B59 A56
H_VSS
2
<7> <7>
SML1_SMBDATA SML1_SMBCLK CLK_TP_SIO DAT_TP_SIO CLK_KBD DAT_KBD CLK_MSE DAT_MSE PBAT_SMBDAT PBAT_SMBCLK
C1
2
1
VSS_RO
2
1
B18
2
1
VR_CAP
2
1
B54
2
1
VSS_ADC
2
1 R357
2
@
VSS
2
1 R356
1
C351 0.1U_0402_25V6
1 R355
2
PAD-OPEN1x1m
C356 0.1U_0402_25V6
R354
1
2 C355 0.1U_0402_25V6
2
+5V_RUN
+3.3V_ALW_U38 PJP7 1
C350 0.1U_0402_25V6
2
A58 B3 A11 A26 B35 A41 A52
C354 0.1U_0402_25V6
2
+3.3V_ALW
2
GPIO021/RC_ID1 GPIO020/RC_ID2 GPIO014/GPTP-IN7/RC_ID3 H_VTR GPIO025/UART_CLK GPIO120/UART_TX GPIO124/GPTP-OUT5/UART_RX VTR_ADC VCC_PWRGD GPIO060/KBRST/BCM_B_INT# GPIO101/ECGP_SCLK/GANG_DATA5 VTR GPIO103/ECGP_MISO/GANG_DATA7 VTR GPIO105/ECGP_MOSI VTR GPIO102/BCM_C_INT#/GANG_DATA6 VTR GPIO104 VTR GPIO106 VTR GPIO116/MSDATA/V2P_COUT_LO/TAP_SEL_STRAP GPIO117/MSCLK/V2P_COUT_HI GPIO127/A20M NFWP GPIO007/I2C1D_DATA/PS2_CLK0B/I2C3A_DATA/GANG_BUSY GPIO010/I2C1D_CLK/PS2_DAT0B/I2C3A_CLK/GANG_ERROR GPIO110/PS2_CLK2/GPTP-IN6 GPIO156/LED0 GPIO111/PS2_DAT2/GPTP-OUT6 GPIO157/LED1 GPIO112/PS2_CLK1A GPIO153/LED2 GPIO113/PS2_DAT1A GPIO027/GPTP-OUT1 GPIO114/PS2_CLK0A GPIO026/GPTP-IN1 GPIO115/PS2_DAT0A GPIO001/ECSPI_CS1 GPIO154/I2C1C_DATA/PS2_CLK1B GPIO015/GPTP-OUT7/GANG_DATA3 GPIO155/I2C1C_CLK/PS2_DAT1B GPIO016/GPTP-IN8/GANG_DATA4 GPIO017/GPTP-OUT8 GPIO145/I2C1K_DATA/JTAG_TDI GPIO107/NRESET_OUT GPIO146/I2C1K_CLK/JTAG_TDO GPIO125/GPTP-IN5 GPIO147/I2C1J_DATA/I2C2C_DATA/JTAG_CLK GPIO126 GPIO150/I2C1J_CLK/I2C2C_CLK/JTAG_TMS GPIO151/GPTP-IN4 JTAG_RST# GPIO152/GPTP-OUT4
B11
2
C349 0.1U_0402_25V6
2
2
C348 10U_0603_6.3V6M
1
2
PCIE_WAKE# 10K_0402_5% BC_DAT_ECE5048 100K_0402_5% BC_DAT_ECE1117 100K_0402_5% PBAT_SMBDAT 2.2K_0402_5% PBAT_SMBCLK 2.2K_0402_5% CHARGER_SMBDAT 10K_0402_5% CHARGER_SMBCLK 10K_0402_5% change to 10K by vendor feedback
A22
VBAT
@ R342 100K_0402_5%
2 2
1
C347 1U_0402_6.3V4Z
+3.3V_ALW
C353 0.1U_0402_25V6
1
1 R340 1 R343 1 R344 1 R345 1 R339 1 R348 1 R350
B64
+3.3V_VTR_ADC
+VR_CAP B12
2 0_0402_5%
B60
1 @ R490
@ R335 10K_0402_5%
U38 +3.3V_ALW_U38
<34>
1
1 <40,9>
1
2
POWER_SW#_MB
2 10K_0402_5%
3
1
C352 1U_0402_6.3V4Z
2
C346 0.1U_0402_25V6
1
2
2
2
1
+3.3V_VTR
@ C342 1 2 1U_0402_6.3V6K 1 R330
DOCK_PWR_SW# C344 1U_0402_6.3V6K
2 0_0402_5%
2 10K_0402_5%
C343 1U_0402_6.3V6K
1 @ R336
+3.3V_ALW_U38
@ C340 1 2 1U_0402_6.3V6K
1 R329
POWER_SW_IN#
R328 100K_0402_5%
2
R327 100K_0402_5%
1
1
+RTC_CELL_VBAT C345 0.1U_0402_25V6
1 @ R332
+RTC_CELL
DELL CONFIDENTIAL/PROPRIETARY PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 2
Compal Electronics, Inc. Title
KBC & SIO MEC5075 Size
Document Number
Date:
Friday, May 17, 2013
Rev 0.3
LA-9431P 1
Sheet
37
of
59
5
4
3
2
1
<12>
I2C1_SCL_TCH_PAD <37>
DAT_TP_SIO
<37>
CLK_TP_SIO
2 0_0402_5% 2 0_0402_5% 2 0_0402_5% 2 0_0402_5%
<12,9>
1
TP_DATA TP_CLK 1
@
2
@
1
2
EMI depop location(EMC)
10P_0402_50V8J C380
10P_0402_50V8J C379
2
@
C378 10P_0402_50V8J
1
C377 10P_0402_50V8J
1 @ R450 1 @ R449 1 @ R441 1 @ R444
CONN@ JKBTP1
KB_DET#
18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
KB_DET#
2
I2C1_SDA_TCH_PAD
2
<12>
Touch Pad
R405 4.7K_0402_5%
D
R404 4.7K_0402_5%
1
+3.3V_TP
@
+5V_RUN +3.3V_ALW <37> BC_INT#_ECE1117 <37> BC_DAT_ECE1117 <37>
1
BC_CLK_ECE1117 +3.3V_TP
2
TP_DATA TP_CLK
GND2 GND1 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
Place close to JKBTP1 +3.3V_TP
+3.3V_ALW
1
2
+5V_RUN
1 @ C374 0.1U_0402_25V6
2
D
1 @ C375 0.1U_0402_25V6
@ C376 0.1U_0402_25V6
2
E-T_6718K-Y16N-01L
EMI depop location(EMC)
ST change to 6718K-Y16N-01L +3.3V_RUN
+3.3V_TP PJP8 1
2
C
C
PAD-OPEN1x1m
@ eDP Cable (30P Normal) Part Number
Description
DC02001PB00
H-CONN SET 0VM MB-EDP-LED-CAM
@ eDP Cable (40P Touch Screen) Part Number
Description
DC02001PA00
H-CONN SET 0VM MB-EDP-LED-CAM-TS
@ Sniffer cable Part Number DC02001P900
Description H-CONN SET 0VM MB-SNIFFER
@ TP_FFC
B
Part Number
Description
NBX0001CV00
FFC 16P F P0.5 PAD=0.3 104.4MM MB-KBTP
B
@ FP FFC Part Number NBX0001CX00
Description FFC 6P G P0.5 PAD=0.3 86.4MM USH/B-FP
@ USH FFC Part Number
RSMRST circuit +5V_ALW
2
RESET#
3
PCH_RSMRST#
5 1 2
RSMRST#
B
O A
GND
Part Number
U42
P
1 2
<37>
GC20323MX00
NBX0001CS00 4
Description BATT CR2032 3V 220MAH MAXELL
FFC 15P F P0.5 PAD=0.3 56.01MM MB-NFC @ Speak
0.1U_0402_25V6 EC SIDE
3
2
VCC
Part Number Description
@ Media Board FFC
G
C387 .01U_0402_16V7K
1
1
NBX0001CU00
@ C386 1 2
1 2
+5V_ALW_U41
@ RTC BATT
@ NFC board _FFC
+3.3V_ALW
R440
10K_0402_5%
U41
Description FFC 20P G P0.5 PAD=0.3 33.5MM MB-USH/B
Part Number
+3.3V_ALW
R411 33_0402_5%
NBX0001CT00
@ R414 @R414 0_0402_5% 1 2
1 @ R413
2 0_0402_5%
PCH_RSMRST#_Q
<9>
Description SPK PACK ZJX 2.0W 4 OHM FG
@ Battery bridge cable
NBX0001CR00
RT9818A-44GU3_SC70-3~D
PK230003Q0L
FFC 8P G P0.5 PAD=0.3 51.8MM MB-MEDIA/B
@ SIM Board FFC + Hall Sensor FFC Part Number
TC7SH08FU_SSOP5~D
Part Number Description
Part Number
Description
DC020014Z10
Description H-CONN SET 0FD M/B-BATTERY 9PIN
FFC 12P G P0.5 PAD=0.3 73.3MM MB-SIM+HALL/B @ UMA DC_IN wire cable
change to E4 solution
Part Number
A
DC30100BN0
Description A
CONN SET 0FD DCJACK-MB WDMD-DCE30004-DF
DELL CONFIDENTIAL/PROPRIETARY Compal Electronics, Inc. PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
KB/TP/RSMRST Size
Document Number
Date:
Friday, May 17, 2013
Rev 0.3
LA-9431P Sheet 1
38
of
59
5
4
3
2
1
DC/DC Interface
+3.3V_ALW_PCH/+1.05V_RUN source 1
+3.3V_ALW_PCH
PJP14 PAD-OPEN1x1m U43 1 2
+3.3V_ALW
<37>
+1.05V_MODPHY
5 6 7
+1.05V_M
GND
ON2
CT2
VIN2 VIN2
VOUT2 VOUT2
S
1 C390
1 C389
11 10
1
9 8
+1.05V_RUN_U43
C391
2 470P_0402_50V7K
15
2
2
1
PJP15
1
+1.05V_RUN
PAD-OPEN1x1m
C393 0.1U_0402_10V7K
2 1
2 0.1U_0402_10V7K
2 470P_0402_50V7K
TPS22966DPUR_SON14_2X3~D @R447 20K_0402_5% 2 1
C413 10U_0603_6.3V6M
+3.3V_ALW_PCH_U43
12
D
+3.3V_SUS/+3.3V_M source +3.3V_SUS 1
2
14 13
<36>
USH_PWR_ON
2 0_0402_5%
SIO_SLP_S4#
1 @ R421
2 0_0402_5%
1 2
1 @ R422
2 0_0402_5%
3
U45 <36,43,9>
<36,43>
SUS_ON
SIO_SLP_A#
G S
<37,44>
A_ON
1 @ R423
2 0_0402_5%
1 @ R424
2 0_0402_5%
VIN1 VIN1 ON1
4
+5V_ALW <36,44,9>
C
PJP16 PAD-OPEN1x1m
1 @ R439
VBIAS
5 6 7
+3.3V_ALW
VOUT1 VOUT1 CT1
CT2
VIN2 VIN2
VOUT2 VOUT2
14 13
+3.3V_SUS_U45
12
C397 1
2 470P_0402_50V7K
1 C396
C398 1
2 470P_0402_50V7K
2 0.1U_0402_10V7K
11
GND
ON2
2
3 4
RUN_ON
CT1
VBIAS
D 3
G
R445 10K_0402_5% 2 1
R442 100K_0402_5% 2 1 6 D
1
G
2 0_0402_5%
S
1 @ R420
D
MPHYP_PWR_EN
RUN_ON
ON1
4
+5V_ALW
VOUT1 VOUT1
GPAD
C412 2200P_0402_50V7K
<12>
<26,36,37>
SIO_SLP_S3#
VIN1 VIN1
3
4
1
DMN66D0LDW-7_SOT363-6 Q124A
MPHYP_PWR_EN# 5 DMN66D0LDW-7_SOT363-6 Q124B
2
6 5 2 1
1.05V_MODPHY_EN
C
SIO_SLP_S3#
2 0_0402_5% 2 0_0402_5% 2 0_0402_5%
Q125 +1.05V_M +1.05V_MODPHY SI3456DDV-T1-GE3_TSOP6
+5V_ALW
+3.3V_ALW2
PCH_ALW_ON
<36,43,9>
1 @ R416 1 @ R417 1 @ R418
2
D
10 9 8
2
+3.3V_M_U45
15
GPAD
1
PJP17
1
TPS22966DPUR_SON14_2X3~D
+3.3V_M
PAD-OPEN1x1m
C399 0.1U_0402_10V7K
2
+3.3V_RUN/+5V_RUN source +5V_RUN B
1
B
U46 1 SIO_SLP_S3# @ R425
2 0_0402_5%
1 @ R426
2 0_0402_5%
RUN_ON
1 2
+5V_ALW
3 4 5 6 7
+3.3V_ALW
VIN1 VIN1 ON1 VBIAS
VOUT1 VOUT1 CT1 GND
ON2
CT2
VIN2 VIN2
VOUT2 VOUT2 GPAD
2
PJP18 PAD-OPEN1x1m
14 13
+5V_RUN_U46
1 C400
12
C401 1
2 470P_0402_50V7K
C402 1
2 1000P_0402_50V7K
2 0.1U_0402_10V7K
11 10 9 8
2
+3.3V_RUN_U46
15
1
TPS22966DPUR_SON14_2X3~D 2
1
PJP19
+3.3V_RUN
PAD-OPEN1x1m
C403 0.1U_0402_10V7K
A
A
DELL CONFIDENTIAL/PROPRIETARY Compal Electronics, Inc. PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
POWER CONTROL Size
Document Number
Date:
Friday, May 17, 2013
Rev 0.3
LA-9431P Sheet 1
39
of
59
5
4
3
2
1
Q23A
D
2 W
3
4 Y
MASK_BASE_LEDS#
2
1 1
2 R429 330_0402_5%
D
BATT_WHITE_LED#
<22>
LED6 1 R430
2 SATA_LED 2 150_0402_5%
1
Q23B
LTW-193ZDS5_WHITE <36>
DMN66D0LDW-7_SOT363-6 1 6
R431 150_0402_5% 1 2
BAT1_LED#_Q
BATT_YELLOW_LED#
<22>
G
<22>
3
2
PANEL_HDD_LED#
BAT1_LED#
D
2 MASK_BASE_LEDS# RB751S40T1G_SOD523-2
S
1
1
BATT_WHITE# BATT_YELLOW#
MASK_SATA_LED# LED_SATA_DIAG_OUT#
2 150_0402_5%
G
S
3
1 R427
BAT2_LED#_Q
LTW-295DSKS-5A_YEL-WHITE
D24 <36>
DMN66D0LDW-7_SOT363-6 4 3
D
S
RB751S40T1G_SOD523-2
5 <36>
Q15 PDTA114EU_SC70-3
DMN66D0LDW-7_SOT363-6 1 6 2
2
BAT2_LED#
5
2
1
<36>
G
D
3
G
S
4
SATA_ACT#
LED7 Q24B
D23 <6>
+5V_ALW
+5V_ALW R428 10K_0402_5%
D
+5V_ALW
Battery LED
HDD LED solution for White LED
+3.3V_ALW
Q24A DMN66D0LDW-7_SOT363-6
1
D
MASK_BASE_LEDS#
R433 150_0402_5% 1 2
Q26 PDTA114EU_SC70-3
3
2
G
4
S
Q25A DMN66D0LDW-7_SOT363-6
G
5
BREATH_LED#
2
G
<34,36>
WLAN LED solution for White LED
+3.3V_ALW
1
1
2
BREATH_WHITE_LED_SNIFF
1 R434
2 150_0402_5%
LTW-193ZDS5_WHITE
Place LED1 close to SW1 LED(white) current need to reach 2mA, need to check current limit resistor 1 R436
2 330_0402_5%
BREATH_WHITE_LED#
<22>
D
3
Q16 PDTA114EU_SC70-3
6
2
2
G
S
1
WIRELESS_LED#
LED1
C
Q25B DMN66D0LDW-7_SOT363-6
2 <31,36>
MASK_BASE_LEDS#
+5V_ALW R432 100K_0402_5%
C
Breath LED +5V_ALW
Q28B DMN66D0LDW-7_SOT363-6 1 6 BREATH_LED#_Q D
SYS_LED_MASK#
2 220_0402_5%
S
1 R438
D
S
1
5
Q28A DMN66D0LDW-7_SOT363-6 4 3
1
MASK_BASE_LEDS#
LED5 1 R435
2 WLAN_LED 150_0402_5%
2
1 LTW-193ZDS5_WHITE
+3.3V_ALW
5
@ C404 1
SYS_LED_MASK#
1 2
U47
B A
O
4
MASK_BASE_LEDS#
MASK_BASE_LEDS#
<28>
TC7SH08FU_SSOP5~D
3
LID_CL#
P
SYS_LED_MASK# <31,36>
G
<36>
0.1U_0402_25V6 2
B
B
<37,9>
2
POWER_SW#_MB
SW1
1 <31,41>
@ JRTC1 1 2 1 G 2 G
+COINCELL
3 4
TYCO_2-1775293-2~D 4
3 SKRBAAE010_4P
POWER & INSTANT ON SWITCH
CONN@ JMEDIA
<37> <37> <37>
6 5 4 3 2 1
VOL_UP VOL_DOWN VOL_MUTE
LED Circuit Control Table
Fiducial Mark @ FD1 1
SYS_LED_MASK#
GND2 GND1 6 5 4 3 2 1
8 7
E-T_6718K-Y06N-01L
LID_CL#
FIDUCIAL MARK~D
Mask All LEDs (Sniffer Function) Mask Base MB LEDs (Lid Closed) Do not Mask LEDs (Lid Opened)
A
@ FD2 1 FIDUCIAL MARK~D
0 1 1
X 0 1
@ FD3 1
DELL CONFIDENTIAL/PROPRIETARY
FIDUCIAL MARK~D
5
4
Compal Electronics, Inc.
@ ST2 H_2P8 PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
1
@ ST1 CLIP_C5P1
1
1
1
1
1
1
1
@ H12 @ H13 @ H14 @ H15 @ H16 @ H17 @ H18 H_2P8 H_2P8 H_2P1 H_2P8 H_2P8 H_2P8 H_2P8
1
@ H11 H_3P4
1
@ H10 H_3P4
1
1
@ H8 @ H9 H_3P4 H_3P4
1
@ H5 H_2P3
1
@ H4 H_2P8
1
@ H3 H_2P8
1
@ H2 H_2P8
1
FIDUCIAL MARK~D
@ H1 H_2P8
1
@ FD4 1
A
ST update symbol to 6718K-Y06N-01L
3
2
Title
PAD & ME & LED Size
Document Number
Date:
Friday, May 17, 2013
Rev 0.3
LA-9431P Sheet 1
40
of
59
5
4
3
2
1
+COINCELL
1
COIN RTC Battery PR1 1K_0402_5%~D 2
+3.3V_RTC_LDO Z4012
+COINCELL
+COINCELL
<31,40>
+RTC_CELL
Primary Battery Connector
+3.3V_ALW
8 7 6 5
1
PC1 1U_0603_10V4Z~D
2
+PBATT PR2 2
100K_0402_5%~D
2
PRP2
1
@ PC2 0.1U_0603_25V7K~D
BAS40CW SOT-323
1
PL2 FBMJ4516HS720NT_2P~D 1 2
PBATT+_C LLTOP_ALLTOP C144LS-109A9-L 9P BATT P2 1 1 2 2 3 Z4304 3 4 Z4305 4 5 Z4306 5 6 6 7 7 8 8 9 9 10 GND 11 GND
PD3
PL1 FBMJ4516HS720NT_2P~D 1 2
3
2
PD2 TVNST52302AB0_SOT523-3
1
1
1 3
2
PD1 TVNST52302AB0_SOT523-3
1 2 3 4
PBAT_SMBCLK PBAT_SMBDAT
<37> <37> PBAT_PRES#
<36,48>
PQ1 ME2301D-G 1P SOT-23-3
100_0804_8P4R_5% PD4 2
1
3
3
1
1
PC3 2200P_0402_50V7K~D 2 1
2
D
3
D
DOCK_SMB_ALERT#
<34,36,48>
SDMK0340L-7-F_SOD323-2~D 2 2
@ PBATT1
@ PR6
GND
<34,36,48>
1
SLICE_BAT_PRES#
2 1
0_0402_5% PC4 2
C
C
1500P_0402_7K~D
+5V_ALW
PR7 1 2 0_0402_5%~D
S 2 G
2 PR10
PQ2 FDV301N_G_NL_SOT23-3~D
2
2
2.2K_0402_5%~D
PR9 33_0402_5%~D 1 2
3
D
1
1
DOCK_PSID
NO
IN
6
GPIO_PSID_SELECT
GND
V+
5
<36>
+5V_ALW
1
PL3 BLM15AG102SN1D_2P 2 1
NB_PSID
PU111 <34> PR8
1
PN: SM010028600
GND 2
@
change from 0603 to 0402 size
3
+3.3V_ALW @ PD5 DA204U_SOT323~D
3
NB_PSID_TS5A63157
NC
COM
4
PS_ID
<37>
TS5A63157DCKR_SC70-6~D
+5V_ALW 1
1
1
100K_0402_1%~D B
C
2 B
PQ3 MMST3904-7-F_SOT323~D
B
PR11 10K_0402_1%~D 2
2
3
E
PR12
@ PR13
15K_0402_1%~D 1
1
2
PSID_DISABLE#
<36>
10K_0402_5%~D
DC_IN+ Source +DC_IN_SS
1
PC10 2 1
10U_0805_25V6K
2 1 100K_0402_5%~D
1 @
PR15
PC8 2
1 2
PC7 @
0.1U_0603_25V7K~D
@ <48>
0.1U_0603_25V7K~D
SOFT_START_GC
2
1
4
<36,48>
A
PR18 2
PQ6A DCX124EK-7-F PNP/NPN_SC74-6~D
PC6
PR14 2
1M_0402_5%~D
1 AC_DIS
2
10K_0402_5%~D
0.1U_0603_25V7K~D
5
5
PR17 1 1
4
1
1 PR16 2 @
4.7K_0805_5%~D
1 @
6
PJP1
@ PJPDC1
PC11
2
2
+DCIN_JACK
@
0.1U_0603_25V7K~D
-DCIN_JACK
PD6
PC9 1000P_0603_50V7K~D 2 1
5 4 3 2 1
2
1 2 3
1M_0402_5%~D
2
DELL CONFIDENTIAL/PROPRIETARY
1
PAD-OPEN 1x3m
Compal Electronics, Inc.
PC12 @ 2
A
5 4 3 2 1
VZ0603M260APT_0603
PQ6B 1
ACES_50299-00501-003 7 GND 6 GND
PQ4 FDMC6679AZ_MLP8-5
+DC_IN PC5 0.022U_0805_50V7K~D 1 2
3
PL4 FBMJ4516HS720NT_2P~D 1 2
DCX124EK-7-F PNP/NPN_SC74-6~D
+DC_IN
Title
0.1U_0603_25V7K~D
5
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4
3
2
+DCIN Size
Document Number
Date:
Friday, May 17, 2013
Rev 0.3
LA-9591P Sheet 1
41
of
58
A
B
C
D
E
+3.3V_RTC_LDO 1
1
+3.3V_ALW2
PR102 10K_0402_5%~D 1 2
PR104 10K_0402_5%~D 2 1
<37>
2
1
@ ALW_PWRGD_3V_5V PR105
PAD-OPEN 1x3m
1
0_0402_5%
VCLK 10
TPS51285BRUKR QFN 20P DRVH2 DRVH1
9
VBST2
1 2 3
BST_3V
UG_5V
17
BST_5V
18
SW1
PC110 0.1U_0603_25V7K 1 2
DRVL1
EN1
PL102 3.3UH_ETQP3W3R3WFN_7A_20% 1 2
1 2
4
3
+DC1_PWR_SRC
FDMC7692S_POWER33-8-5
1
PC114 @ 680P_0603_50V7K
1 + 2
@
PR112 @ 2
1 2 3 2
@ PR111 4.7_1206_5%
PQ103 3 2 1
FDMC7692S_POWER33-8-5
PC118 4.7U_0603_10V6K 2 1
PQ102
3VALWP TDC 6.7 A Peak Current 8.1 A OCP Current 9.72 A Rds(on): 13.6m ohm (max)
PC115 330U_D_6.3VM_R25M
5 EN
LG_5V
4
2
+5V_ALWP
15
20
VREG5
VIN
13
LG_3V
2
FDMC8884_POWER33-8-5
1
@ PC111 680P_0603_50V7K
PC117 0.1U_0603_25V7K 2 1
+
@
PQ101
5
12
SW1
@
4 PR109 2.2_0603_5% 1 2
2
1
1
1
PC113 330U_D_6.3VM_R25M
2
PC112 @
0.1U_0603_25V7K
11
SW2
DRVL2
PL101 2.2UH_ETQP3W2R2WFN_8.5A_20% 2 1
+3.3V_ALWP
8
16
@
3 2 1
VBST1 SW2
PR114 200_0402_1% 1
1
PR110 2.2_0603_5% 1 2
2
PC116 0.1U_0603_25V7K
UG_3V PC109 0.1U_0603_25V7K 1 2
19
2
4
PQ100 FDMC8884_POWER33-8-5
14
5
CS1
PGOOD
PC103 10U_0805_25V6K 2 1
7
PGOOD_3V_5V
21
PC102 10U_0805_25V6K 2 1
1
2 VFB1
3
VO1
PC106 2200P_0402_50V7K 2 1
2
PAD
PC101 0.1U_0402_25V6 2 1
1
4
1
@ PR108
@
EN2
VREG3
6
EN
VFB2
5
1 2
PU100
PR107 100K_0402_1%~D 5
PC104 10U_0805_25V6K 2 1
@
PC107 10U_0805_25V6K 2 1
+PWR_SRC
PC105 2200P_0402_50V7K 2 1
PC108 0.1U_0402_25V6 2 1
@
16.9K_0402_1%
+3.3V_ALW
PL100 1UH_PCMB053T-1R0MS_7A_20% 2 1
2
+DC1_PWR_SRC
PR106
20K_0402_1%~D
+DC1_PWR_SRC
CS2
1
2
PJP100
PC100 4.7U_0603_10V6K 2 1
PR103 0_0402_5% 2
PR101 15K_0402_1% 2 1
2
@
PR100 6.49K_0402_1%~D 1 2
4.7_1206_5%
3
+5V_ALW2
EN
<37>
ALWON
2
@ PR113
PJP101
1
+5V_ALWP
0_0402_5%
1
2
+5V_ALW
5VALWP TDC 4.88 A Peak Current 6.89 A OCP Current 8.268 A Rds(on):13.6m ohm (max)
PAD-OPEN 1x3m PJP102
+3.3V_ALWP
1
2
+3.3V_ALW
PC119 1U_0603_10V6K 2 1
PAD-OPEN 1x3m
@
4
4
Compal Electronics, Inc. Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: A
B
C
D
+5V_ALW/3.3V_ALW Document Number
Rev 0.3
LA-9591P Friday, May 17, 2013
Sheet E
42
of
58
5
4
3
2
1
1.35Volt +/- 5% TDC: 7.2 A Peak Current: 10 A OCP current: 12 A Rds(on): 13.6m ohm(max) +PWR_SRC
0.75Volt +/- 5% TDC 0.525A Peak Current 0.75A OCP Current 0.9A
PJP200
2
D
1
1.35V_B+
D
PJP201 PR200 1 2 2.2_0603_5%~D
PAD-OPEN 1x2m~D
BOOT_1.35V
+VLDOIN_1.35V
2
+1.35V_MEN_P
1
PQ200
1 2 3
PR201 23.7K_0402_1% 1 2
13 PC209 1U_0603_10V6K~D
5
1
VTTSNS
2
21
12
1 2
CS
GND
+V_DDR_REF
RT8207MZQW _W QFN20_3X3
VDDP
VTTREF
3 4
+V_DDR_REF
PR202
1 2 3
1U_0603_10V6K~D
+5V_ALW
FB 1.35V_FB
2
PR204 100K_0402_1%~D
PC213 100P_0402_50V8J~D 2 1
2 <37>
1.35V_SUS_PW RGD
PC212 0.033U_0402_16V7~D
PR205 8.06K_0402_1%~D 2 1
1 @ PR203 4.7_1206_5%
C
FB sense trace when FB pull down to GND
1
+3.3V_ALW
+1.35V_MEN_P
5
6
PC211
FDMC7692S_POW ER33-8-5
VDDQ S3
VDD
S5
11
7
VDD_1.35V
8
2
5.1_0603_5%~D
TON
+5V_ALW
9
1 4 PQ201
PGOOD
680P_0603_50V7K
PC205 22U_0805_6.3V6M
19
18
20 VTT
PAD
VTTGND
PGND
10
1
PU11
CS_1.35V
@ PC208
SNUB_1.35V 2
2
PC207 330U_D2_2VM_R15M
+
C
14
LGATE
VLDOIN
15
BOOT
4
FDMC8884_POW ER33-8-5 PL200 1UH_PCMB063T-1R0MS_12A_20% 1 2
16
DL_1.35V
17
SW _1.35V
UGATE
+1.35V_MEN_P
1
+0.675V_P
PHASE
2 1
PC204
5
1 2
@
0.22U_0603_16V7K~D
@
PC203 2200P_0402_50V7K~D
1 2
PC202 0.1U_0402_25V6
1 2
PC201 4.7U_0805_25V6K~D
2
1
PC200 4.7U_0805_25V6K~D
PAD-OPEN1x1m DH_1.35V
1.35V_SUS_PW RGD PR206
SIO_SLP_S4#
1
1.35V_B+
2
1M_0402_1%~D
S5_1.35V
PR209 10K_0402_1%
@ PR208
1
2 0_0402_5%
1
<18>
1
0.675V_DDR_VTT_ON
2
0.1U_0402_16V7K~D <36,39,9>
Mode S5 S3 S0
S3 L L H
S5 L H H
+1.5V_MEN off on on
+V_DDR_REF off on on
@ PC214 0.1U_0402_16V7K~D
2
0_0402_5%
@ PC215
B
@ PR210
2
SUS_ON
1
<36,39>
1
2
<36,39,9>
@ PR207 0_0402_5%~D 1 2
B
@ PR211 1 2 0_0402_5%~D
SIO_SLP_S3#
+0.75V_P off off(Hi-Z) on
+1.35V_MEN_P
FB sense trace PJP203
2
2
1
1
JUMP_1x3m
+1.35V_MEN_P
PJP204
2
2
1
1
PJP202
+1.35V_MEM
+0.675V_P
JUMP_1x3m
2
+0.675V_DDR_VTT
1 PAD-OPEN1x1m
A
A
DELL CONFIDENTIAL/PROPRIETARY Compal Electronics, Inc. Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5
4
3
2
+1.35V_MEN/+0.675V_DDR_VTT Size
Document Number
Date:
Friday, May 17, 2013
Rev 0.3
LA-9591P Sheet 1
43
of
58
5
4
3
2
1
PJP300 2
+V1.05SP_B+
1
+PWR_SRC
PR301 2.2_0603_5% 1 2
PU300
0_0402_5%~D
3
FB_+V1.05SP
4
RF_+V1.05SP
5
VBST
TRIP
DRVH
EN
SW
VFB
V5IN
RF
DRVL TP
C
@ PR304 <37,39>
1
A_ON
10
UG_+V1.05SP
8
SW_+V1.05SP
6 11
4 PQ301 FDMC7692S_POWER33-8-5
1
10U_0805_25V
PC307 C
220U_B2_2.5VM_R15M
@ PR306
3 2 1 1
+
680P_0603_50V7K 2
4.7_1206_5%
2
2
2
470K_0402_1%
@ PC308
1 @ PC306
PC305 1U_0402_6.3V6K~D
PR305
0.1U_0402_16V7K
+1.05V_MP
+5V_ALW LG_+V1.05SP
1
0_0402_5%
PL300 2.2UH_ETQP3W2R2WFN_8.5A_20% 1 2
7
TPS51212DSCR_SON10_3X3 2
4.7U_0805_25V6K~D PC303 2 1
BST_+V1.05SP
9
1
SIO_SLP_A#
S0 mode be high level
EN_+V1.05SP
PGOOD
2
<36,39,9>
@ PR303 1 2
2
5
95.3K_0402_1%
TRIP_+V1.05SP
PQ300 FDMC8884_POWER33-8-5
1
PR302 2
2
1 1
@
D
1
1.05V_A_PWRGD
PC304 0.1U_0603_25V7K 1 2 3 2 1
2
100K_0402_1%~D
<37>
@
@ 4
PR300
PC302 2
1
PC300 2
5
+3.3V_ALW
2200P_0402_50V7K
1
D
0.1U_0402_25V6 PC301 2 1
PAD-OPEN 1x2m~D
PR307 2
1
4.99K_0402_1%
2
+1.05Volt +/- 5% TDC 3.67 A Peak Current 5.25 A OCP current 6.3 A Rds(on): 13.6m ohm (max)
B
PR308 10K_0402_1% 1
PJP301
+1.05V_MP
2
+1.05V_M
1
B
PAD-OPEN 1x2m~D
DELL CONFIDENTIAL/PROPRIETARY
A
A
Compal Electronics, Inc. Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
+1.05V_M Size
4
3
2
Rev 0.3
LA-9591P Date:
5
Document Number Friday, May 17, 2013
Sheet 1
44
of
58
5
4
3
2
1
+3.3V_RUN +3.3V_ALW D
1
+5V_ALW
1
D
PJP400
@ PJP402
2
2
PC400 1U_0402_6.3V6K
PAD-OPEN1x1m
PU400
1
1
1 PR402 1.54K_0402_1%
APL5930KAI-TRG_SO8
+1.5V_THERMAL
PC403 0.01U_0402_25V7K
1
VIN
9
1 PAD-OPEN1x1m
PC404 22U_0805_6.3V6M
2
47K_0402_5%
0.1U_0402_16V7K
2
PJP401
2
1.5VSP
2
@ PC402
2
@ PR401
FB
PC401 4.7U_0805_6.3V6K
3
2
1
1
100K_0402_5%~D
EN
4
2
8
GND
2
5
1
VIN VOUT VOUT
1
1
PR400
POK
2
7
+3.3V_RUN
VCNTL
6
2
1
PAD-OPEN1x1m
PR403 1.74K_0402_1%
C
2
C
B
B
A
A
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
Deciphered Date
Title
+1.05VS_VTTP/+1.0VSP
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
5
4
3
2
Rev 0.3
Chief River VC
Friday, May 17, 2013
Sheet 1
45
of
58
5
4
3
2
1
20120911 TI-Alex Note: Although there is no pulse-overlap in 1-phase mode, during USR, the pulse comes in immediately. So, the problem with PR504 = DNP is that if there is a high ripple, and USR is faultily detected, you will get a double-pulse. So, we want to make sure USR is not active if it is not necessary. So, I moved it all the way to highest level so PR504 works to 8.87k.
VREF
2 1 PR504
+PWR_SRC
PWM1
8 7 6 5 4 3 2 1
@ PR539 2 0_0402_5% 1
@ PR513 1 2 75_0402_1%
2 1
@ PR516
2
1.91K_0402_1%~D
H_VR_READY
<15>
IMVP_PWRGD
<36>
@ PR540
1 0_0402_5%
+3.3V_RUN PU501
1
+5V_RUN
PR512 2.1K_0402_1%~D 2 1
1
PC511 0.1U_0402_25V6
VIDSCLK
<15>
VIDALERT_N
<15>
VIDSOUT
PR514 43.2K_0402_1% 2 1
1 2
PR529 110_0402_1%
1 2
PR528 75_0402_1%
1 2
1 2 <15>
PR527 54.9_0402_1%
B
@
CSP1
<15>
VCCSENSE
2
@ PR531 0_0402_5% 1
VFB
2
@ PR532 0_0402_5% 1
GFB
from processor <17>
VSSSENSE
1 2 PC502 0.068U_0402_16V7K
+1.05V_VCCST
C
2
PH501 10K_0402_1%_TSM0A103F34D1RZ
H_PROCHOT#
PC509 1U_0603_10V7K~D
3
PR515 3.01K_0402_1% 2 1 2
2 1 PC514
<37,47,48,9>
2
PC510 1U_0603_10V7K~D
1
PR526 10_0603_1%
2
+5V_ALW
@
TI recommend 1nF
CSD97374CQ4M_SON8_3P5X4P5
VIDALERT_N
1
2
PR534 0_0402_5%
PC507 1 2 0.33U_0603_10V7K~D PC512 1500P_0402_50V7K 2 1
1 PR535 4.87K_0402_1%
VIDSCLK
2
VREF
+VCC_CORE PL500 0.22UH_FDUE0640J-H-R22M=P3_25A_20% 4 1
4 3 @PR520 @ PR520 2 0_0402_5% 1SKIP#1 1 2 SKIP#
47P_0402_50V8J~D
1 PR523 2 10K_0402_5%~D
1VR_HOT#
2.32K_0402_1%
100P_0402_50V8~D
6 5
PGND2 PWM BOOT VSW PGND1 BOOT_R VDD VIN SKIP#
PC508 2
1
2
9 8 7
2
2
PC503 1000P_0402_50V7K~D 1 2
PC505 1U_0603_10V6K
1
PR521
1 2 0.1U_0402_25V6 2 1 PR517 0_0603_5%~D
1
1_0603_5%
TPS51622RSM
PC504
PWM1
+3.3V_RUN
PC513 0.068U_0402_16V7K
1
1
PR519
4.7_1206_5%~D
2
1 2 PR522
DROP COMP VREF V5A GND VR_HOT# VCLK ALERT# GND 25 26 27 28 29 30 31 32 33 @ PC506 1 2
PC738
SKIP#
VR_ON SKIP# PWM1 PWM2 N/C PGOOD VDD VDIO
C
<36>
+
2
820P_0603_50V7K~D
CSP1 CSN1 CSN2 CSP2 PU3 N/C GFB VFB
2
<15>
IMVP_VR_ON
VIDSOUT
17 18 19 20 21 22 23 24 VFB
GFB
VBAT SLEWA THERM IMON OCP-I B-RAMP F-IMAX O-USR
CSN1
@
1
2
PU500
H_VR_EN
2 1 @ PR537 0_0402_5%
16 15 14 13 12 11 10 9
CSP1
+
100U_D3L_20VM_R55M
10K_0402_5%~D
+3.3V_RUN +3.3V_RUN
1 2 FBMA-L11-453215-121LMA90T
@ PR536 2 0_0402_5%1
PC735
2
1
33U_D_25VM_R60M
PR511
PL501
PC734 10U_0805_25V6K 2 1
1
+VCC_PWR_SRC
PC732 22U_0805_25V6K 2 1
+VCC_PWR_SRC
2
PAD-OPEN 4x4m
PC731 10U_0805_25V6K 2 1
@ PJP500
1
PC736 22U_0805_25V6K 2 1
PR509
2
D
1
1
PR508
2
O-USR 150K_0402_1%
2 PR507
1
150K_0402_1%
8.87K_0402_1%
PR503 1 2 1M_0402_1%
2 PR502
1
75_0402_1%
2 PR501
1
365K_0402_1%
PC500 1 2
2
F-IMAX
1
PR510 39K_0402_5%~D
B-RAMP
1 PR506
2
SLEWA
@
OCP-I 75K_0402_1%
D
PC501 0.1U_0402_16V7K~D 2 1
PR505 10K_0402_5%~D 1 2
1
2
@ PR500 75_0402_1%
4700P_0603_50V7K
2
PH500
IMON
150K_0402_1%
1
100K_0402_1%_NCP15WF104F03RC
B
CSN1
CPU TDC 10 A Peak Current 32 A OCP Current 38.4 A DCR: 0.82m +-5% ohm PH500 B value: 4250k 1% PH501 B value: 3435k 1%
A
A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc. Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5
4
3
2
+VCC_CORE Size
Document Number
Date:
Friday, May 17, 2013
Rev 0.3
LA-9591P Sheet 1
46
of
58
4
+SDC_IN
PR745 10_1206_5%~D 2 1
1 16
REGN
BQ24715_REGN
ACDET
PHASE
18
SDA
LODRV
SCL
GND
2 4
CHG_UGATE
19
15
CHG_LGATE
14
CELL
/BATDRV
4
BQ24715RGRR_QFN 2
PQ706
10K_0402_1%~D SIRA06DP-T1-GE3_POWERPAKSO-8
@ PR751
GNDA_CHG GNDA_CHG
GNDA_CHG
1
1
TC7SH08FU_SSOP5~D 5
ACAV_IN
PQ712B 4
Adapter Protection Circuit for Turbo Mode
<37,47,48>
DMN66D0LDW-7 2N SOT363-6
PR739 10K_0402_1%~D 2 1
PU2B
P
8 +
7
1 1
G
O -
LM393DR_SO8~D
@ PR741
ACAV_IN_NB
2
<37,48>
0_0402_5% A
2
<36>
3
PROCHOT_GATE
PC730 100P_0402_50V8J~D 2 1
2
A
6
4
PR737 232K_0402_1%~D 2 1
+5V_ALW
5
3
A
PR736 1M_0402_1%~D 1 2
5 P
1
B
O G
1
PR740 100K_0402_5%~D
PR742 22.6K_0402_1%~D 2 1
3
PU3 4
PC728 0.1U_0402_25V4Z~D 1
PC729 100P_0402_50V8J~D 2 1
1
2
2
DYN_TUR_CURRNT_SET#
+DC_IN +3.3V_ALW +3.3V_ALW 1
220P_0402_50V8J
5
2
2 @ PC740
4
LM393DR_SO8~D 1
4
1
6
8 1 2
PC727 220P_0402_50V8J~D
PC726 100P_0402_50V8J~D 2 1
PR735 69.8K_0402_1% 2 1
PR734 210K_0402_1% 1 6 2 <37>
-
BQ24715_REGN
+3.3V_ALW2
PU2A O
2
PQ712A DMN66D0LDW-7 2N SOT363-6
+
P
3
DMN66D0LDW-7 2N SOT363-6 PQ710B
2
PR732 20K_0402_1%~D 1 2
@ PR728 0_0402_5%
PQ710A DMN66D0LDW-7 2N SOT363-6
VCP
B
2
221K_0402_1%~D PR729 1.8M_0402_1% 1 2
G
PR730 150K_0402_1%
<48>
<37,46,48,9>
2
PR727
H_PROCHOT#
@
2
PC724 100P_0402_50V8J~D 2 1
PC725 0.01U_0402_25V7K~D 2 1
Low
2
PAD-OPEN1x1m
10K_0402_1%~D
1
65W
@
+5V_ALW
PC722 1
2
BATDRV#
+3.3V_ALW2
PC721 0.1U_0603_25V7K~D 1 2
0.1U_0603_25V7K~D
PJP701 1
+5V_ALW
High
@
2
B
DYN_TUR_CURRENT_SET#
@
PR744
1
+3.3V_ALW2
2 0_0402_5%
2
10K_0402_1%~D
1
CHARGER_CELL_PIN
3
@
@ PC720 0.1U_0603_25V7K~D 1 2
PR738 48.7K_0402_1% 2 1
<48>
@PR750 @ PR750
PR724 1
GNDA_CHG
PR722 4.02K_0402_1% 1 2
11
3 2 1
PR711
2
SRN
2
IOUT
10K_0402_1%~D BQ24715_REGN 1
12
4.7_1206_5%~D
10
1
5 @ PR726 2
TP
1
1
13
21
2
PC719 100P_0402_50V8J~D
V_SYS
4
PR718 0_0402_5%
SRP
10U_0805_25V6K 1 2
ACOK
PC716 2 1
5
PC737 10U_0805_25V6K 2 1
2
+VCHGR
PR716 0.01_1206_1%~D
PL701
GNDA_CHG
45W
+PWR_SRC
3.3UH_FDVE1040-H-3R3M=P3_11.3A_20%~D 2 1
1
PR746 121K_0402_1%~D 2 1
C
PQ704 SIRA14DP-T1GE3_POWERPAK-SO8-5
PC718 10U_0805_25V6K 2 1
HIDRV
PC717 10U_0805_25V6K 2 1
ACDRV
PR715 2.2_0603_5% 1 2
PC742 22U_0805_25V6M 2 1
BTST
PC741 22U_0805_25V6M 2 1
17
CMSRC
PC715 0.1U_0603_25V7K~D 2 1
9
7
GNDA_CHG
<48>
PR719 0_0402_5% 1 2
8
+3.3V_ALW
CSSP_1
1U_0603_10V6K~D PD702 BAT54HT1G_SOD323-2~D
0_0402_5%
<37>
1
1
PR705 1 2
3
PR704 10_0402_5%~D 1 CSSP_1
3
DK_CSS_GC
PR743 42.2K_0402_1%~D 2 1
@ PR717
1
Discrete current monitor circuit 2
PC712 22U_0805_25V6M 2 1
4
6
1
PR749
59_0402_1%
0.1U_0603_25V7K~D
1
1
2
VCC
BQ24715_REGN
ACAV_IN
4
INA199A1DCKR_SC70-6~D
@ PR709
PC714 820P_0603_50V7K~D
PR747 100K_0402_1%~D 1
PC733
2 <37,47,48>
IN+
2
<34>
PC711 22U_0805_25V6M 2 1
3
1
CHARGER_SMBCLK
IN-
V+
0_0402_5%
0.1U_0402_25V6
<37>
GND
5
2
GNDA_CHG
CHARGER_SMBDAT
DOCK_DCIN_IS-
3
PC709 1 2 2
20
+DCIN
0_0402_5%
<37>
+SDC_IN
4
PR748 44.2_0402_1%~D 2 1
5
3 2 1
2 PC708 C
PU700
@ PR725
1
PC705 1 2
6
GNDA_CHG GNDA_CHG
+SDC_IN 1
1
2
1
PR713 261K_0402_1% PR714 49.9K_0402_1%~D 2
PQ703B SI3993CDV-T1-GE3_TSOP6~D
0.1U_0603_25V7K~D
ACN
2
PC706 10U_0805_25V6K 2 1
PC704 0.1U_0603_25V7K~D 1 2
ACP
+SDC_IN
2
PC703 1U_0603_25V6K 1 2
Out
<34> 2
D
2
1_0805_1%~D
DOCK_DCIN_IS+
G
1
+CHGR_DC_IN
REF
CSSN_1
6
S
<48>
@ PR708
5
D
BAT54CW_SOT323~D
S
PR703 10K_0402_5%~D 2 1
1
PQ703A SI3993CDV-T1-GE3_TSOP6~D
G
1 3
D
PU703
S
S
PQ702 NTR4502PT1G_SOT23-3~D
2
+DC_IN_SS
1
PQ701 NTR4502PT1G_SOT23-3~D
2 G PD701
@ PR710 0_0402_5% 2
VCP
D 2 G D
PR707 100K_0402_1%~D 2 1
2
0_0402_5%
+DOCK_PWR_BAR
sense adapter
PC713 0.047U_0603_25V7M 2 1
CSS_GC
2
<37>
PR706 100K_0402_1%~D 1
<48>
PAD-OPEN 4x4m
2
0_0402_5% D
1
2
3
<48> @ PR702 1
1
3
CSSN_1
DC_BLOCK_GC
CHAGER_SRC
PJP700
4
10_0402_5%~D
2
2
@ PR701 1
@
1
@
1
4
PR700 0.01_1206_1%~D
1
1 2 3
5
+DC_IN_SS
2
PL700 1UH_PCMB042T-1R0MS_4.5A_20% 2 1
+PWR_SRC_AC
V30415-T1-GE3 1P POWERPAK1212-8
PC700 0.1U_0603_25V7K~D
PQ700
3
PC707 2200P_0402_50V7K~D 2 1
5
DELL CONFIDENTIAL/PROPRIETARY Compal Electronics, Inc. Title
+GPU_CORE THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5
4
3
2
Size
Document Number
Date:
Friday, May 17, 2013
Rev 0.3
LA-9591P Sheet 1
47
of
58
O
+3.3V_ALW
1
A
PQ802A DMN66D0LDW-7 2N_SOT363-6~D
2
+PWR_SRC_AC
6 2
1
2 1
8 7 6 5
3301_DSCHRG_FET_GC 3
<36,48>
4 B A
6 1
6
PU804
TC7SH08FU_SSOP5~D
1 @ PR812 2
DIS_BAT_PROCHOT#
4
O
2
PQ805A DMN66D0LDW-7 2N_SOT363-6~D
2
@ PD818 SDMK0340L-7-F_SOD323-2~D 1
2
CHARGER_CELL_PIN
<47>
0_0402_5%
+DOCK_PWR_BAR 5
2
PC811 0.01U_0603_25V7K~D
<36>
2
PR814 330K_0402_5%~D 2 1
1
SLICE_BAT_ON
PQ810 FDS6679AZ-G_SO8~D
2
5
PR821 820_0603_5%~D 1 2
4
STSTART_DCBLOCK_GC
1 2 3 1 PD808 PDS5100H-13_POWERDI5-3~D
PQ812B DMN66D0LDW-7 2N_SOT363-6~D 4 3
PBAT_PRES#
4
1
PBAT_PRES#
DMN66D0LDW-7 2N_SOT363-6~D
5
SLICE_BAT_ON
PQ806A
4
FDS6679AZ-G_SO8~D
+3.3V_ALW PC805 0.1U_0402_10V7K 1 2
1
2200P_0402_50V7K~D PC807 @ PR811 1 2 2 1 0_0402_5% 0.47U_0805_25V7K~D
<34,36,41,48>
5
SLICE_BAT_PRES#
P
5
2
3
2 DMN66D0LDW-7 2N_SOT363-6~D PQ807B
G
PR817
3
4
1
330K_0402_5%~D
3
8 7 6 5
1
1 2 3
D
0.1U_0603_25V7K~D PC806 1 2
PQ811
+PBATT
PR816 100K_0402_5%~D
PQ805B DMN66D0LDW-7 2N_SOT363-6~D
5
PR810 100K_0402_5%~D
PQ806B
2
1
2
DMN66D0LDW-7 2N_SOT363-6~D
DMN66D0LDW-7 2N_SOT363-6~D PQ807A
2
+3.3V_ALW2
<37,46,47,9>
1 PR807 100K_0402_5%~D
+3.3V_ALW PC803 1 2
H_PROCHOT#
3
TC7SH08FU_SSOP5~D
PR808
+3.3V_ALW
6 4
3
2
1
B
2
SLICE_BAT_ON
1
4
PR804 100K_0402_5%~D
2 1
<36,41>
1
SLICE_BAT_PRES#
PU801
+3.3V_ALW2
PQ812A DMN66D0LDW-7 2N_SOT363-6~D
PR801 100K_0402_5%~D 2 1 5
2
+NBDOCK_DC_IN_SS
PR802 100K_0402_5%~D
PC801 0.1U_0402_10V7K 1 2
100K_0402_5%~D PR815 10K_0402_5%~D
2 2
1
PR813 100K_0402_5%~D 1 2 PD811
1
6
BATDRV#
3
1
4 <47>
SDMK0340L-7-F_SOD323-2~D
PQ800 SI4835DDY-T1-GE3_SO8~D 1 8 2 7 3 6 5
1
PQ809 SI4835DDY-T1-GE3_SO8~D 1 8 2 7 3 6 5
1
+3.3V_ALW
Purpose: Trigger PROCHOT# when active battery is removed from system. Allows EC to re-establish system performance for battery next in line.
2
+VCHGR
2
1
D
PD800 PDS5100H-13_POWERDI5-3~D 3 1 2
+PBATT_IN_SS
2
PQ801 NTR4502PT1G 1P SOT23-3 3
+BATT_SUM
3
PD807 SDMK0340L-7-F_SOD323-2~D
P
4
PD806 PDS5100H-13_POWERDI5-3~D 3 1 2
G
5
PQ826 FDMC6679AZ_MLP8-5
+3.3V_ALW2
5 P
1 3
3
A
TP
ERC3
ERC2
CSS_GC DK_CSS_GC
@ PR868 1
2
0_0402_5%
@
STSTART_DCBLOCK_GC @ PR877 1 2 0_0402_5%
2
1
6
3
PQ818
1 1
1 3
1
+3.3V_ALW2
3
S
1
D
1
PR837 100K_0402_5%~D
3
PC814 0.1U_0402_10V7K 2 1
2 G
+3.3V_ALW2
1 5
1 4
+PBATT
B A
O 3
DOCK_DET#
1 2
SLICE_BAT_PRES# DOCK_DET#
<34,36,41,48> <34,36,48>
PR864 100K_0402_5%~D
PU808 TC7SH08FU_SSOP5~D
2
2
P
1 3
2
G
2
<36>
@ PR869 1
ACAV_IN#
<37,47,48> 1
2
240K_0402_5%~D @ PR856
D
2 G S
3301_PWRSRC
2
3 1
2
EN_DOCK_PWR_BAR
0_0402_5%~D 2 1
PQ827 @ DMN65D8LW-7_SOT323-3~D
DOCK_DET#
<34,36,48>
<37,48>
+3.3V_ALW2
B
<34,36,41,48>
PQ831
2 2
@ PQ823 ME2301D-G 1P SOT-23-3
+3.3V_ALW
PR874 1 2 1M_0402_5%~D
3
5 <34,36,41,48>
3 @ PR866 0_0402_5% 1
2 P33ALW
SLICE_PERF_EN <34,36,48>
SLICE_BAT_PRES#
DMN65D8LW-7_SOT323-3~D
1
<36> <37,48>
2
@ PR834 2
1M_0402_5%~D SLICE_BAT_PRES#
@ PR863 1 2 0_0402_5%
CD3301BRHHR_QFN36_6X6~D
2
PR853 0_0402_5% 1 2
2 1
0_0402_5%~D
PR848 1 1 @ PR860 0_0402_5% 2
PQ822 NTR4502PT1G 1P SOT23-3
+DC_IN_SS
<37,47>
DOCK_AC_OFF_EC PR858
1
ACAV_IN
@ PR870 1
2
D
S
2 G
@ PQ824A DMN66D0LDW-7 2N_SOT363-6~D 1 6
2
47K_0402_5%~D 1
@ PR872
0_0402_5% PQ825 DMN65D8LW-7_SOT323-3~D
+NBDOCK_DC_IN_SS
EN_DK_PWRBAR PC817 0.1U_0402_25V4Z~D 2 1
PC816 0.047U_0603_25V7M 2 1
PC815 0.1U_0603_25V7K~D 2 1
<47> <47>
ACAV_IN_NB
1 2 @ PR857 0_0402_5%
<37,48>
PD821 SDMK0340L-7-F_SOD323-2~D
PR836 100K_0402_5%~D
@ PR852 0_0402_5%
2
A
@ PR851 0_0402_5%~D
@ PR855 0_0402_5% 1 2
1
10 11 12 13 14 15 16 17 18
37
3301_ACAV_IN_NB DK_AC_OFF_EN SL_BAT_PRES#
1
2 2
1 PR840 2 100K_0402_5%~D
1
@ PR862 1 2 0_0402_5%
DK_AC_OFF
3
+3.3V_ALW2
@ PR859 1 2 0_0402_5%
27 26 25 24 23 22 21 20 19
SLICE_PERF_EN
@ PQ819A DMN66D0LDW-7 2N_SOT363-6~D
1
ACAV_IN
P50ALW PBATT_OFF DK_AC_OFF_EN ACAV_IN_NB GND DK_AC_OFF_EN SL_BAT_PRES# BLKNG_MOSFET_GC NBDK_DCINSS
<36,48>
SDMK0340L-7-F_SOD323-2~D
DMN65D8LW-7_SOT323-3~D
+3.3V_ALW2
SLICE_BAT_ON
ACAV_IN#
3
<37,47,48>
DC_BLOCK_GC
DC_IN SS_GC ERC1 ACAVDK_SRC GND SDC_IN DC_BLK_GC ACAV_IN P33ALW2
@PR850 @ PR850 2 0_0402_5%
2
5
2
@ PQ824B
@ PR875 100K_0402_5%~D
4
A
DMN66D0LDW-7 2N_SOT363-6~D 3
5
0_0402_5% CD3301_SDC_IN
<47>
1 2 3 4 5 6 7 8 ACAVIN P33ALW2 9
+5V_ALW
PD816
PQ828
2
ERC1
1 CD_PBATT_OFF
BAT54CW_SOT323~D
@
0_0402_5%
1
@ PR854 1 2
3
@ PR843 0_0402_5% 2
1
2 G S
1
PQ821A DMN66D0LDW-7 2N_SOT363-6~D PR839 1 6 2 1 100K_0402_5%~D DOCK_AC_OFF <34> PQ821B DMN66D0LDW-7 2N_SOT363-6~D 4 3 PR849 @ PR844 2 1 10K_0402_5%~D 100K_0402_5%~D
2
+SDC_IN
@ PR847 1 2ACAVDK_SRC 0_0402_5%
1
+PBATT P50ALW
2
@ PR861 0_0402_5%
DOCK_DET#
2
ACAV_DOCK_SRC#
SLICE_PERF_EN <34,36,48>
<34,36,41>
D
+NBDOCK_DC_IN_SS
<34,36,41,48>
1
100K_0402_5%~D <34>
PU800
1
0_0402_5%
NC CHARGERVR_DCIN DC_IN_SS DK_PWRBAR GND NC BLK_MOSFET_GC DSCHRG_MOSFET_GC PBatt+
PR846 <41>1 SOFT_START_GC 2
2
@PR838 @ PR838
CSS_GC DK_CSS_GC ERC3 ERC2 GND PWR_SRC SS_DCBLK_GC EN_DK_PWRBAR P33ALW
+3.3V_ALW2
<37,48> PD815 2
36 35 34 33 32 31 30 29 28
2
PC813 0.1U_0603_50V4Z~D
SLICE_BAT_PRES# 1 2
@
0_0402_5%
1
1
47_0805_5%~D
@
3
2 @ PR833 0_0402_5%
CD3301_DCIN
+DOCK_PWR_BAR
1 3301_DSCHRG_FET_GC
2
1
+CHGR_DC_IN
DSCHRG_MOSFET_GC
2
CHGVR_DCIN DC_IN_SS DK_PWRBAR
PR835
1
100K_0402_5%~D
<36,48>
DMN65D8LW-7_SOT323-3~D
3
PR827 1 2 100K_0402_5%~D
G
<47>
+DC_IN
@ 2 PR841
100K_0402_5%~D
PQ819B DMN66D0LDW-7 2N_SOT363-6~D
G
SLICE_BAT_ON 1 @ PR825 2
2
3 1
2 2
5
+3.3V_ALW2
1
1
DOCK_SMB_ALERT#
3
PR829
D
+DC_IN_SS
PR824 @
1
1
B
O
for Slice battery discharge without AC exist
PR823
S
@ PR831 0_0402_5% 1 2
B
+3.3V_ALW2 Purpose: Turn on the PQ817
+3.3V_ALW2 2
3
4
PD819 SDMK0340L-7-F_SOD323-2~D 1 2
NTR4502PT1G_SOT23-3~D PQ830
2
1
PQ813B DMN66D0LDW-7 2N_SOT363-6~D 4 3
3
S
1
<34,36,48>
1
PR822
PU807 TC7SH08FU_SSOP5~D
C
+3.3V_ALW2
2 DOCK_DET# G PQ817 DMN65D8LW-7_SOT323-3~D
S
PC812 0.1U_0402_10V7K 2 1 PD814 SDMK0340L-7-F_SOD323-2~D 1 2
100K_0402_5%~D
100K_0402_5%~D @ PR832 0_0402_5% 2 1
PR819 2
D
1 @ PR820 2 ACAV_IN#
2
+3.3V_ALW2
PQ814 NTR4502PT1G 1P SOT23-3
2 D PQ832 DMN65D8LW-7_SOT323-3~D
2 G
6 2
PR826
2
PR828 1 2 10K_0402_5%~D
AC_DIS
1
<36,41>
1
0_0402_5% PQ813A DMN66D0LDW-7 2N_SOT363-6~D 1
3
<34,36,41,48>
PD820 SDMK0340L-7-F_SOD323-2~D 1 2 SLICE_BAT_PRES#
SLICE_BAT_PRES#
2
3
5
1
0_0402_5%
2 G
2
2
PR830 100K_0402_5%~D
A
100K_0402_5%~D
1
S
SDMK0340L-7-F_SOD323-2~D 1
A
B
O
D
PD813
1
B
O
Purpose: Turn on the PQ817 for primary or module bay battery to provide power to dock side without AC exist. <34,36,41,48>
5
3
@ PR895 0_0402_5%
4
SDMK0340L-7-F_SOD323-2~D
P
2
1
3
1
+3.3V_ALW
1
PQ829 SI2301CDS-T1-GE3 1P_SOT23-3
0_0402_5%~D
2
P
1 2
4
0.1U_0402_10V7K
2
1
+3.3V_ALW2
PQ816 AO3418_SOT23-3
8 7 6 5
FDS6679AZ-G_SO8~D
@ PR894
1 PD810
2 1 10K_0402_5%~D
1 2 3
4
PQ815
PC810 2 1 PU806 TC7SH08FU_SSOP5~D
G
2 1
PR818
2
@ PC809 1500P_0402_7K~D
100K_0402_5%~D
C
G
1 2 3
PC808 0.1U_0402_10V7K 2 1 PU805 TC7SH08FU_SSOP5~D
+3.3V_ALW2
4
4
SLICE_PERF_EN
+PWR_SRC_AC
DELL CONFIDENTIAL/PROPRIETARY Compal Electronics, Inc. PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Selector Size
Document Number
Date:
Friday, May 17, 2013
Rev 0.3
LA-9591P 1
Sheet
48
of
58
5
4
3
2
1
Based on PDDG rev 0.7 Table 5-1.
+VCC_CORE
D
D
1
2
1 PC900 22U_0805_6.3V6M
1
2
1 PC905 22U_0805_6.3V6M
1
2
2
1 PC901 @ 22U_0805_6.3V6M
2
1 PC906 22U_0805_6.3V6M
1 PC910 @ 22U_0805_6.3V6M
2
2
1 PC902 @ 22U_0805_6.3V6M
2
1 PC907 @ 22U_0805_6.3V6M
1 PC911 @ 22U_0805_6.3V6M
2
2
1 PC903 22U_0805_6.3V6M
2
1 PC908 22U_0805_6.3V6M
1 PC912 22U_0805_6.3V6M
2
2
PC904 22U_0805_6.3V6M
2
PC909 22U_0805_6.3V6M
1 PC913 22U_0805_6.3V6M
2
PC914 22U_0805_6.3V6M
C
C
1
2
1 PC915 22U_0805_6.3V6M
1
2
1 PC920 22U_0805_6.3V6M
1
2
2
1 PC916 22U_0805_6.3V6M
2
1 PC921 22U_0805_6.3V6M
1 PC925 22U_0805_6.3V6M
2
2
1 PC917 22U_0805_6.3V6M
2
1 PC922 22U_0805_6.3V6M
1 PC926 22U_0805_6.3V6M
2
2
1 PC918 @ 22U_0805_6.3V6M
2
2
PC919 @ 22U_0805_6.3V6M
1 PC923 @ 22U_0805_6.3V6M
1 PC927 22U_0805_6.3V6M
2
2
PC924 @ 22U_0805_6.3V6M
1 PC928 22U_0805_6.3V6M
2
PC929 22U_0805_6.3V6M
B
B
A
A
DELL CONFIDENTIAL/PROPRIETARY Compal Electronics, Inc. Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5
4
3
2
PROCESSOR DECOUPLING Size
Document Number
Date:
Friday, May 17, 2013
Rev 0.3
LA-9591P Sheet 1
49
of
58
5
4
3
V ersion Change L ist ( P. I. R . L ist ) Item Page# 1
Title
P45
1.5VSP
D ate 8/17
R equest O w ner Compal
2
1
Page 1
Issue D escription Base power budget request, add 1.5V powre rail
Solution D escription
R ev.
Add PU400
D
D
2
P42
+5V/+3.3V
8/17
Compal
reserver PR114 for TPS51282 application
ADD @PR114
3
P47
Charger
8/17
Compal
EC can't detect charger IC cause can't charger
modify SMBus net for correct connect
4
P46
Vcore
8/17
Compal
schematic control error cause can't set OCP
add Vref net for correct connect
5
P48
Selector
8/17
Compal
in order to meet latest multi-battery request
change control signal for meet E5 request
6
P43
1.35V/0.675V
8/17
Compal
chagne OCP setting
change PR201 from 20k to 24.9k.
7
P42
+5V/+3.3V
10/22
Compal
Reserve 0ohm for 3v5v enable debug
Change PR113 from SD03420018L (S RES 1/16W 2K +-1% 0402) to SD028000080 (S RES 1/16W 0 +-5% 0402)
8
P44
+1.05V_MP
10/22
Compal
+1.05V_MP EA for ripple portion can't meet spec. 31.5mv, after change from 1u to 2.2u test is pass
9
P42
+5V/+3.3V
10/22
Compal
Original 3v5v IC -TPS51225 can't support 2cell battery follow TI suggestion, When TPS51285A/B is used, please update the below four components. 1)VREG5 cap to 4.7uF 2)VREG3 cap to 4.7uF 3)CS1 resistor to 1/5 of the Tps51275’s value 4)CS2 resistor to 1/5 of the Tps51275’s value 5)VCLK connection (when not be used): add 200-ohm to GND
C
X01 C
Change PL300 from SH00000PJ00 (S COIL 1UH +-20% PCMB063T-1R0MS 12A) X01 to SH00000MR00 (S COIL 2.2UH +-20% ETQP3W2R2WFN 8.5A) Change PU100 from SA00005LS00 (S IC TPS51225CRUKR QFN 20P PWM) to SA000064T00 (S IC TPS51285BRUKR QFN 20P PWM)
X01
1)2)Change PC118(VREG5 Cap) and PC100(VREG3 Cap) from SE080105K80(S CER CAP 1U 10V K X5R 0603) to SE00000MA00(S CER CAP 4.7U 10V K X5R 0603) 3) Change PR106(for CS1) from SD03484528L (S RES 1/16W 84.5K +-1% 0402) to SD034169280 (S RES 1/16W 16.9K +-1% 0402) 4) Change PR105(for CS2) from SD03410038L (S RES 1/16W 100K +-1% 0402) to SD034200280 (S RES 1/16W 20K +-1% 0402) 5) Add
B
10
P47 P48
Charger Selector
10/22
Compal
To avoid HW and Power SMT materials can't entirely replace
11
P47
Charger
10/22
Compal
follow E5- Salado 14"15" schematic
12
P46
Vcore
11/02
Compal
follow TI suggestion modify setting value to meet Intel VR12.6(ULV) validation EA 1) Imon 2) Loadline 3) transient
PR114 SD034200080(S RES 1/16W 200 +-1% 0402)
Change PU3,PU801,PU804,PU805,PU806,PU807 from SA74108040L(S IC 74AHC1G08GW SOT353 AND) to SA00708012L(S IC TC7SH08FU SSOP 5P AND)
X01
1) @PQ819, @PQ824 2) EMI request for add PL700 SH00000IW00(S COIL 1UH +-20% PCMB042T-1R0MS 4.5A) 1) Change PR501 from SD034422380 (S RES 1/16W 422K +-1% 0402) to SD034365380 (S RES 1/16W 365K +-1% 0402)
X01
B
X01
2) Change PR521 from SD000009M80 (S RES 1/16W 2.61K +-1% 0402) to SD00000WS8L(S RES 1/16W 2.32K +-1% 0402) 3) @PC506 100p_0402 and change PR535 from SD02810028L(S RES 1/16W 10K +-5% 0402) to SD034487100 (S RES 1/16W 4.87K +-1% 0402 (LF))
A
A
DELL CONFIDENTIAL/PROPRIETARY Compal Electronics, Inc. Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PWR_PIR 1 Size
4
3
2
Rev 0.3
LA-9591P Date:
5
Document Number Friday, May 17, 2013
Sheet 1
50
of
58
5
4
3
V ersion Change L ist ( P. I. R . L ist ) Item Page# 13
Title
P47
Charger
D ate
R equest O w ner
11/05 Compal
D
2
Page 1
Issue D escription 1) TI suggestion BQ24715 cell pin pull high 3.3V change to V_regn(6v) for sequence issue 2) Reserve 0 ohm for debug
14
+5V/+3.3V
P42
11/05
Compal
1
Solution D escription
R ev.
1) Change PR711 from SD02800008L (S RES 1/16W 0 +-5% 0402) to SD034100280 (S RES 1/16W 10K +-1% 0402) ,add PR750 SD028000080(S RES 1/16W 0 +-5% 0402)
X01 D
2) Add @PR751
follow E5- Salado 14"15" schematic
1) @PR863, @PR870, @PR869, @PR824, @PR875, @PQ823
X01
2) Add @PR848, @PR851 and add PR834, PR852, PR853, all is SD028000080(S RES 1/16W 0 +-5% 0402) 3) Add PR874 SD028100480(S RES 1/16W 1M +-5% 0402) 4) Add PD819 SCS0340L01L(S SCH DIO SDMK0340L-7-F SOD-323)
15
P47
Charger
11/05
Compal
16
P47
Charger
11/05
Compal
17
P44
+1.05VTTP
11/05
18
P48
+5V/+3.3V
11/05
Improve charger efficiency
Change PR715 from SD028200A80 (S RES 1/16W 20 +-5% 0402) to SD013220B80 (S RES 1/10W 2.2 +-5% 0603)
follow E5- Salado 14"15" schematic
Delete @PR731, @PR733, @PU702
X01
C
C
1.35V/0.675V +1.05V_MP B
19
P48
Selector
11/15
Compal Support QAD WCEPTA analysis, to modify 1.05 OCP Rtrip -QAD team resistance to 95K, Cpk value will pass specification. -Huang.Hanks (PCP)
Compal - EMC team Wen. Andy
Compal
EMC team suggestion
follow E5- Salado 14"15" schematic for undock shutdown issue
X01
Change PR302 from SD00000H880 (S RES 1/16W 54.9K +-1% 0402) to SD034953280 (S RES 1/16W 95.3K +-1% 0402 )
X01
@PC105, @PC203, @PC301
X01
Add PQ827 SB00000UO00 (S TR DMN65D8LW-7 1N SOT323-3), @PR856 SD028000080 (S RES 1/16W 0 +-5% 0402), PQ816 SB534020000 (S TR AO3402 1N SOT-23), PQ828 SB00000UO00 (S TR DMN65D8LW-7 1N SOT323-3), PR861 SD028000080 (S RES 1/16W 0 +-5% 0402)
X01
B
PR802, PR827, PR840 change from SD028240380 (S RES 1/16W 240K +-5% 0402) to SD028470280 (S RES 1/16W 47K +-5% 0402), PR804, PR826, PR839 change from SD028470280 (S RES 1/16W 47K +-5% 0402), to SD028240380 (S RES 1/16W 240K +-5% 0402)
20
P47
Charger
P48
Selector
P41
+DCIN
Change PR713 from SD034294380 (S RES 1/16W 294K +-1% 0402) to SD034261380 (S RES 1/16W 261K +-1% 0402)
12/12 Compal
A
21
2013 Compal/01/11 ESD team
ESD team's PD1 vendor(NXP) proposal PD1 pin 5 connected to the VCC (5V or 3.3V).
X01
@PR844 PD1 pin5 connect to +3.3V_ALW
A
X01_2
DELL CONFIDENTIAL/PROPRIETARY Compal Electronics, Inc. Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PWR_PIR 2 Size
4
3
2
Rev 0.3
LA-9591P Date:
5
Document Number Friday, May 17, 2013
Sheet 1
51
of
58
5
4
3
V ersion Change L ist ( P. I. R . L ist ) Title
D ate
R equest O w ner
Selector
2013/ 01/23
Compal
Item Page# 22
P48
D
2
1
Page 1
Issue D escription To avoid +DOCK_PWR_BAR leakage voltage when system only with main battery
Solution D escription
R ev.
1). Add PU808 P/N: SA007080120 (S IC TC7SH08FU SSOP 5P AND)
X01_2 D
2). Add PQ830 P/N: SB000007900 (S TR NTR4502PT1G 1P SOT23-3) 3). Add PQ831 P/N: SB00000UO00 (S TR DMN65D8LW-7 1N SOT323-3) 4). Add PD821 P/N: SCS0340L010 (S SCH DIO SDMK0340L-7-F SOD-323) 5). Add PR836, PR837 P/N: SD028100380 (S RES 1/16W 100K +-5% 0402) 6). Add PC814 P/N: SE102104K00 (S CER CAP 0.1U 10V +-10% X7R 0402)
23
P41
+DCIN
C
24
P48
Selector
2013 Compal /02/07
PPM-Jovins_Chang and Sourcer-Willie_Zeng highlight SB000009N8L will shortage after 2013/05
2013/ Compal 02/18
Change PQ6 From : SB000009N8L (S TR IMD2AT-108 PNP/NPN SC74-62) To : SB000009P80 (TR DCX124EK-7-F PNP/NPN SC74R-6)
X02
GPIO net - AC_DIS# is high active. Corrent net name.
1). Change PQ6A.5 and PR828.1 net name from AC_DIS# to AC_DIS
X02
AC_DIS circuit modify to improve output voltage level.
2). Add PQ829 P/N: SB00000H500 , PQ832 P/N: SB00000UO00 , PD820 P/N: SCS0340L010 , @PR894 , PR895 P/N: SD028000080
C
(S TR SI2301CDS-T1-GE3 1P SOT23-3) (S TR DMN65D8LW-7 1N SOT323-3) (S SCH DIO SDMK0340L-7-F SOD-323) (S RES 1/16W 0 +-5% 0402)
3). modify PR828,PR830 4). Delete PQ820 5). Delete PL5, add PJP1
B
25
P41
+DCIN
2013/ Compal-ME 02/18
26
P48
Selector
2013/ Compal 02/18
layout spec limit
P46 P48
Vcore Selector
2013/ Compal02/18 ESD team Hsu. Matt
Add snubber component by ESD team request
27
DFX highlight Battery connetor(locattion:PBATT1) hard to insert.
B
Battery connetor(locattion:PBATT1) footprint follow ME team Iris requesti to change from SUYIN_200277GR009M262ZR_9P-T to ALLTO_C144LS-109A9-L_9P-T
X02
Delete PD817, modify PD815 footprint same as PD701, from SDMK0340L-7-F_SOD323-2 to RB717F_SOT323-3 Add PC508, PC714 P/N:SE025821K80 (S CER CAP 820P 50V K X7R 0603) PR522, PR724 P/N:SD001470B80 (S RES 1/4W 4.7 +-5% 1206 )
X02 X02
A
A
DELL CONFIDENTIAL/PROPRIETARY Compal Electronics, Inc. Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PWR_PIR 3 Size
4
3
2
Rev 0.3
LA-9431P Date:
5
Document Number Friday, May 17, 2013
Sheet 1
52
of
58
5
4
3
V ersion Change L ist ( P. I. R . L ist ) Title
D ate
R equest O w ner
Selector
2013/ 02/21
Compal
Item Page# 28
P48
D
2
1
Page 1
Issue D escription
Solution D escription
follow E5- Salado 14"15" schematic
1). Change PC703 from 0.1U to 1U P/N: SE000006900 (S CER CAP 1UF 25V K X5R 0603)
1) For Input current sense stablilze
2). Change PC706 from 1U to 0.1U P/N: SE00000QK00 (S CER CAP 10U 25V K X5R 0805 H1.25)
2) To provent charger into sleep mode dual AC transient.
3). Change PC708 from 0.01U to 10U P/N: SE00000G880 (S CER CAP 0.1U 25V K X5R 0402)
4) Adapter protect rating setting 5) Fine tune H_PROCHOT# response time. 6) Improve ACAV_IN_NB ref voltage accuracy. 7) Improve current sense accuracy.
C
4). Change PR734 P/N: SD034210380 Change PR735 P/N: SD034698280
Vcore
2013/ Compal02/26 ESD team Hsu. Matt
Add 22U_0805 by ESD team request
from 100K ohm to 210K ohm (S RES 1/16W 210K +-1% 0402) from 46.4K ohm to 69.8K ohm (S RES 1/16W 69.8K +-1% 0402)
5). Add @PC740 6). Change PR738.pin1 from BQ24715_REGN connect to +3.3V_ALW2. Change PR738 from 118K ohm to 48.7K ohm P/N: SD034487280 (S RES 1/16W 48.7K +1% 0402) Change PR744 from 12K ohm to 10K ohm P/N: SD034100280 (S RES 1/16W 10K +-1% 7). Change PR748 P/N: SD034442A80 Change PR749 P/N: SD00000W200
P46
X02 D
3) Fine tune ACOK response time.
29
R ev.
C
from 6.8 ohm to 210K ohm (S RES 1/16W 44.2 +-1% 0402) from 10 ohm to 69.8K ohm (S RES 1/16W 59 +-1% 0402)
X02
Change PC732, PC736 from 10U to 22U from P/N: SE00000QK00 (S CER CAP 10U 25V K X5R 0805 H1.25) to P/N: SE00000XH80 (S CER CAP 22U 25V M X5R 0805 H1.25)
B
B
30
Selector
P48
2013/ Compal 02/27
Modify resistor value to meet voltage tolerence
X02
1). Change PR802,PR827,PR840 from 47K ohm to 100K P/N: SD028100380 (S RES 1/16W 100K +-5% 0402) 2). Change PR804,PR826,PR839 from 240K to 100K P/N: SD028100380 (S RES 1/16W 100K +-5% 0402)
31
P47
Charger
2013/ Compal 03/18
follow E5- Salado 14"15" schematic to add charger input MLCC to 88u
1). Add PC741, PC742 P/N: SE00000XH80 (S CER CAP 22U 25V M X5R 0805 H1.25)
X02_1
2). Due to space limit, so delete @PC701, @PC702, @PC710
A
32
P42 P43 P44
+5V/+3.3V 1.35V/0.675V +1.05V_MP
2013/ Compal 03/20
support DFX team change choke layout pad to avoid soldering issue
1). Change PL101, PL102, PL200, PL300 change from CYNTE_PCMC063T-2R2MN_2P to CYNTE_PCMB064T-3R3MS_2P
33
P46
Vcore
2013/ Compal 03/21
Support acoustic team to reduce noise
3). Change PC738 X02_1 from 33U(SGA00005M00) to 100U P/N: SGA00008R00 (S POLY C 100U 20V M D ESR55M (D3L_H=2.8mm) DELL CONFIDENTIAL/PROPRIETARY
PCB FootPrint
X02_1
Compal Electronics, Inc. Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PWR_PIR 4 Size
4
3
2
Rev 0.3
LA-9431P Date:
5
Document Number Friday, May 17, 2013
Sheet 1
53
of
58
A
5
4
3
2
1
V ersion Change L ist ( P. I. R . L ist ) Item Page# D
1
22,40,38 26,34
2 3 4
Title
D ate
ESD
11/05/2012
27
Safty
37
HW
22,40,38 26
HW
R equest O w ner
A
Solution D escription
R ev.
COMPAL
ESD team request
Remove D3,D27,D22,DE1,DE2 Reserve D20
0.2(X01)
11/05/2012
COMPAL
Safty team request
Pop F2 and reserve R160
0.2(X01)
11/05/2012
COMPAL
Based on align E5,P5 Fan module pin define
Swap JFAN1 pin define
0.2(X01)
11/06/2012
COMPAL
To avoid PT phase occurs ESD issue and change back ESD request
Reserve D3,D27,D22,DE1,DE2
0.2(X01)
5
40 36
HW
11/08/2012
DELL
DELL drop Media LED function
Remove backlight LED function and change connector to 6pin
0.2(X01)
6
26
HW
11/09/2012
COMPAL
Remove EMI solution at Speaker side
Remove R132, R133, R134 and R135
0.2(X01)
7
12,22,37
HW
11/09/2012
DELL
DELL drop ALS function
Remove ALS interface from EC and CPU side than move touch screen signal to eDP side
0.2(X01)
8
22
HW
11/09/2012
COMPAL
change Webcam power enable from PCH
pop R106 and de-pop R102
0.2(X01)
9
10
HW
11/09/2012
COMPAL
Schmatic error and remove eDP backlight control pull up resistor
Remove RC150
0.2(X01)
C
B
Issue D escription
C
10
39
HW
11/12/2012
COMPAL
+1.05V_MODPHY can't meet INTEL timing spec
change +1.05V_MODPHY to MOS solution
0.2(X01)
11
18 19
HW
11/12/2012
COMPAL
Remove DIMM VERF power rail from power side
Remove RD2, RD4, RD8 and RD9
0.2(X01)
12
27
HW
11/12/2012
COMPAL
change miniDP OCP solution
remove D10 R160 F2 and add U50 de-pop C383
0.2(X01)
13
26
HW
11/12/2012
COMPAL
refer salado 14" to change PCBEEP circuit
remove C132,C146,R146,R138,C133 and C143 than add C145,C146,R147,R151 and de-pop R194 R153
0.2(X01)
14
26
HW
11/12/2012
COMPAL
If doesn't has external power, Sleeve will be floating mode and no reference GND.
Add AUD_NB_MUTE# to control Sleeve pin.
0.2(X01)
15
37
HW
11/12/2012
COMPAL
Change board ID to X01
change R392 form 240K to 130Kohm
0.2(X01) 0.2(X01)
COMPAL
Vendor update schematic for power saving
change +1.05V_RUN_VMM power enable signal from LP_EN to DOCKED and add +3.3V_RUN_VMM for DP2320 series 3.3V power rail remove L3 and move U6.E5 to +1.05V_VMM_VDD power rail change U6.J4 to +3.3V_RUN_VDDA R85 change to 3.74K_1% remove LP_EN, R232 and U6A.A5 to NC remove R55 and pop-option R207 when use VMM2310
16
21
HW
11/12/2012
B
17
21
HW
11/12/2012
COMPAL
change VMM2320 config
remove DP to VGA PTN3392 circuit and add 0ohm pop option for 2320 config 0.2(X01)
18
22
HW
11/13/2012
COMPAL
Add Mic power and remove DBC function
Add 3.3V_RUN for Mic power and remove DBC function at JeDP.2
0.2(X01)
19
19
HW
11/13/2012
COMPAL
refer PDG1.0 to change SODIMM control circuit resistor
change RC68, RC126 and RC173 from 2.2 to 2ohm 1% change RC67,RC69,RC130,RC132,RC217 and RC221 from 1.82K to 1.8Kohm 1%
0.2(X01)
20
37,36,12
HW
11/13/2012
COMPAL
GPIO map update to 2.7 version
Move EC_WAKE# from ECE5048[L]5 to MEC5075 GPIO52. Change name: 1.5V_SUS_PWRGD to 1.35V_SUS_PWRGD for DDR3L. Add NFC_DET# ECE5048 GPIOL[5] to NFC moudle & add R38 PU
0.2(X01)
21
20,27,29 ,38,40
ME
11/13/2012
COMPAL
ME change connector
change JmDP1,JNFC1,JMEDIA,JKBTP1,JUSH1
0.2(X01)
22
24
HW
11/14/2012
COMPAL
Vendor update schematic for power saving
align AUX/DDC SW voltage with DP Hub to +3.3V_RUN_VMM
0.2(X01)
DELL CONFIDENTIAL/PROPRIETARY Compal Electronics, Inc. Title PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 5
4
3
D
2
EE P.I.R (1/6) Size
Document Number
Date:
Friday, May 17, 2013
Rev 0.3
LA-9431P Sheet 1
54
of
59
A
5
4
3
2
1
V ersion Change L ist ( P. I. R . L ist ) Item Page# D
23
Title
2,3,6,34
HW
D ate 11/15/2012
R equest O w ner
Issue D escription
COMPAL
update SATA topology fro Mainstream CPU
Solution D escription
R ev.
exchange SATA1&SATA2 topology
0.2(X01)
24
12
HW
11/15/2012
COMPAL
Add LAN_WAKE# T-topology
Pop RC301 to link LAN_WAKE# and EC_WAKE#
0.2(X01)
25
15
HW
11/15/2012
COMPAL
remove RC252 for cost saving
change RC252 to PJP11(1mm jumper-short)
0.2(X01)
26
16
HW
11/15/2012
INTEL
MOW_WW46 request change for VCCUSB3PLL and VCCSATA3PLL
change CC42 and CC49 from 1u_0402 to 22u_0603 change CC76 and CC77 from 100u_1206 to 22u_0603
0.2(X01)
HW
11/15/2012
COMPAL
change AND gate to same source
Change U20, U26, U29 and U30 from SA74108040L to SA00708012L
0.2(X01)
27
20,28,30,31
28
34
ME
11/15/2012
COMPAL
ME change Docking connector
change JDOCK1 that Pin145 from PWR1 to GND1 & Pin148 from PWR2 to GND2
0.2(X01)
29
38,12
HW
11/15/2012
COMPAL
remove +3.3V_TP power load switch solution
remove U40, R458,C424 and C423
0.2(X01) 0.2(X01)
30
22
HW
11/15/2012
COMPAL
change LCDVDD power control circuit
change U9 from TPS22966 to APL3512 solution
31
31,32
HW
11/15/2012
COMPAL
remove TPS22965 solution
remove U51(TPS22965) and U34(TPS22965) than add U3(TPS22966)
0.2(X01)
32
10,27
HW
11/15/2012
COMPAL
ESD solution for black screen issue
Add CC450 on EDP_CPU_HPD to GND and C451 on DPC_HPD to GND
0.2(X01)
33
40
ME
11/16/2012
COMPAL
ME change drawing
Add H18 and H10,H11 change size from 2.3 to 3.4 , H5 change size from 2.8 to 2.3
0.2(X01)
34
22
HW
11/16/2012
COMPAL
change diode to daul-diode fro cost saving
remove D4,D5,D6,D7 and add D10,D21
0.2(X01)
35
40
ME
11/16/2012
COMPAL
ME request
change SW1 to SKRBAAE010
0.2(X01)
36
30
ME
11/16/2012
COMPAL
ME change connector
change SD1
0.2(X01)
37
21,26,28, 31,39
HW
11/16/2012
COMPAL
For EA rework request
Add PJP12~25 for +1.05V_RUN_VMM,+3.3V_RUN_VMM,+3.3V_ALW_PCH,+1.05V_RUN, 0.2(X01) +3.3V_SUS,+3.3V_M,+5V_RUN,+3.3V_RUN,+3.3V_LAN,+3.3V_mSATA_WWAN,+3.3V_HDD ,+3.3V_WLAN,+5V_RUN_AUDIO,+3.3V_RUN_AUDIO
38
37
HW
11/19/2012
COMPAL
change thermal diode for cost saving
change Q11,Q13 and Q14 form SB000008P0L to SB33904510L
0.2(X01) 0.2(X01)
change Bead for cost reduce
change change change change
C
D
C
39
38,26,30,22
HW
11/19/2012
COMPAL
B
L44 L35 LE1 L21
and L45 from SM01000558L to SM01000C500 and L36 from SM01000AM0L to SM01000C500 from SM01000DH0L to SM01000BV00 from SM01001788L to SM010005N00
B
40
9
HW
11/19/2012
COMPAL
change APS pin 11 net_name for DELL APS debug Change JAPS1.11 net name from SIO_PWRBTN# to POWER_SW#_MB change net name from HOST_ALERT1_R_N to PCH_GPIO15, and pop RC190 support TLS confidentility remove R188
0.2(X01)
41
12,28
HW
11/19/2012
COMPAL
42
37
HW
11/19/2012
COMPAL
change thermal OTP to 98 degree
change R394 from 1.24K to 1.82K_1%
0.2(X01)
43
31
HW
11/20/2012
COMPAL
Intel notice remove HDD_DEVSLP function on WWAN JMINI port
remove HDD_DEVSLP from JMINI2.44 de pop HDD_DEVSLP pull up resistor R155
0.2(X01)
44
28
HW
11/20/2012
COMPAL
LOM LED issue
reverse Q32,Q33 of C & D gate
0.2(X01)
45
22
HW
11/20/2012
COMPAL
ME change connector
change JLED1
0.2(X01)
46
35
HW
11/21/2012
COMPAL
Align EMI part
change L54 pat to DLW21SN900SQ2L that same with L42, L39
0.2(X01)
47
15
HW
11/22/2012
COMPAL
Per Intel CRB updated
change VCCST_PWRGD pull high value from 10K ohm to 1K ohm
0.2(X01)
48
26
HW
11/22/2012
COMPAL
Universal Jack no longer supported on X5
Remove D9,D11,R209,R210,C195,C196,R198,R199
0.2(X01)
0.2(X01)
A
A
49
6,12,25,31
HW
11/26/2012
DELL
For support DEVSLP on WWAN JMINI2 & mSATA JMINI3
SATA HDD change from port0 to port1, and connect HDD_DEVSLP Dock change from port1 to port2, and connect mSATA_DEVSLP
0.2(X01)
Compal Electronics, Inc. PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
Title
EE P.I.R (2/6) Size
4
3
2
Rev 0.3
LA-9431P Date:
5
Document Number Friday, May 17, 2013
Sheet 1
55
of
59
5
4
3
2
1
V ersion Change L ist ( P. I. R . L ist ) Item Page# D
Title
D ate
R equest O w ner
Issue D escription
Solution D escription
R ev.
50
21,26
HW
11/26/2012
COMPAL
change Bead for cost reduce
L6 and L7 from SM01000GG0L to BLM15PX471SN1D(SM01000M700) L22, L23, L24 and L25 from SM010028800 to BLM15PX121SN1D(SM01000L300)
0.2(X01)
51
31
HW
11/26/2012
COMPAL
change WWAN power control signal
Change U3.5 from 3.3_1.5V_WLAN_E to SIO_SLP_WLAN#
0.2(X01)
52
12,36
HW
11/27/2012
COMPAL
NFC_DET# change to PCH side GPIO59
UC1.AT5 change from PCH_GPIO59 to NFC_DET# U37.B1 change to NC
0.2(X01)
53
22,26,38,40
HW
11/27/2012
COMPAL
Remove ESD reserve location
Per ESD experiment, D3,D27,D22,DE1,DE2 can be remove
0.2(X01)
54
33
HW
11/27/2012
COMPAL
Per USB2.0 EA result
Change U42 from SM01002080L(DLW21SN900SQ2L) to SM070001600(OCE2012120YZF)0.2(X01)
55
6,12,25,31
HW
11/27/2012
DELL
Per Dell requset, only JMINI3(mSATA ) support DEVSLP
SATA HDD use port0 ,Dock use port1
0.2(X01)
56
31
HW
11/28/2012
COMPAL
change +3.3V_WLAN PWR control
change +3.3V_WLAN PWR control from SIO_SLP_WLAN# to AUX_EN_WOWL
0.2(X01)
57
28
HW
11/28/2012
COMPAL
change +3.3V_mSATA_WWAN control
change +3.3V_mSATA_WWAN control from WWAN_mSATA_EN to MCARD_WWAN_PWREN
0.2(X01)
58
34
HW
11/28/2012
COMPAL
For EMI request, change to 33 ohm for docking DVI noise
R252/R253/R254/R255/R256/R257/R258/R259/R260/ R261/R262/R263/R264/R265/R266/R267 change to 33ohm from 0 ohm
0.2(X01)
59
21
HW
11/28/2012
COMPAL
For use IDT2320, need change EEPROM PN
U7 change from SA00003FL10(W25X10BVSNIG) to SA00006HH00(W25X10CLSNIG)
0.2(X01)
60
22
HW
11/28/2012
COMPAL
change Bead for cost reduce
LE1 change from SM01000DH0L(BLM18BB221SN1D)to SM01000BV00(BLM15BB221SN1D)0.2(X01)
C
D
C
61
6,25,31
HW
11/29/2012
DELL
To support mainstream and Premium CPU, change to SATA port assignment.
SATA HDD change from port0 to port1, and connect HDD_DEVSLP Dock change from port1 to port0, and connect mSATA_DEVSLP
62
12,31,34
HW
11/29/2012
DELL
To support the SATA DevSLP function for new SATA port assignment.
Change DEVSLP0/GPIO33 to mSATA_DEVSLP and DEVSLP1 to HDD_DEVSLP
0.2(X01) 0.2(X01)
63
33
HW
01/10/2013
COMPAL
For USB3.0 EA result
L37 & L38 change to SM070000S80(S COM FI_ CHENG HANN WCM2012F2SF-670T04) 0.3(X02)
64
40
HW
01/10/2013
COMPAL
For ME team force test result
SW1 change to SN111005800(S TACK SW BCL31 SKRBAAE010 SPST)
0.3(X02)
65
9
HW
01/17/2013
COMPAL
For U42 2nd source (MC74VHC1G08DFT2G)can't boot issue
PCH_RSMRST#_R add RC136 10K pull dowm
0.3(X02)
66
28
HW
01/17/2013
COMPAL
For meet INTEL LAN SPEC
Y3 change to SJ10000JC00(S CRYSTAL 25MHZ 18PF +-30PPM 7V25000034)
0.3(X02)
67
22
HW
01/17/2013
COMPAL
For trial run U9 2nd source
U9 pin 4 & pin5 connect to +3.3V_ALW
0.3(X02)
1.change R435 from 1.8k to 150(SD028150080) 2.R430/R438/R436 from 2.2k to 150(SD028150080) 3.R434 change from 220 to 150(SD028150080) 4.R427 change from 1K to 150 ohm(SD028150080) 5.R429 change from 620 to 330 ohm(SD028330080) 6.R431/R433 change from 330 to150 ohm(SD028150080)
0.3(X02)
1. modify JEDP1 pin assignment 2. pin 29 (IO_LOOP) add 1k pull down
0.3(X02)
B
B
68
40
HW
01/17/2013
COMPAL
69
22
HW
01/17/2013
COMPAL
A
For LED light test result
For prevent EDP pin shift then cause broken issue
A
Compal Electronics, Inc. PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
Title
EE P.I.R (3/6) Size
4
3
2
Rev 0.3
LA-9431P Date:
5
Document Number Friday, May 17, 2013
Sheet 1
56
of
59
5
4
3
2
1
V ersion Change L ist ( P. I. R . L ist ) Item Page#
Title
D ate
R equest O w ner
Issue D escription
Solution D escription 1.L22/L23/L24/L25 change to SM010019400 from SM01000L300 2.L51/L52 change to SM01000FV00 from SM01000AM0L 3.Delete L50/L53 & add R491/R492 0 ohm-short
D
D
0.3(X02)
70
25,26
HW
12/05/2012
COMPAL
For Audio Presison result
71
37
HW
12/07/2012
COMPAL
Change Board ID for ST
R392 change to 33K ohm from 130k ohm
0.3(X02)
Change connector tyoe
1. JNFC1 change to 6718K-Y15N-01L 2. JKBTP1 change to 6718K-Y16N-01L 3. JUSH1 change to 6718K-Y20N-00L 4. JUSB3 change to PUBAUE-09FLBS1FF4H0 5.JMEDIA change to 6718K-Y06N-01L 6. SH1 change to 6718K-Y12N-01L
0.3(X02)
72
73
37
HW
02/19/2012
COMPAL
HW
02/21/2012
COMPAL
For OTP issue, & change OTP to 96 degree from 98 degree
C
1. Q11/Q13/Q14 change to SB000008P00(S TR MMBT3904WT1G NPN SC70-3) from SB33904510L(S TR PMST3904 NPN SOT323-3) 2. R394 chagne to SD00000SJ80(S RES 1/16W 1.58K +-1% 0402) from SD034182180(S RES 1/16W 1.82K +-1% 0402)
0.3(X02) C
74
7
HW
02/21/2012
COMPAL
change JTAA1 connector type
JTAA1 change to PANAS_AXK820145WG from ACES_50185-02041-001
0.3(X02)
75
38
HW
02/21/2012
COMPAL
Per EMI Test result
Remove L44 & L45
0.3(X02)
76
38
HW
02/21/2012
COMPAL
Per ESD Test result
Pop C141 & C142 & C143
0.3(X02)
77
9
HW
02/21/2012
COMPAL
add XDP@ for XDP component
change XDP circuit to XDP@
0.3(X02)
78
9
HW
02/21/2012
COMPAL
update XDP circuit for INTEL ITE can't boot remove RC121 and pop RC102
0.3(X02)
HW
02/21/2012
COMPAL
HW
02/21/2012
79
B
R ev.
80
9,11,35
9,11,35
COMPAL
Fixed 2 USB Port use the same OC# signal issue
1.change JUSB3 OC# from USB_OC0# to USB_OC1# 2.change USB_OC1#/3# to USB_OC1#, USB_OC3# and add RC166 for OC1# pull up resistor
Add jumper for clock buffer co-layout
add PJP26, PJP27 and PJP28 beween UC5
0.3(X02)
1.L42 change to SM070003N00(CHILISIN CMM0805-20Y-N)from SM070001600( SUPERWORLD OCE2012120YZF) 2.L37/L38 change to SM070001R00(MURATA DLW21SN670HQ2L) from SM070001E0L(MURATA DLW21SN900HQ2L) 3.L8/L39/L54 change to SM070001N00(MURATA DLW21HN900SQ2L)from SM01002080L(MURATA DLW21SN900SQ2L)
0.3(X02)
81
33
HW
02/21/2013
COMPAL
Per EMI test result
82
33
HW
02/22/2013
COMPAL
Per ESD test result
83
9,12
HW
02/25/2013
COMPAL
For LID & AOAC S3 wake up issue
1. 2. 3. 4.
Pop CC71 & CC72 & CC73 Add C452 & C453 & C454(@) 22uF 0603 size R338 & R349 & R352 change to 10k ohm from 1k ohm Add C455 & C456 & C457 0.1UF
0.3(X02)
B
0.3(X02)
Change Net name to SIO_EXT_SMI# from USB_OC3# and change to PCH_GPIO45 from SIO_EXT_SMI#
0.3(X02)
A
A
Compal Electronics, Inc. PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
Title
EE P.I.R (4/6) Size
4
3
2
Rev 0.3
LA-9431P Date:
5
Document Number Friday, May 17, 2013
Sheet 1
57
of
59
5
4
3
2
1
V ersion Change L ist ( P. I. R . L ist ) Item Page#
Title
D ate
R equest O w ner
Issue D escription
Solution D escription 1. 2. 3. 4.
D
C
R ev.
add CC86~CC90 between clock signal add RC62 for UC5 power rail change RC100 from 0ohm short to 10ohm change UC5 from IDT_5V60034DCG8 to CYPRESS_CY2304SXI-1T
D
84
7
HW
02/25/2013
COMPAL
add RF noise solution at clock buffer
85
23
HW
02/25/2013
COMPAL
refer INTEL MOW to upfate HDMI cost reduce level shifter main link
86
33
HW
02/25/2013
COMPAL
change USB charge solution for SAMSUNG phone change U39 from SA00004VH00 to SA00006L600
0.3(X02)
87
26
HW
COMPAL
for Fixed BIOS fliah HOTSOS issue
change R154 from PCH_AUDIO_EN to RUN_ON
0.3(X02)
88
9
HW
02/28/2013
COMPAL
For ESD request
Add CC149(@) on H_PROCHOT# near CPU side
0.3(X02)
89
9
HW
02/28/2013
COMPAL
Follow INTEL CRB XDP schematic
CC68 change to 0.1uF from 0.01uF
0.3(X02)
90
7
HW
02/28/2013
COMPAL
For RF 24MHz issue
1. remove UC5 CC25,CC57,CC80,CC86~CC90,CC22,RC62,RC100,CC23 2. Change RC65 to 0 ohm-short
0.3(X02)
91
9
HW
02/28/2013
COMPAL
For Touch panel issue
92
7,29
HW
03/01/2013
COMPAL
refer GPIO3.0 to add PCH_TPM_LPC_EN
1. add RC56 for pull up enable signal and add R198 for pop option 2. change R193 form 0hm to 10ohm
93
7
HW
03/12/2013
COMPAL
Base on INTEL EDS SPEC Update Rev 1.5.1
1. 2. 3. 4. 5.
LANCLK_REQ# change to UC1.AD1 from UC1.Y5 MINI1CLK_REQ# change to UC1.T2 from UC1.U2 MINI2CLK_REQ# change to UC1.N1 from UC1.T2 MMICLK_REQ# change to UC1.U5 from UC1.AD1 PCH_TPM_LPC_EN change to UC1.Y5 from UC1.U5
0.4(X02)
1. 2. 3. 4.
CLK_PCIE_LAN change CLKOUT_PCIE port2 CLK_PCIE_MINI2 change CLKOUT_PCIE port3 CLK_PCIE_MMI change CLKOUT_PCIE port4 CLK_PCIE_MINI1 change CLKOUT_PCIE port5
0.4(X02)
94
7
HW
02/27/2013
03/14/2013
COMPAL
change
0.3(X02)
R462~R469 resistor from 680(SD034680080) to 470ohm(SD034470080) 0.3(X02)
1.TOUCH_PANEL_INTR# add RC181(@) PU & RC180 PD
For PCIE CLK & PCIE CLK REQ signal mapping
B
0.3(X02) 0.3(X02)
B
95
30
HW
03/14/2013
COMPAL
For O2 enters into test mode unexpectedly with SD card inserted incompletely issue.
1. SD/MMCCD# add C256(0.1uF) & R493(1M) pull-down to GND 2. C222 change to 1uF(SE000000K80) from 0.1u(SE00000G880)
0.4(X02)
96
21
HW
03/15/2013
COMPAL
For Synaptics vender request
1. Delete VMM2310 co-lay related schematic
0.4(X02)
97
21
HW
03/15/2013
COMPAL
For ESD request
1. Add C458(@) &C459(@) &C460(@) &C461(@) 22uF 0603 size
0.4(X02)
98
7
HW
03/18/2013
COMPAL
For INTEL request
PCIECLK_REQ0# add RC57(10k) pull-high to+3.3V_RUN
0.4(X02)
99
21
HW
03/20/2013
COMPAL
For Synaptics vender request
1. Delete R78/R80/R82 2. add C132
0.4(X02)
100
21
HW
03/20/2013
COMPAL
For ME request
ST2 change to H_2P8 from CLIP_C5P1
0.4(X02)
101
9, 12, 15
HW
03/22/2013
COMPAL
For ESD request
1. H_CPUPWRGD add CC90 100pF(@) to GND 2. H_THERMTRIP# add CC91 100pF(@) to GND 3. H_VCCST_PWRGD add CC22 100pF(@) to GND
A
0.4(X02)
Compal Electronics, Inc. PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
Title
EE P.I.R (5/6) Size
4
3
2
Document Number
Rev 0.3
LA-9431P Date:
5
C
Friday, May 17, 2013
Sheet 1
58
of
59
A
5
4
3
2
1
V ersion Change L ist ( P. I. R . L ist ) Item Page# D
Title
D ate
R equest O w ner
102
9
HW
03/27/2013
COMPAL
103
9
HW
03/27/2013
COMPAL
104
32
HW
04/24/2013
COMPAL
105
9
HW
04/24/2013
106
37
HW
107
40
108
Issue D escription
Solution D escription
For Touch panel issue
R ev.
pop RC181 and depop RC180(@)
0.4(X02)
pop RC97 & RC135
0.4(X02)
For USB S3 wake up issue
U33 power rail change from +3.3V_RUN to +3.3V_SUS
1.0(A00)
COMPAL
For XDP signal should be contact to PCH
change RC97 and RC135 to 0ohm short
1.0(A00)
04/25/2013
COMPAL
Change Board ID for A00
R392 change from33K ohm to 1K ohm
1.0(A00)
HW
04/25/2013
COMPAL
For LED EA
R436 change from150 ohm to 330 ohm;R438 change from 150 ohm to 220 ohm
1.0(A00)
28
HW
04/25/2013
COMPAL
for support Vpro reset pin
depop U20 and add R145
1.0(A00)
109
12
HW
04/25/2013
COMPAL
reserve for support non vpro pop option pin reserve RC292 100 ohm pull down
110
6
HW
05/13/2013
COMPAL
For Crystal EA result & RTC time fail issue
1. CC1 & CC2 change from 18pF to 15pF
1.0(A00)
111
16
HW
05/17/2013
COMPAL
For ESD request
Depop CC71/CC72/CC73
1.0(A00)
For XDP SPEC
D
1.0(A00)
C
C
B
B
A
A
Compal Electronics, Inc. PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
Title
EE P.I.R (6/6) Size
4
3
2
Rev 0.3
LA-9431P Date:
5
Document Number Friday, May 17, 2013
Sheet 1
59
of
59
B
C
D
E
COMPAL CONFIDENTIAL MODEL NAME : VAZ50 PCB NO : LA-9431P (DAA00005Z10) BOM P/N : 4319LL31LXX
1
1
GPIO MAP: 3.0C
Goliad 12"
2
2
Haswell ULT
2013-05-17 3
4
REV : 1.0 (A00) @ : Nopop Component 1@ : M/B 8M SPI ROM Component SPI on MB 2@ : TAA/B 8M SPI ROM EMC@ : EMI & ESD & RF Component Vpro 1@/4@/EMC@/ XDP@ : XDP Component 3@/EMC_3@ CONN@ : Connector Component non-Vpro 1@/EMC@/ 3@ : Delete componet for cost down BOM 3@/EMC_3@ EMC_3@ : Delete EMC component for cost down BOM 4@ : M/B 4M SPI ROM Component non-Vpro 5@ : TAA/B 4M SPI ROM (cost down) 1@/EMC@ 7@ : M/B for 8M SPI(Reverse)
TAA
3
2@/5@/EMC@ 3@/EMC_3@ 2@/5@/EMC@ 3@/EMC_3@ 2@/5@/EMC@/ 4
DELL CONFIDENTIAL/PROPRIETARY Compal Electronics, Inc. PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
MB PCB Part Number
Description
DAA00005Z10
PCB 0VM LA-9431P REV1 M/B 4
A
B
C
D
Title
Cover Sheet Size
Document Number
Date:
Friday, May 17, 2013
Rev 0.3
LA-9431P Sheet E
1
of
59
A
B
C
D
E
Goliad12 Block Diagram
Memory BUS (DDR3L)
DDRIII-DIMM X2
1333/1600MHz
eDP CONN
1
BANK 0, 1, 2, 3, 4 ,5 ,6 ,7
eDP
REV. type
PAGE 22
PAGE 18 19
DP
Mini-DP
1
PAGE 27
USB2.0[3]
Camera PAGE 22
DP
For MB/Dock DP Video Switch IDT VMM2320 VGA
Pericom PI3VDP12412
DP
INTEL HASWELL ULT
DDI2
PAGE 27
PAGE 21
Trough eDP Cable
DOCKED_LIO_EN
SLGC55594A USB2.0[0]
NX3DV221
SW_USB2.0[0] USB POWER SHARE PAGE 33
USB20 Switch PAGE 33
BGA CPU DOCKING PORT 2
HDMI
HDMI CONN PAGE 23
Reduce Level ShifterPAGE 23
USB
PAGE 6~17
Card reader
SD4.0 PAGE 30
O2 Micro OZ777FJ2LN PAGE 30
PCIE4
WLAN+BT/ 60GHz
PAGE 28
PAGE 31
3
USB2.0[2] LAN SWITCH PI3L720
LPC
TDA8034HN
RFID RJ45 PAGE 35
Fingerprint CONN
FP_USB
Full Mini Card mSATA PAGE 25
2
USB3.0/2.0 PAGE 35
32M 4K sector
INT.Speaker HDA Codec ALC3226
PAGE 26
Vol bottom SW
PAGE 26
W25Q32FVSSIQ PAGE 7
Touch Screen Conn
SMSC SIO ECE5048
CPU XDP Port
DAI
PAGE 9
To Docking side
Trough eDP Cable
Automatic Power Switch (APS) PAGE 9
Dig. MIC
PAGE 36
USB2.0[4]
WiFi ON/OFF
PAGE 22
PAGE 35
Trough eDP Cable
PAGE 29 USH board
PAGE 37
IO/B
DC/DC Interface
SMSC KBC MEC5075
FAN CONN
3
PAGE 40
Combo Jack
PAGE 22
USH BCM5882
PAGE 35
PAGE 33
DOCK _USB2.0[5] DOCK_USB3.0[3]
PAGE 20 Near Field Communications con
64M 4K sector
USB2.0[6]
PAGE 28
Transformer
W25Q64FVSSIQ
PAGE 29
SATA2
Smart Card
PAGE 33
USB3.0/2.0
HD Audio I/F SATA0 USB2.0[7]
Discrete TPM AT97SC3204
PAGE 31
USB3.0/2.0+PS
IO/B
PCIE6_L0
Full Mini Card WWAN+mSATA
SW_USB2.0[5] SW_USB3.0[3]
USB3.0[1]
SPI
PCIE3
USB3.0[2]
USB2.0[1]
PCIE5_L0
PCI Express BUS
Intel Clarkville I218LM
DOCK _USB2.0[0]
USB2.0[5] PI3USB3102 USB3&2 Switch USB3.0[3] PAGE 32
PAGE 34
DAI DOCK_USB3.0[3] SATA1 DOCK_USB2.0[0] DOCK_USB2.0[5]
DOCKED
DDI1
BC BUS
PAGE 39
PAGE 37
Power On/Off SW & LED PAGE 40
4
KB and TP CONN PAGE 38
4
DELL CONFIDENTIAL/PROPRIETARY Compal Electronics, Inc. Title
Block Diagram Size
Document Number
Rev 0.3
LA-9431P Date: A
B
C
D
Friday, May 17, 2013
Sheet E
2
of
59
5
4
3
2
1
POWER STATES Signal
SLP S3#
SLP S4#
SLP S5#
SLP A#
M PLANE
SUS PLANE
RUN PLANE
S0 (Full ON) / M0
HIGH
HIGH
HIGH
HIGH
ON
ON
ON
ON
ON
S3 (Suspend to RAM) / M3
LOW
HIGH
HIGH
HIGH
ON
ON
ON
OFF
OFF
S4 (Suspend to DISK) / M3
LOW
LOW
HIGH
HIGH
ON
ON
OFF
OFF
OFF
S5 (SOFT OFF) / M3
LOW
LOW
LOW
HIGH
ON
ON
OFF
OFF
OFF
S3 (Suspend to RAM) / M-OFF
LOW
HIGH
HIGH
LOW
ON
OFF
ON
OFF
OFF
S4 (Suspend to DISK) / M-OFF
LOW
LOW
HIGH
LOW
ON
OFF
OFF
OFF
OFF
S5 (SOFT OFF) / M-OFF
LOW
LOW
LOW
LOW
ON
OFF
OFF
OFF
OFF
State
D
ALWAYS PLANE
CLOCKS
USB3.0
PCIE
power plane
+5V_ALW
+3.3V_SUS
+5V_RUN
+3.3V_M
+3.3V_M
+3.3V_ALW
+1.35V_MEM
+3.3V_RUN
+1.05V_M
+1.05V_M
+3.3V_ALW_PCH
+0.675V_DDR_VTT
+3.3V_RTC_LDO
+1.05V_RUN
DESTINATION
USB3.0 1
JUSB3-->Right
USB3.0 2
JUSB1-->Rear left
USB3.0 3
JUSB2-->Rear Right//DOCK
D
PCIE 1 PCIE 2 PCIE 3
LOM
PCIE 4
WLAN (WiGi)
PCIE 5
MMI (CARD READER)
PCIE 6
PM TABLE C
SATA
SATA 3
WWAN(PP/mSATA)
SATA 2
NA
SATA 1
mSATA
SATA 0
DOCK
C
(M-OFF)
+VCC_CORE
USB PORT# State
B
S0
ON
ON
ON
ON
ON
S3
ON
ON
OFF
ON
OFF
S5 S4/AC
ON
OFF
OFF
ON
OFF
S5 S4/AC don't exist
OFF
OFF
OFF
OFF
OFF
HSW ULT
need to update Power Status and PM Table
DESTINATION
0
JUSB1 // E-Dock 1
1
JUSB3
2
WLAN + BT
3
CAMERA
4
USH->SMART CARD
5
JUSB2 // E-Dock 2
6
WWAN
7
TOUCH
B
USH
0
BIO
1
NA
A
A
DELL CONFIDENTIAL/PROPRIETARY Compal Electronics, Inc. PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
Title
Index and Config. Size
4
3
2
Rev 0.3
LA-9431P Date:
5
Document Number Friday, May 17, 2013
Sheet 1
3
of
59
4
3
+3.3V_RUN
D
ADAPTER
1
PWRSHARE_EN# ESATA_USB_PWR_EN#
TPS51212 (PU300)
DOCKED
+1.05V_RUN
2
A_ON
5
G547I2P81U (U35)
USB_SIDE_EN#
G547I2P81U (U32)
G547I2P81U (U52) D
+1.05V_M
TPS22966 (U31)
+5V_USB_ CHG_PWR
+USB_PWR
+USB_SIDE_PWR
MPHYP_PWR_EN
+1.05V_MODPHY
ALWON C
+1.35V_MEM
0.675V_DDR_VTT_ON
+VCC_CORE
C
+5V_ALW
RUN_ON
TPS22966 (U3)
ENVDD_PCH
TPS22966 (U22)
AUX_EN_WOWL
TPS22966 (U22)
3.3V_HDD_EN
SIO_SLP_LAN#
+3.3V_ALW
MCARD_WWAN_PWREN
SUS_ON
TPS22966 (U45)
TPS51285BRUKR (PU100)
APL3512A (U9)
TPS22966 (U46)
TPS22966 (U43)
TPS22966 (U18) B
SUS_ON
B
RT8207 (PU11)
H_VR_EN
TPS51622 (PU500)
A_ON
CHARGER
RUN_ON
+BL_PWR_SRC
PCH_ALW_ON
FDC654P (Q2)
RUN_ON
EN_INVPWR
+3.3V_RUN_VMM
RUN_ON
+1.05V_RUN_VMM
+PWR_SRC
RUN_ON
BATTERY
SI3456DDV (Q125)
+3.3V_ALW_PCH
+5V_RUN _AUDIO +3.3V_M
+3.3V_WLAN
+3.3V_LAN
+3.3V_mSATA_WWAN
+3.3V_HDD
+LCDVDD
3.3V_TS_EN
+3.3V_SUS
3.3V_CAM_EN
+3.3V_RUN
+0.675V_DDR_VTT
+3.3V_RUN _AUDIO
+5V_RUN
+1.05V_RUN
LP2301ALT1G (Q1)
+3.3V_TSP
A
A
+3.3V_CAM
LP2301ALT1G (Q3)
DELL CONFIDENTIAL/PROPRIETARY Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
Title
Power Rail Size
4
3
2
Rev 0.3
LA-9431P Date:
5
Document Number Friday, May 17, 2013
Sheet 1
4
of
59
5
4
3
2
1
2.2K
SMBUS Address [0x9a]
+3.3V_ALW_PCH
2.2K AP2
MEM_SMBCLK
AH1
MEM_SMBDATA
202
2N7002
DIMMA
200
2N7002 1K
PCH D
202
+3.3V_ALW_PCH
1K AN1 AH3
AK1
AU3
SML1_SMBCLK
3A
0ohm
LAN_SMBCLK
28
SML0DATA
0ohm
LAN_SMBDATA
31
LOM
2.2K
+3.3V_ALW_PCH 2.2K
3A
2.2K B4
DOCK_SMB_CLK
A3
DOCK_SMB_DAT
1A
XDP
51
2.2K
B6
1A
D
53
SML1_SMBDATA
A5
DIMMB
200
SML0CLK
0ohm depop
NFC_SMBCLK
0ohm depop
NFC_SMBDATA
NFC
+3.3V_ALW 127 129
DOCKING 30
2.2K C
2.2K 1B
B5
LCD_SMBCLK
A4
LCD_SMBDAT
WWAN
32
+3.3V_ALW
C
1B
2.2K
KBC
2.2K 1C 1C
A56 B59
PBAT_SMBCLK PBAT_SMBDAT
+3.3V_ALW 100 ohm
7
100 ohm
6
BATTERY CONN
2.2K
2.2K A50 1E B53 1E
+3.3V_SUS M9
USH_SMBCLK
L9
USH_SMBDAT
B
USH B
2.2K
2.2K
MEC 5075 2B
A49
CARD_SMBCLK
2B
B52
CARD_SMBDAT
+3.3V_ALW
10K
+3.3V_ALW
10K B50 1G A47 1G
9
CHARGER_SMBCLK
8
CHARGER_SMBDAT
Charger
2.2K 2.2K 2D A
2D
B7 A7
+3.3V_ALW
BAY_SMBDAT BAY_SMBCLK
A
2.2K 2.2K 2A
B7
+3.3V_ALW
Compal Electronics, Inc.
GPU_SMBDAT Title
2A
A7
SMBUS TOPOLOGY
GPU_SMBCLK Size
Document Number
Rev 0.3
LA-9431P Date: 5
4
3
2
Friday, May 17, 2013
Sheet 1
5
of
59
5
4
3
2
1
2
RC1 330K_0402_1%
1
+RTC_CELL
D
+3.3V_ALW_PCH
1
2
@ RC3
INTVRMEN - INTEGRATED SUS 1.05V VRM ENABLE High - Enable Internal VRs Low - Enable External VRs
PCH_AZ_SDOUT 1K_0402_5%
FLASH DESCRIPTOR SECURITY OVERRIDE LOW = ENABLE (DEFAULT) HIGH = DISABLE
2
PCH_RTCX1_R 1 @ RC4
2 0_0402_5%
PCH_RTCX1
2
YC1
CC2 1
1 RC7 +RTC_CELL
CMOS setting
CMOS_CLR1 Shunt
Clear CMOS
Open
Keep CMOS
ME_CLR1
RC8 RC6
1 1
215P_0402_50V8J
1
2
@ ME1
TPM setting
Shunt
Clear ME RTC Registers
Open
Keep ME RTC Registers
1 CC3
2
SHORT PADS~D 2 1U_0402_6.3V6K
1
1
2
HASWELL_MCP_E
UC1E
C
PCH_RTCX2 INTRUDER# PCH_INTVRMEN SRTCRST# PCH_RTCRST#
2 1M_0402_5% 2 220K_0402_5% 20K_0402_5% <9>
1
2
32.768KHZ_12.5PF_Q13FC135000040
C
RC5 10M_0402_5%
15P_0402_50V8J
1
CC1 1
1
2
D
@ RC2 330K_0402_1%
1
PCH_INTVRMEN
AW5 AY5 AU6 AV7 AV6 AU7
RTCX1 RTCX2 INTRUDER INTVRMEN SRTCRST RTCRST
SATA_RN0/PERN6_L3 SATA_RP0/PERP6_L3 SATA_TN0/PETN6_L3 SATA_TP0/PETP6_L3
RTC
PCH_RTCRST#
@ CMOS1 SHORT PADS~D 1 2 1U_0402_6.3V6K
CMOS place near DIMM
<26> <36>
PCH_AZ_CODEC_SDIN0 ME_FWP
1 RC9
AW8 PCH_AZ_BITCLK AV11 PCH_AZ_SYNC AU8 PCH_AZ_RST# PCH_AZ_CODEC_SDIN0 AY10 AU12 2 PCH_AZ_SDOUT AU11 AW10 1K_0402_5% AV10 AY8
HDA_BCLK/I2S0_SCLK HDA_SYNC/I2S0_SFRM HDA_RST/I2S_MCLK HDA_SDI0/I2S0_RXD HDA_SDI1/I2S1_RXD HDA_SDO/I2S0_TXD HDA_DOCK_EN/I2S1_TXD HDA_DOCK_RST/I2S1_SFRM I2S1_SCLK
AUDIO
SATA
SATA_PRX_DKTX_N0_C SATA_PRX_DKTX_P0_C SATA_PTX_DKRX_N0_C SATA_PTX_DKRX_P0_C
J8 H8 A17 B17
SATA_RN1/PERN6_L2 SATA_RP1/PERP6_L2 SATA_TN1/PETN6_L2 SATA_TP1/PETP6_L2
2
CC4
J5 H5 B15 A15
SATA_PRX_DTX_N1_C SATA_PRX_DTX_P1_C SATA_PTX_DRX_N1_C SATA_PTX_DRX_P1_C
<34> <34> <34> <34>
DOCK
<25> <25> <25> <25>
SATA HDD (for Goliad 12 to MSATA)
J6 H6 B14 C15
SATA_RN2/PERN6_L1 SATA_RP2/PERP6_L1 SATA_TN2/PETN6_L1 SATA_TP2/PETP6_L1
F5 E5 C17 D17
SATA_RN3/PERN6_L0 SATA_RP3/PERP6_L0 SATA_TN3/PETN6_L0 SATA_TP3/PETP6_L0
SATA_PRX_mSATATX_N3 SATA_PRX_mSATATX_P3 SATA_PTX_mSATARX_N3 SATA_PTX_mSATARX_P3
<31> <31> <31> <31>
mSATA HDD(for WWAN card)
PCH Rx side need use strap pin to update PCIE +/-
1
RC16 0_0603_5%
<9> <9> <9> <9> <9>
2
@
B
+1.05V_M_JTAG2 RC17
<9>
1 PCH_JTAG_TDI 51_0402_1%
2
1 PCH_JTAG_TDO 51_0402_1%
2
1 PCH_JTAG_TMS 51_0402_1%
2
1 PCH_JTAG_JTAGX 1K_0402_1%
2
1 PCH_JTAG_TCK 51_0402_1%
RC18
PCH_JTAG_TRST# PCH_JTAG_TCK PCH_JTAG_TDI PCH_JTAG_TDO PCH_JTAG_TMS @ T3 @ T4 PCH_JTAG_JTAGX @ T5
PCH_JTAG_TRST# PCH_JTAG_TCK PCH_JTAG_TDI PCH_JTAG_TDO PCH_JTAG_TMS PAD~D PAD~D PCH_JTAG_JTAGX PAD~D
AU62 AE62 AD61 AE61 AD62 AL11 AC4 AE63 AV2
PCH_TRST PCH_TCK PCH_TDI PCH_TDO PCH_TMS RSVD RSVD JTAGX RSVD
A12 L11 K10 C12 U3
SATA_IREF RSVD RSVD SATA_RCOMP SATALED
JTAG
2 SATA_IREF @ RC14 SATA_COMP SATA_ACT#
MPCIE_RST# <31,7> HDD_DET# <25> PCH_GPIO36 <10> mCARD_PCIE_SATA#
+3.3V_RUN
<36>
1 +PCH_ASATA3PLL 0_0402_5% PAD~D T1 @ PAD~D T2 @ SATA_ACT#
1 HDD_DET# 100K_0402_5% mCARD_PCIE_SATA# 1 10K_0402_5%
<40>
SATA Impedance Compensation Rev1p2
+PCH_ASATA3PLL
1
SATA_COMP @ RC10
@ RC22
2 RC11 2 RC12
B
5 OF 19 RC20
V1 MPCIE_RST# U1 HDD_DET# V6 PCH_GPIO36 AC1 mCARD_PCIE_SATA#
SATA0GP/GPIO34 SATA1GP/GPIO35 SATA2GP/GPIO36 SATA3GP/GPIO37
+1.05V_M
2 3.01K_0402_1%
RC19
CAD note: Place the resistor within 500 mils of the PCH. Avoid routing next to clock pins. reference FFRD sch 0.5
reference 479493 figure 7-1
HDA for Codec <26> <26> <26> <26>
PCH_AZ_CODEC_SDOUT
1
2
1
2
PCH_AZ_SDOUT 33_0402_5% PCH_AZ_SYNC 33_0402_5% 2 PCH_AZ_RST# 33_0402_5% 2 PCH_AZ_BITCLK 33_0402_5%
RC23
PCH_AZ_CODEC_SYNC
RC24
1
PCH_AZ_CODEC_RST#
RC25
1
PCH_AZ_CODEC_BITCLK 27P_0402_50V8J @ CC5
A
RC26 EMC@
1 A
2
EMI depop location
DELL CONFIDENTIAL/PROPRIETARY PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 5
4
3
2
Compal Electronics, Inc. Title
MCP(1/12) Size
Document Number
Date:
Friday, May 17, 2013
Rev 0.3
LA-9431P Sheet 1
6
of
59
5
4
3
2
1
+3.3V_RUN HASWELL_MCP_E
1 R2
AF2 AD2 AF4
PCH_CL_CLK1 PCH_CL_DATA1 PCH_CL_RST1#
<11>
SML0CLK SML0DATA PCH_GPIO73 SML1_SMBCLK SML1_SMBDATA
SML1_SMBCLK <37> SML1_SMBDATA <37> PCH_CL_CLK1 PCH_CL_DATA1 PCH_CL_RST1#
2
1
2
1
@ RC29
2
1
2
1
+3.3V_M
U1
<36>
2
SPI_WP#_SEL @ R8
SPI_WP#_SEL
1 2 3 4
SPI_PCH_CS0#_R SPI_DIN64 SPI_PCH_DO2_64
1 R122 1 R123
1 0_0402_5%
1@
/CS VCC DO(IO1) /HOLD(IO3) /WP(IO2) CLK GND DI(IO0) W25Q64FVSSIQ_SO8
8 7 6 5
SPI_PCH_DO3_64 1@ R5 1 SPI_CLK64 1@ R7 1 1@ R9 1 SPI_DO64
2 33_0402_5% 2 33_0402_5% 2 33_0402_5%
2 DDR_XDP_WAN_SMBDAT 10K_0402_5% 2 DDR_XDP_WAN_SMBCLK 10K_0402_5%
+3.3V_M
200 MIL SO8
4@ C6 1 2
32Mb Flash ROM reference PDG0.7
0.1U_0402_25V6 U2
PCH_SPI_CS1# 4@ R14 1 PCH_SPI_DIN 4@ R15 1 PCH_SPI_DO2 4@ R19 1
2
SPI_WP#_SEL @R23 @ R23
2 0_0402_5% 2 33_0402_5% 2 33_0402_5%
SPI_PCH_CS1#_R SPI_DIN32 SPI_PCH_DO2_32
1 0_0402_5%
1 2 3 4
PCH_SPI_DO PCH_SPI_DO
2@ 5@
R11 R12
1 1
2 33_0402_5% 2 33_0402_5%
PCH_SPI_CLK PCH_SPI_CLK PCH_SPI_CS0# PCH_SPI_CS1#
2@ 5@ 2@ 5@
R13 R18 R10 R17
1 1 1 1
2 2 2 2
PCH_SPI_DIN PCH_SPI_DIN
2@ 5@
R22 R41
1 1
2 33_0402_5% 2 33_0402_5%
1 3 5 7 TAA_CLK64 9 TAA_CLK32 TAA_CS0#_R 11 TAA_CS1#_R 13 15 17 TAA_DIN64 19 TAA_DIN32 TAA_DO64 TAA_DO32
33_0402_5% 33_0402_5% 0_0402_5% 0_0402_5%
4@
/CS DO/IO1 /WP/IO2 GND
VCC /HOLD/IO3 CLK DI/IO0
8 7 6 5
SPI_PCH_DO3_32 4@ R16 1 4@ R20 1 SPI_CLK32 SPI_DO32 4@ R21 1
2 33_0402_5% 2 33_0402_5% 2 33_0402_5%
21 23
PCH_SPI_DO3 PCH_SPI_CLK PCH_SPI_DO
1 3 5 7 9 11 13 15 17 19
2 4 6 8 10 12 14 16 18 20
G G
G G
10/100/1G LAN --->
<28> <28> <10,28>
WLAN (Mini Card 2)--->
<31> <31> <31>
MMI---> +3.3V_RUN
WWAN (Mini Card 1)---> 8 7 6 5
DGPU_PWROK MINI2CLK_REQ# MINI1CLK_REQ# MPCIE_RST#
DGPU_PWROK MPCIE_RST#
1
2
1
2
2
1
2
1
RC30
RC34 RC36 RC37 RC38 RC39
22 24
R43 R48 R58 R59
1 1 1 1
2 2 2 2
33_0402_5% 33_0402_5% 33_0402_5% 33_0402_5%
PCH_SPI_DO3 PCH_SPI_DO3 PCH_SPI_DO2 PCH_SPI_DO2
C
XB use 50185-02041-001
2 XTAL24_IN_R 0_0402_5%
<30> <30> <30> <31> <31> <31>
PCH_TPM_LPC_EN +3.3V_RUN CLK_PCIE_LAN# CLK_PCIE_LAN LANCLK_REQ#
1 RC57
PCIECLK_REQ0# 10K_0402_5%
B41 A41 Y5 RC56
1
2 10K_0402_5% CLK_PCIE_LAN# CLK_PCIE_LAN LANCLK_REQ#
C41 B42 AD1 B38 C37 N1
CLK_PCIE_MINI2# CLK_PCIE_MINI2 MINI2CLK_REQ#
CLK_PCIE_MINI2# CLK_PCIE_MINI2 MINI2CLK_REQ# CLK_PCIE_MMI# CLK_PCIE_MMI MMICLK_REQ# +3.3V_RUN CLK_PCIE_MINI1# CLK_PCIE_MINI1 MINI1CLK_REQ#
2
RC55
1
A39 B39 U5
CLK_PCIE_MMI# CLK_PCIE_MMI MMICLK_REQ# 2 10K_0402_5% CLK_PCIE_MINI1# CLK_PCIE_MINI1 MINI1CLK_REQ#
B37 A37 T2
CLKOUT_PCIE_N0 CLKOUT_PCIE_P0 PCIECLKRQ0/GPIO18
XTAL24_IN XTAL24_OUT RSVD RSVD DIFFCLK_BIASREF
CLKOUT_PCIE_N1 CLKOUT_PCIE_P1 PCIECLKRQ1/GPIO19 CLOCK
CLKOUT_PCIE_N2 CLKOUT_PCIE_P2 PCIECLKRQ2/GPIO20
SIGNALS
CLKOUT_PCIE_N3 CLKOUT_PCIE_P3 PCIECLKRQ3/GPIO21
TESTLOW_C35 TESTLOW_C34 TESTLOW_AK8 TESTLOW_AL8 CLKOUT_LPC_0 CLKOUT_LPC_1 CLKOUT_ITPXDP_N CLKOUT_ITPXDP_P
CLKOUT_PCIE_N4 CLKOUT_PCIE_P4 PCIECLKRQ4/GPIO22
A25 B25
2
3 4 YC2 24MHZ_12PF_X3G024000DC1H
XTAL24_IN XTAL24_OUT
K21 M21 C26
CLK_BIASREF
C35 C34 AK8 AL8
MCP_TESTLOW1 MCP_TESTLOW2 MCP_TESTLOW3 MCP_TESTLOW4
AN15 AP15
PCI_CLK_LPC_0 PCI_CLK_LPC_1
CC7 1
18P_0402_50V8J
1 2
2 <29>
ADD EMI solution(EMC)
1 2 3 4
1
TAA Config 2@ 5@ 2@ 5@
TAA_DO3_64 TAA_DO3_32 TAA_DO2_64 TAA_DO2_32
1
2
2 1
C43 C42 U2
1
+3.3V_RUN
RP4
2
+3.3V_M
2 4 6 8 10 12 14 16 18 20
RC44 1M_0402_5%
1
HASWELL_MCP_E
UC1F
@ C76 0.1U_0402_25V6
2
PCH_GPIO73 10K_0402_5% SML1_SMBCLK 2.2K_0402_5% SML1_SMBDATA 2.2K_0402_5% SML0CLK 1K_0402_5% SML0DATA 1K_0402_5%
RC28
W25Q32FVSSIQ_SO8
@ R57 33_0402_5%
B
@ C85 0.1U_0402_25V6
1
1
ACES_50185-02041-001
SPI_CLK64
@ R45 33_0402_5%
2
1
2
Intel PDG 0.9
1 @ RC40 SPI_CLK32
2
PCH_SPI_DO3 PCH_SPI_CLK PCH_SPI_DO CONN@ JTAA1
C
<20>
+3.3V_RUN 1@ C5 1 2
MEM_SMBCLK 2.2K_0402_5% MEM_SMBDATA 2.2K_0402_5%
D
<20>
NFC_SMBDATA
0_0402_5%
0.1U_0402_25V6
2 0_0402_5% 2 33_0402_5% 2 33_0402_5%
<18,19,31,9> +3.3V_ALW_PCH
<28>
NFC_SMBCLK
0_0402_5%
@ RC35
PCH_SPI_CS0# 1@ R3 1 PCH_SPI_DIN 1@ R4 1 PCH_SPI_DO2 1@ R6 1
<18,19,31,9>
DDR_XDP_WAN_SMBDAT
<28>
LAN_SMBDATA
0_0402_5%
@ RC33
Rev1p2
200 MIL SO8
4
LAN_SMBCLK
0_0402_5%
@ RC31
reference PDG0.7
DDR_XDP_WAN_SMBCLK
QC1A DMN66D0LDW-7_SOT363-6
SML0DATA
64Mb Flash ROM
1
QC1B DMN66D0LDW-7_SOT363-6
3
MEM_SMBDATA
<31> <31> <31>
SML0CLK
7 OF 19
6
MEM_SMBCLK
S
R1
CL_CLK CL_DATA CL_RST
C-LINK
PCH_SMB_ALERT#
D
PCH_SPI_DO PCH_SPI_DIN PCH_SPI_DO2 PCH_SPI_DO3
2 PCH_SPI_DO2 1K_0402_5% 2 PCH_SPI_DO3 1K_0402_5% reference PDG0.7
SPI
PCH_SMB_ALERT# MEM_SMBCLK MEM_SMBDATA
S
1
SPI_CLK SPI_CS0 SPI_CS1 SPI_CS2 SPI_MOSI SPI_MISO SPI_IO2 SPI_IO3
AN2 AP2 AH1 AL2 AN1 AK1 AU4 AU3 AH3
D
+3.3V_M
SMBALERT/GPIO11 SMBCLK SMBDATA SML0ALERT/GPIO60 SMBUS SML0CLK SML0DATA SML1ALERT/PCHHOT/GPIO73 SML1CLK/GPIO75 SML1DATA/GPIO74
LPC
G
AA3 Y7 Y4 AC2 AA2 AA4 Y6 AF1
PCH_SPI_CLK PCH_SPI_CS0# PCH_SPI_CS1#
D
LAD0 LAD1 LAD2 LAD3 LFRAME
2
AU14 AW12 AY12 AW11 AV12
LPC_LAD0 LPC_LAD1 LPC_LAD2 LPC_LAD3 LPC_LFRAME#
LPC_LAD0 LPC_LAD1 LPC_LAD2 LPC_LAD3 LPC_LFRAME#
G
<25,29,36,37> <25,29,36,37> <25,29,36,37> <25,29,36,37> <25,29,36,37>
5
UC1G
2 PAD~D T6 PAD~D T7
CC6 1
18P_0402_50V8J
@ @
B
0_0402_5% 22_0402_5% 22_0402_5%
1 1 1
2 RC65 @ PCI_CLK_LPC 2 RC64 EMC_3@ 2 RC66 EMC@
B35 A35
CLK_PCI_DOCK <34> CLK_PCI_LPDEBUG <25>
CLKOUT_PCIE_N5 CLKOUT_PCIE_P5 PCIECLKRQ5/GPIO23
<10>
6 OF 19
Rev1p2
<31,6>
10K_8P4R_5% +PCH_VCCACLKPLL
PCI_CLK_LPC_0 12P_0402_50V8J
2
1 @CC15 @ CC15 PCI_CLK_LPC
PCI_CLK_LPC_1 12P_0402_50V8J
2
1 @CC14 @ CC14
EMC@ RC58 1
2 22_0402_5%
EMC@ RC61 1
2 22_0402_5%
EMC@ RC63 1
2 22_0402_5%
CLK_PCI_TPM_TCM <36>
CLK_PCI_MEC
<37>
2
1
2
1
2
1
2
1
2
MCP_TESTLOW1 10K_0402_5% MCP_TESTLOW2 10K_0402_5% MCP_TESTLOW3 10K_0402_5% MCP_TESTLOW4 10K_0402_5%
<29>
CLK_PCI_5048
1 CLK_BIASREF 3.01K_0402_1%
A
RC45 RC46 RC47 RC50 RC52
A
DELL CONFIDENTIAL/PROPRIETARY PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
For RF request(EMC) Every pin need one gnd by itself 5
4
3
2
Compal Electronics, Inc. Title
MCP(2/12) Size
Document Number
Date:
Friday, May 17, 2013
LA-9431P Sheet 1
Rev 0.3 7
of
59
5
4
D
UC1C <18>
DDR_A_D[0..63]
DDR_A_D0 DDR_A_D1 DDR_A_D2 DDR_A_D3 DDR_A_D4 DDR_A_D5 DDR_A_D6 DDR_A_D7 DDR_A_D8 DDR_A_D9 DDR_A_D10 DDR_A_D11 DDR_A_D12 DDR_A_D13 DDR_A_D14 DDR_A_D15 DDR_A_D16 DDR_A_D17 DDR_A_D18 DDR_A_D19 DDR_A_D20 DDR_A_D21 DDR_A_D22 DDR_A_D23 DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 DDR_A_D28 DDR_A_D29 DDR_A_D30 DDR_A_D31 DDR_A_D32 DDR_A_D33 DDR_A_D34 DDR_A_D35 DDR_A_D36 DDR_A_D37 DDR_A_D38 DDR_A_D39 DDR_A_D40 DDR_A_D41 DDR_A_D42 DDR_A_D43 DDR_A_D44 DDR_A_D45 DDR_A_D46 DDR_A_D47 DDR_A_D48 DDR_A_D49 DDR_A_D50 DDR_A_D51 DDR_A_D52 DDR_A_D53 DDR_A_D54 DDR_A_D55 DDR_A_D56 DDR_A_D57 DDR_A_D58 DDR_A_D59 DDR_A_D60 DDR_A_D61 DDR_A_D62 DDR_A_D63
C
B
AH63 AH62 AK63 AK62 AH61 AH60 AK61 AK60 AM63 AM62 AP63 AP62 AM61 AM60 AP61 AP60 AP58 AR58 AM57 AK57 AL58 AK58 AR57 AN57 AP55 AR55 AM54 AK54 AL55 AK55 AR54 AN54 AY58 AW58 AY56 AW56 AV58 AU58 AV56 AU56 AY54 AW54 AY52 AW52 AV54 AU54 AV52 AU52 AK40 AK42 AM43 AM45 AK45 AK43 AM40 AM42 AM46 AK46 AM49 AK49 AM48 AK48 AM51 AK51
SA_DQ0 SA_DQ1 SA_DQ2 SA_DQ3 SA_DQ4 SA_DQ5 SA_DQ6 SA_DQ7 SA_DQ8 SA_DQ9 SA_DQ10 SA_DQ11 SA_DQ12 SA_DQ13 SA_DQ14 SA_DQ15 SA_DQ16 SA_DQ17 SA_DQ18 SA_DQ19 SA_DQ20 SA_DQ21 SA_DQ22 SA_DQ23 SA_DQ24 SA_DQ25 SA_DQ26 SA_DQ27 SA_DQ28 SA_DQ29 SA_DQ30 SA_DQ31 SA_DQ32 SA_DQ33 SA_DQ34 SA_DQ35 SA_DQ36 SA_DQ37 SA_DQ38 SA_DQ39 SA_DQ40 SA_DQ41 SA_DQ42 SA_DQ43 SA_DQ44 SA_DQ45 SA_DQ46 SA_DQ47 SA_DQ48 SA_DQ49 SA_DQ50 SA_DQ51 SA_DQ52 SA_DQ53 SA_DQ54 SA_DQ55 SA_DQ56 SA_DQ57 SA_DQ58 SA_DQ59 SA_DQ60 SA_DQ61 SA_DQ62 SA_DQ63
3
2
HASWELL_MCP_E
<19>
SA_CLK#0 SA_CLK0 SA_CLK#1 SA_CLK1 SA_CKE0 SA_CKE1 SA_CKE2 SA_CKE3 SA_CS#0 SA_CS#1 SA_ODT0 SA_RAS SA_WE SA_CAS SA_BA0 SA_BA1 SA_BA2 SA_MA0 SA_MA1 SA_MA2 SA_MA3 SA_MA4 SA_MA5 SA_MA6 SA_MA7 SA_MA8 SA_MA9 SA_MA10 SA_MA11 SA_MA12 SA_MA13 SA_MA14 SA_MA15
DDR CHANNEL A
SA_DQSN0 SA_DQSN1 SA_DQSN2 SA_DQSN3 SA_DQSN4 SA_DQSN5 SA_DQSN6 SA_DQSN7 SA_DQSP0 SA_DQSP1 SA_DQSP2 SA_DQSP3 SA_DQSP4 SA_DQSP5 SA_DQSP6 SA_DQSP7 SM_VREF_CA SM_VREF_DQ0 SM_VREF_DQ1
3 OF 19
AU37 AV37 AW36 AY36
M_CLK_DDR#0 M_CLK_DDR0 M_CLK_DDR#1 M_CLK_DDR1
AU43 AW43 AY42 AY43
DDR_CKE0_DIMMA DDR_CKE1_DIMMA
AP33 AR32
DDR_CS0_DIMMA# DDR_CS1_DIMMA#
M_CLK_DDR#0 M_CLK_DDR0 M_CLK_DDR#1 M_CLK_DDR1
<18> <18> <18> <18>
DDR_CKE0_DIMMA DDR_CKE1_DIMMA
<18> <18>
DDR_CS0_DIMMA# DDR_CS1_DIMMA#
<18> <18>
AP32 AY34 AW34 AU34
DDR_A_RAS# DDR_A_WE# DDR_A_CAS#
AU35 AV35 AY41
DDR_A_BS0 DDR_A_BS1 DDR_A_BS2
AU36 AY37 AR38 AP36 AU39 AR36 AV40 AW39 AY39 AU40 AP35 AW41 AU41 AR35 AV42 AU42
DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13 DDR_A_MA14 DDR_A_MA15
AJ61 AN62 AM58 AM55 AV57 AV53 AL43 AL48
DDR_A_DQS#0 DDR_A_DQS#1 DDR_A_DQS#2 DDR_A_DQS#3 DDR_A_DQS#4 DDR_A_DQS#5 DDR_A_DQS#6 DDR_A_DQS#7
AJ62 AN61 AN58 AN55 AW57 AW53 AL42 AL49
DDR_A_DQS0 DDR_A_DQS1 DDR_A_DQS2 DDR_A_DQS3 DDR_A_DQS4 DDR_A_DQS5 DDR_A_DQS6 DDR_A_DQS7
AP49 AR51 AP51
DDR_A_RAS# DDR_A_WE# DDR_A_CAS#
<18> <18> <18>
DDR_A_BS0 <18> DDR_A_BS1 <18> DDR_A_BS2 <18> DDR_A_MA[0..15]
<18>
DDR_A_DQS#[0..7]
DDR_A_DQS[0..7]
UC1D
DDR_B_D[0..63]
<18>
<18>
+SM_VREF_CA +SM_VREF_DQ0 +SM_VREF_DQ1
DDR_B_D0 DDR_B_D1 DDR_B_D2 DDR_B_D3 DDR_B_D4 DDR_B_D5 DDR_B_D6 DDR_B_D7 DDR_B_D8 DDR_B_D9 DDR_B_D10 DDR_B_D11 DDR_B_D12 DDR_B_D13 DDR_B_D14 DDR_B_D15 DDR_B_D16 DDR_B_D17 DDR_B_D18 DDR_B_D19 DDR_B_D20 DDR_B_D21 DDR_B_D22 DDR_B_D23 DDR_B_D24 DDR_B_D25 DDR_B_D26 DDR_B_D27 DDR_B_D28 DDR_B_D29 DDR_B_D30 DDR_B_D31 DDR_B_D32 DDR_B_D33 DDR_B_D34 DDR_B_D35 DDR_B_D36 DDR_B_D37 DDR_B_D38 DDR_B_D39 DDR_B_D40 DDR_B_D41 DDR_B_D42 DDR_B_D43 DDR_B_D44 DDR_B_D45 DDR_B_D46 DDR_B_D47 DDR_B_D48 DDR_B_D49 DDR_B_D50 DDR_B_D51 DDR_B_D52 DDR_B_D53 DDR_B_D54 DDR_B_D55 DDR_B_D56 DDR_B_D57 DDR_B_D58 DDR_B_D59 DDR_B_D60 DDR_B_D61 DDR_B_D62 DDR_B_D63
AY31 AW31 AY29 AW29 AV31 AU31 AV29 AU29 AY27 AW27 AY25 AW25 AV27 AU27 AV25 AU25 AM29 AK29 AL28 AK28 AR29 AN29 AR28 AP28 AN26 AR26 AR25 AP25 AK26 AM26 AK25 AL25 AY23 AW23 AY21 AW21 AV23 AU23 AV21 AU21 AY19 AW19 AY17 AW17 AV19 AU19 AV17 AU17 AR21 AR22 AL21 AM22 AN22 AP21 AK21 AK22 AN20 AR20 AK18 AL18 AK20 AM20 AR18 AP18
1
HASWELL_MCP_E
SB_DQ0 SB_DQ1 SB_DQ2 SB_DQ3 SB_DQ4 SB_DQ5 SB_DQ6 SB_DQ7 SB_DQ8 SB_DQ9 SB_DQ10 SB_DQ11 SB_DQ12 SB_DQ13 SB_DQ14 SB_DQ15 SB_DQ16 SB_DQ17 SB_DQ18 SB_DQ19 SB_DQ20 SB_DQ21 SB_DQ22 SB_DQ23 SB_DQ24 SB_DQ25 SB_DQ26 SB_DQ27 SB_DQ28 SB_DQ29 SB_DQ30 SB_DQ31 SB_DQ32 SB_DQ33 SB_DQ34 SB_DQ35 SB_DQ36 SB_DQ37 SB_DQ38 SB_DQ39 SB_DQ40 SB_DQ41 SB_DQ42 SB_DQ43 SB_DQ44 SB_DQ45 SB_DQ46 SB_DQ47 SB_DQ48 SB_DQ49 SB_DQ50 SB_DQ51 SB_DQ52 SB_DQ53 SB_DQ54 SB_DQ55 SB_DQ56 SB_DQ57 SB_DQ58 SB_DQ59 SB_DQ60 SB_DQ61 SB_DQ62 SB_DQ63
D
SB_CK#0 SB_CK0 SB_CK#1 SB_CK1 SB_CKE0 SB_CKE1 SB_CKE2 SB_CKE3 SB_CS#0 SB_CS#1 SB_ODT0 SB_RAS SB_WE SB_CAS SB_BA0 SB_BA1 SB_BA2
DDR CHANNEL B
SB_MA0 SB_MA1 SB_MA2 SB_MA3 SB_MA4 SB_MA5 SB_MA6 SB_MA7 SB_MA8 SB_MA9 SB_MA10 SB_MA11 SB_MA12 SB_MA13 SB_MA14 SB_MA15 SB_DQSN0 SB_DQSN1 SB_DQSN2 SB_DQSN3 SB_DQSN4 SB_DQSN5 SB_DQSN6 SB_DQSN7 SB_DQSP0 SB_DQSP1 SB_DQSP2 SB_DQSP3 SB_DQSP4 SB_DQSP5 SB_DQSP6 SB_DQSP7
AM38 AN38 AK38 AL38
M_CLK_DDR#2 M_CLK_DDR2 M_CLK_DDR#3 M_CLK_DDR3
AY49 AU50 AW49 AV50
DDR_CKE2_DIMMB DDR_CKE3_DIMMB
AM32 AK32
DDR_CS2_DIMMB# DDR_CS3_DIMMB#
M_CLK_DDR#2 M_CLK_DDR2 M_CLK_DDR#3 M_CLK_DDR3
<19> <19> <19> <19>
DDR_CKE2_DIMMB DDR_CKE3_DIMMB
<19> <19>
DDR_CS2_DIMMB# DDR_CS3_DIMMB#
<19> <19>
AL32 AM35 AK35 AM33
DDR_B_RAS# DDR_B_WE# DDR_B_CAS#
AL35 AM36 AU49
DDR_B_BS0 DDR_B_BS1 DDR_B_BS2
AP40 AR40 AP42 AR42 AR45 AP45 AW46 AY46 AY47 AU46 AK36 AV47 AU47 AK33 AR46 AP46
DDR_B_MA0 DDR_B_MA1 DDR_B_MA2 DDR_B_MA3 DDR_B_MA4 DDR_B_MA5 DDR_B_MA6 DDR_B_MA7 DDR_B_MA8 DDR_B_MA9 DDR_B_MA10 DDR_B_MA11 DDR_B_MA12 DDR_B_MA13 DDR_B_MA14 DDR_B_MA15
AW30 AV26 AN28 AN25 AW22 AV18 AN21 AN18
DDR_B_DQS#0 DDR_B_DQS#1 DDR_B_DQS#2 DDR_B_DQS#3 DDR_B_DQS#4 DDR_B_DQS#5 DDR_B_DQS#6 DDR_B_DQS#7
AV30 AW26 AM28 AM25 AV22 AW18 AM21 AM18
DDR_B_DQS0 DDR_B_DQS1 DDR_B_DQS2 DDR_B_DQS3 DDR_B_DQS4 DDR_B_DQS5 DDR_B_DQS6 DDR_B_DQS7
DDR_B_RAS# DDR_B_WE# DDR_B_CAS#
<19> <19> <19>
DDR_B_BS0 <19> DDR_B_BS1 <19> DDR_B_BS2 <19> DDR_B_MA[0..15]
<19>
C
DDR_B_DQS#[0..7]
<19>
DDR_B_DQS[0..7]
<19>
B
4 OF 19
Rev1p2
Rev1p2
A
A
DELL CONFIDENTIAL/PROPRIETARY PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 5
4
3
2
Compal Electronics, Inc. Title
MCP(3/12) Size
Document Number
Date:
Friday, May 17, 2013
Rev 0.3
LA-9431P Sheet 1
8
of
59
5
4
3
2
1
+3.3V_ALW_PCH
+RTC_CELL
2
B
O 3
A
RC71
PCH_PCIE_WAKE# 10K_0402_5%
PCH_DPWROK @ RC79
1
2
PCH_RSMRST#_R 0_0402_5%
ME_SUS_PWR_ACK_R @ RC82
1
2
SUSACK#_R 0_0402_5%
RESET_OUT#
1
2
SYS_PWROK_R 0_0402_5%
@ RC84
PCH_PLTRST#_EC
PCH_PLTRST#_EC
<25,29,31,36,37>
1 DSWODVREN
0.1U_0402_25V6
UC3 TC7SH08FU_SSOP5~D
<37>
PM_APWROK
SIO_SLP_A#
1
PM_APWROK
2
B A
4
O 3
2
4
2
1
PCH_PLTRST#
PM_APWROK_R
UC7 TC7SH08FU_SSOP5~D
1
D
1
SYS_RESET#
@ UC2 74AHC1G09GW_TSSOP5~D
5
4
@ RC78 330K_0402_1%
1
D
+3.3V_ALW2 @ CC82 1 2
5
0.1U_0402_25V6
O A
3
+PCH_VCCDSW3_3
B
2
P
1 ME_RESET# 8.2K_0402_5%
2
G
2
P
1
XDP_DBRESET# @ RC76
@ CC9 1
0.1U_0402_25V6
G
5
@ RC74
SUS_STAT#/LPCPD# 10K_0402_5%
P
2
G
1
RC73 330K_0402_1%
1 2 @ RC72 0_0402_5% +3.3V_RUN @ CC8 1 2
2
+3.3V_RUN
2
@ RC144
0_0402_5%
DSWODVREN - ON DIE DSW VR ENABLE
+3.3V_RUN
HIGH = ENABLED (DEFAULT) 1
2
@ RC81
ME_RESET# 8.2K_0402_5%
HASWELL_MCP_E
UC1H
LOW = DISABLED
SYSTEM POWER MANAGEMENT
<12,36>
<20> <29> <30> <28>
+3.3V_ALW_PCH
<21> RP10
1 2 3 4
8 7 6 5
ME_SUS_PWR_ACK USB_OC3# SIO_EXT_WAKE# KB_DET#
@ RC86
SUSACK#
<36,9> SYS_PWROK <15,37> RESET_OUT# @ RC300 1 PLTRST_NFC# 1 @ RC89 PLTRST_USH# 1 @ RC90 PLTRST_MMI# 1 @ RC91 PLTRST_LAN# 1 @ RC92 PLTRST_VMM2320# <38> PCH_RSMRST#_Q <37> ME_SUS_PWR_ACK
2 2 2 2 2
@ RC87 @ RC88 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% @ RC93 @ RC94
1
2 0_0402_5%
1 1
2 0_0402_5% 2 0_0402_5%
SUSACK#_R SYS_RESET# SYS_PWROK_R PCH_PWROK PM_APWROK_R PCH_PLTRST#
2 0_0402_5% PCH_RSMRST#_R 2 0_0402_5% ME_SUS_PWR_ACK_R SIO_PWRBTN# <37,9> SIO_PWRBTN# AC_PRESENT <12,37> AC_PRESENT PCH_BATLOW# <12> PCH_BATLOW# SIO_SLP_S0# <37> SIO_SLP_S0# <36> SIO_SLP_WLAN#
USB_OC3# <11> SIO_EXT_WAKE# <12,36> KB_DET# <12,38>
1 1
AK2 AC3 AG2 AY7 AB5 AG7
AW6 AV4 AL7 AJ8 AN4 AF3 AM5
SUSACK SYS_RESET SYS_PWROK PCH_PWROK APWROK PLTRST
DSWVRMEN DPWROK WAKE
AW7 AV5 AJ5
DSWODVREN PCH_DPWROK PCH_PCIE_WAKE#
V5 AG4 AE6 AP5
CLKRUN# SUS_STAT#/LPCPD# SUSCLK SIO_SLP_S5#
AJ6 AT4 AL5 AP4 AJ7
SIO_SLP_S4# SIO_SLP_S3# SIO_SLP_A# SIO_SLP_SUS# SIO_SLP_LAN#
PCH_DPWROK <36> PCH_PCIE_WAKE# <37> JAPS1 CONN@
CLKRUN/GPIO32 SUS_STAT/GPIO61 SUSCLK/GPIO62 SLP_S5/GPIO63
RSMRST SUSWARN/SUSPWRDNACK/GPIO30 PWRBTN ACPRESENT/GPIO31 BATLOW/GPIO72 SLP_S0 SLP_WLAN/GPIO29
SLP_S4 SLP_S3 SLP_A SLP_SUS SLP_LAN
CLKRUN# T10
+3.3V_ALW_PCH
<10,29,36,37>
SIO_SLP_S3#
+PCH_VCCDSW3_3
PAD~D@ SIO_SLP_S5# <37> T11 PAD~D@ T12 PAD~D @ SIO_SLP_S4# <36,39,43> SIO_SLP_S3# <36,39,43> SIO_SLP_A# <36,39,44> SIO_SLP_SUS# <36> SIO_SLP_LAN# <28,36>
SIO_SLP_S5# SIO_SLP_S4# SIO_SLP_A#
+PCH_VCCDSW3_3 <6>
PCH_RTCRST#
PCH_RTCRST#
<37,40>
POWER_SW#_MB
POWER_SW#_MB
10K_8P4R_5%
SYS_RESET# SIO_SLP_S0# Rev1p2
8 OF 19
1
2
RC136
PCH_RSMRST#_R 10K_0402_5% +3.3V_RUN
C
XDP@
2
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 GND GND ACES_50506-01841-P01 C
CC41 1
UC6
XDP@
0.1U_0402_25V6
14 <6>
1 PCH_JTAG_TDO XDP@ RC95
PCH_JTAG_TDO
2 TDO_XDP 0_0402_5%
2
1 RC103 XDP@
2 TDI_XDP_R 0_0402_5%
<6>
PCH_JTAG_TMS
2 TMS_XDP 0_0402_5%
9 10
RUNPWROK TRST#_XDP
<36,37>
H_PROCHOT#
12 13
RUNPWROK
RUNPWROK
5 4
RUNPWROK
1 RC101 XDP@
2A
@ CC149 22P_0402_50V8J
2
CPU_XDP_TDO
6
CPU_XDP_TDI
2B
8
CPU_XDP_TMS
1
2OE 3A
3B
2
2
@
+1.05V_RUN
4B
4OE
GND
11
CPU_XDP_TRST#
Place near JXDP1 7 15
2
<6>
2
PCH_JTAG_JTAGX
RC5 need to close to JCPU1
<15>
1 CPU_XDP_TCLK RC97 @
0_0402_5%
2
+1.05V_VCCST
1
<13> <13>
CFG2 CFG3
CFG2 CFG3
<15>
2 PCH_JTAG_TDO 0_0402_5%
1 TDI_XDP_R RC104 @
2 PCH_JTAG_TCK 0_0402_5%
1 CPU_XDP_TCLK RC124 @
<18,19,31,7> <18,19,31,7>
<13> <13>
CFG4 CFG5
CFG4 CFG5
CFG6 <13> CFG6 2 1K_0402_5% RC105 1 CFG7 <13> CFG7 XDP@ 2 1K_0402_5% H_CPUPWRGD @ RC106 1 H_VCCST_PWRGD_XDP 2 0_0402_5% @ RC107 1 CFD_PWRBTN#_XDP SIO_PWRBTN#
H_VCCST_PWRGD <37,9>
1 TDO_XDP RC123 @
0_0402_5% B
@ RC113
CFG0 CFG1
CFG0 CFG1
XDP_OBS0_R XDP_OBS1_R
1 CPU_XDP_TRST# RC135 @
0_0402_5%
ESD request, place near CPU side
1
<13> <13>
74CBTLV3126BQ_DHVQFN14_2P5X3
PCH_JTAG_TRST#
CPU_PWR_DEBUG# <36,9> SYS_PWROK
DDR_XDP_WAN_SMBDAT DDR_XDP_WAN_SMBCLK <6> PCH_JTAG_TCK
@ RC108 @ RC110
1 1
2 0_0402_5% 2 0_0402_5%
CPU_PWR_DEBUG#_R SYS_PWROK_XDP
@ RC111 @ RC112 @ RC142
1 1 1
2 0_0402_5% 2 0_0402_5% 2 0_0402_5%
DDR_XDP_SMBDAT_R1 DDR_XDP_SMBCLK_R1 PCH_JTAG_TCK_R CPU_XDP_TCLK
GND0 GND1 OBSFN_A0 OBSFN_C0 OBSFN_A1 OBSFN_C1 GND2 GND3 OBSDATA_A0 OBSDATA_C0 OBSDATA_A1 OBSDATA_C1 GND4 GND5 OBSDATA_A2 OBSDATA_C2 OBSDATA_A3 OBSDATA_C3 GND6 GND7 OBSFN_B0 OBSFN_D0 OBSFN_B1 OBSFN_D1 GND8 GND9 OBSDATA_B0 OBSDATA_D0 OBSDATA_B1 OBSDATA_D1 GND10 GND11 OBSDATA_B2 OBSDATA_D2 OBSDATA_B3 OBSDATA_D3 GND12 GND13 PWRGOOD/HOOK0 ITPCLK/HOOK4 HOOK1 ITPCLK#/HOOK5 VCC_OBS_AB VCC_OBS_CD HOOK2 RESET#/HOOK6 HOOK3 DBR#/HOOK7 GND14 GND15 SDA TD0 SCL TRST# TCK1 TDI TCK0 TMS GND16 GND17 SAMTE_BSH-030-01-L-D-A CONN@
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60
CFG17 CFG16
CFG17 CFG16
CFG8 CFG9
CFG8 CFG9
CFG10 CFG11
CFG10 CFG11
<13> <13>
CFG19 CFG18
CFG19 CFG18
<13> <13>
CFG12 CFG13
CFG12 CFG13
<13> <13>
CFG14 CFG15
CFG14 CFG15
<13> <13>
XDP_RST#_R XDP_DBRESET#
<13> <13> <13> <13>
2
1
RC109 XDP@
TDO_XDP TRST#_XDP TDI_XDP TMS_XDP 1 CFG3_R RC99 XDP@
PCH_PLTRST#_EC 1K_0402_5% B
2 CFG3 1K_0402_5%
+1.05V_RUN
2
H_CATERR# 49.9_0402_1% 2 H_PROCHOT# 62_0402_5%
2 1 2
XDP@ RC102 1K_0402_5%
1 2
1
HASWELL_MCP_E
UC1B
<36> ESD request
CPU_DETECT# <37>
PECI_EC
CPU_DETECT# H_CATERR# PECI_EC
D61 K61 N62
2H_PROCHOT#_R 56_0402_5%
K63
2 PROC_DETECT CATERR PECI
MISC
PRDY PREQ PROC_TCK PROC_TMS PROC_TRST PROC_TDI PROC_TDO
JTAG
CAD Note: Avoid stub in the PWRGD path while placing resistors RC115
<37,46,47,48>
H_PROCHOT#
1 RC117
H_CPUPWRGD
C61
PROCHOT
PROCPWRGD
THERMAL
2
1RC125
SM_RCOMP0
121_0402_1%
2
1RC129
SM_RCOMP1
100_0402_1%
2
1RC133
SM_RCOMP2
SM_RCOMP0 SM_RCOMP1 SM_RCOMP2 <18>
DDR3_DRAMRST#_CPU <18> DDR_PG_CTRL
CAD Note: Trace width=12~15 mil, Spcing=20 mils Max trace length= 500 mil
AU60 AV60 AU61 AV15 AV61
SM_RCOMP0 SM_RCOMP1 SM_RCOMP2 SM_DRAMRST SM_PG_CNTL1
CPU_XDP_PRDY# CPU_XDP_PREQ# CPU_XDP_TCLK CPU_XDP_TMS CPU_XDP_TRST# CPU_XDP_TDI CPU_XDP_TDO
J60 H60 H61 H62 K59 H63 K60 J61
XDP_OBS0_R XDP_OBS1_R XDP_OBS2_R XDP_OBS3_R XDP_OBS4_R XDP_OBS5_R XDP_OBS6_R XDP_OBS7_R
Place near JXDP1.48
SYS_PWROK_XDP
1
@ CC48 0.1U_0402_25V6
2
PU/PD for JTAG signals +3.3V_RUN
Place near JXDP1.47
RC116 2
1 1K_0402_5%
CPU_XDP_TMS
@ RC118 2
1 51_0402_1%
CPU_XDP_TDI
@ RC119 2
1 51_0402_1%
CPU_XDP_PREQ#
XDP_DBRESET#
+1.05V_RUN
BPM#0 BPM#1 BPM#2 BPM#3 BPM#4 BPM#5 BPM#6 BPM#7
DDR3
PAD~D PAD~D PAD~D PAD~D PAD~D PAD~D
T122 T126 T129 T130 T131 T132
@ @ @ @ @ @
@ RC120 2
1 51_0402_1%
CPU_XDP_TDO
RC122 2
1 51_0402_1%
CPU_XDP_TCLK
RC127 2
1 51_0402_1%
@ RC131 2
1 51_0402_1%
CPU_XDP_TRST#
A
Rev1p2
2 OF 19
DELL CONFIDENTIAL/PROPRIETARY PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
XDP@ CC68 0.1U_0402_25V6
PWR
DDR3 COMPENSATION SIGNALS 200_0402_1%
J62 K62 E60 E61 E59 F63 F62
1 51_0402_1%
XDP_DBRESET#
@
1
CC90
100P_0402_50V8J
RC115 10K_0402_5%
reference CRB
TDO_XDP @ RC280 2
+3.3V_ALW_PCH
H_CPUPWRGD
A
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59
CPU_XDP_PREQ# CPU_XDP_PRDY#
4A
+1.05V_RUN
JXDP1
reference Shark Bay ULT Validation Customer Debug Port Implementation Requirement Rev 1.0 <6>
RC114
1
@
3OE
GND PAD
1
3
CC11 0.1U_0402_25V6
2 TDI_XDP 0_0402_5%
1B
1OE CC10 0.1U_0402_25V6
1 RC96 XDP@
PCH_JTAG_TDI
1A
+1.05V_RUN
1
RUNPWROK <6>
VCC
4
3
2
Compal Electronics, Inc. Title
MCP(4/12) Size
Document Number
Date:
Friday, May 17, 2013
Rev 0.3
LA-9431P Sheet 1
9
of
59
5
4
3
UC1A
D
+3.3V_RUN 1
2
CONTACTLESS_DET# 10K_0402_5%
1
2
TOUCHPAD_INTR# 10K_0402_5%
1
2
TOUCH_RST_N_GYRO_INT1 10K_0402_5%
RC137
RC140
<23> <23> <23> <23> <23> <23> <23> <23>
DDI1_LANE_N0 DDI1_LANE_P0 DDI1_LANE_N1 DDI1_LANE_P1 DDI1_LANE_N2 DDI1_LANE_P2 DDI1_LANE_N3 DDI1_LANE_P3
<27> <27> <27> <27> <27> <27> <27> <27>
DDI2_LANE_N0 DDI2_LANE_P0 DDI2_LANE_N1 DDI2_LANE_P1 DDI2_LANE_N2 DDI2_LANE_P2 DDI2_LANE_N3 DDI2_LANE_P3
DDI1_LANE_N0 DDI1_LANE_P0 DDI1_LANE_N1 DDI1_LANE_P1 DDI1_LANE_N2 DDI1_LANE_P2 DDI1_LANE_N3 DDI1_LANE_P3
C54 C55 B58 C58 B55 A55 A57 B57
DDI2_LANE_N0 DDI2_LANE_P0 DDI2_LANE_N1 DDI2_LANE_P1 DDI2_LANE_N2 DDI2_LANE_P2 DDI2_LANE_N3 DDI2_LANE_P3
C51 C50 C53 B54 C49 B50 A53 B53
DDI1_TXN0 DDI1_TXP0 DDI1_TXN1 DDI1_TXP1 DDI1_TXN2 DDI1_TXP2 DDI1_TXN3 DDI1_TXP3
2
1
HASWELL_MCP_E
EDP_TXN0 EDP_TXP0 EDP_TXN1 EDP_TXP1
DDI
EDP_TXN2 EDP_TXP2 EDP_TXN3 EDP_TXP3
EDP
DDI2_TXN0 DDI2_TXP0 DDI2_TXN1 DDI2_TXP1 DDI2_TXN2 DDI2_TXP2 DDI2_TXN3 DDI2_TXP3
EDP_AUXN EDP_AUXP EDP_RCOMP EDP_DISP_UTIL
C45 B46 A47 B47
EDP_CPU_LANE_N0 EDP_CPU_LANE_P0 EDP_CPU_LANE_N1 EDP_CPU_LANE_P1
EDP_CPU_LANE_N0 EDP_CPU_LANE_P0 EDP_CPU_LANE_N1 EDP_CPU_LANE_P1
COMPENSATION PU FOR eDP
<22> <22> <22> <22>
follow intel feedback +VCCIOA_OUT
C47 C46 A49 B49
EDP_COMP 24.9_0402_1%
A45 B45 D20 A43
EDP_CPU_AUX# EDP_CPU_AUX
EDP_CPU_AUX# EDP_CPU_AUX
2
1 RC134 D
CAD Note:Trace width=20 mils ,Spacing=25mil, Max length=100 mils.
<22> <22>
EDP_COMP
Rev1p2
1 OF 19
+3.3V_RUN RC202
UC1I
Intel WW18 Strapping option
HASWELL_MCP_E
Intel WW18 Strapping option 1
2
2
1
@ RC152 @ RC154
<22> <22> <22,36>
ENVDD_PCH 100K_0402_5% CODEC_IRQ 1K_0402_5% <29>
C
<12>
EDP_BIA_PWM PANEL_BKLEN ENVDD_PCH
EDP_BIA_PWM PANEL_BKLEN ENVDD_PCH
CONTACTLESS_DET# <7> DGPU_PWROK PIRQ#_TPM @T13 @ T13
DGPU_PWROK PIRQ#_TPM HDD_FALL_INT PAD~D
TOUCHPAD_INTR# TOUCH_RST_N_GYRO_INT1 +3.3V_RUN
CODEC_IRQ
B8 A9 C6
U6 P4 N4 N2 AD4 U7 L1 L3 R5 L4
EDP_BKLCTL EDP_BKLEN EDP_VDDEN
PIRQA/GPIO77 PIRQB/GPIO78 PIRQC/GPIO79 PIRQD/GPIO80 PME
DDPB_CTRLCLK DDPB_CTRLDATA DDPC_CTRLCLK DDPC_CTRLDATA
eDP SIDEBAND
DDPB_AUXN DDPC_AUXN DDPB_AUXP DDPC_AUXP
DISPLAY
GPIO
B9 C9 D9 D11
CPU_DPB_CTRLCLK CPU_DPB_CTRLDAT CPU_DPC_CTRLCLK CPU_DPC_CTRLDAT
C5 B6 B5 A6
CPU_DPB_AUX# CPU_DPC_AUX# CPU_DPB_AUX CPU_DPC_AUX
C8 A8 D6
DPB_HPD DPC_HPD
1 CLKRUN# <29,36,37,9> LANCLK_REQ# <28,7>
Rev1p2
9 OF 19
<6> 2
PCH_GPIO36
C
<27>
DPC_HPD
2
1
2
1
2
1
100K_0402_5%
<27>
CPU_DPB_AUX
RC151
10K_8P4R_5%
reference PDG 0.9
1
2
RC153
100K_0402_5%
DPB_HPD <23> DPC_HPD <27> EDP_CPU_HPD <22>
RC155
CC450 0.1U_0402_25V6
CLKRUN# LANCLK_REQ# HDD_FALL_INT PCH_GPIO36
CPU_DPC_AUX
CPU_DPC_AUX DDPB_HPD DDPC_HPD EDP_HPD
RC158 100K_0402_5%
8 7 6 5
CPU_DPC_AUX#
<23> <23> <27> <27>
1 RC139 1 RC141 1 RC143 1 RC145 1 RC147 1 RC149
100K_0402_5%
GPIO55 GPIO52 GPIO54 GPIO51 GPIO53
RP6 1 2 3 4
CPU_DPB_CTRLCLK CPU_DPB_CTRLDAT CPU_DPC_CTRLCLK CPU_DPC_CTRLDAT
2 CPU_DPB_CTRLCLK 2.2K_0402_5% 2 CPU_DPB_CTRLDAT 2.2K_0402_5% 2 CPU_DPC_CTRLCLK 2.2K_0402_5% 2 CPU_DPC_CTRLDAT 2.2K_0402_5% 2 CPU_DPB_AUX# 100K_0402_5% 2 CPU_DPC_AUX# 100K_0402_5%
@
ESD solution for black screen issue
B
B
A
A
DELL CONFIDENTIAL/PROPRIETARY PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 5
4
3
2
Compal Electronics, Inc. Title
MCP(5/12) Size
Document Number
Rev 0.3
LA-9431P Date:
Friday, May 17, 2013
Sheet 1
10
of
59
5
4
3
2
1
D
D
HASWELL_MCP_E
PCIE_PRX_MMITX_N5 PCIE_PRX_MMITX_P5
<30> <30>
PCIE_PTX_MMIRX_N5 PCIE_PTX_MMIRX_P5
PCIE_PTX_MMIRX_N5 PCIE_PTX_MMIRX_P5
C23 C22 F8 E8 B23 A23 H10 G10 B21 C21 E6 F6
C
B22 A21
10/100/1G LAN --->
<28> <28>
WLAN (Mini Card 2)--->
<31> <31> <31> <31>
PCIE_PTX_GLANRX_N3 PCIE_PTX_GLANRX_P3 PCIE_PRX_WLANTX_N4 PCIE_PRX_WLANTX_P4 PCIE_PTX_WLANRX_N4 PCIE_PTX_WLANRX_P4
Ext USB Port 2 <----
PCIE_PRX_GLANTX_N3 PCIE_PRX_GLANTX_P3
G11 F11
PCIE_PTX_GLANRX_N3 PCIE_PTX_GLANRX_P3
C29 B30
PCIE_PRX_WLANTX_N4 PCIE_PRX_WLANTX_P4
F13 G13
PCIE_PTX_WLANRX_N4 PCIE_PTX_WLANRX_P4
B29 A29
<32> <32>
USB3RN3 USB3RP3
<32> <32>
USB3TN3 USB3TP3
G17 F17 C30 C31 F15 G15 B31 A31
reference CRB
3.01K 1%
B
+PCH_AUSB3PLL
RC161 @RC163 @ RC163
1 1
@ T16 PAD~D @ T17 PAD~D 2 3.01K_0402_1% PCH_PCIE_RCOMP 2 0_0402_5% PCH_PCIE_IREF
E15 E13 A27 B27
USB2N0 USB2P0
PETN5_L0 PETP5_L0
USB2N1 USB2P1
PERN5_L1 PERP5_L1
USB2N2 USB2P2
PETN5_L1 PETP5_L1
USB2N3 USB2P3
PERN5_L2 PERP5_L2
USB2N4 USB2P4
PETN5_L2 PETP5_L2
USB2N5 USB2P5
PERN5_L3 PERP5_L3
USB2N6 USB2P6
PETN5_L3 PETP5_L3
USB2N7 USB2P7
PERN3 PERP3 PETN3 PETP3
USB3RN1 USB3RP1 USB
PCIe
USB3TN1 USB3TP1
PERN4 PERP4
USB3RN2 USB3RP2
PETN4 PETP4
USB3TN2 USB3TP2
AN8 AM8
USBP0USBP0+
AR7 AT7
USBP1USBP1+
AR8 AP8
USBP2USBP2+
AR10 AT10
USBP3USBP3+
AM15 AL15
USBP4USBP4+
AM13 AN13
USBP5USBP5+
AP11 AN11
USBP6USBP6+
AR13 AP13
USBP7USBP7+
G20 H20 C33 B34 E18 F18 B33 A33
USBP0USBP0+
<33> <33>
----->Ext Port 1 and DOCK2 (USB SW)
USBP1USBP1+
<35> <35>
----->Ext Port 2 IO/B
USBP2USBP2+
<31> <31>
----->WLAN/BT
USBP3USBP3+
<22> <22>
USBP4USBP4+
<29> <29>
USBP5USBP5+
<32> <32>
USBP6USBP6+
<31> <31>
----->WWAN
USBP7USBP7+
<22> <22>
----->Touch
USB3RN1 USB3RP1
<35> <35>
USB3TN1 USB3TP1
<35> <35>
USB3RN2 USB3RP2
<33> <33>
USB3TN2 USB3TP2
<33> <33>
----->Camera ----->USH ----->Ext Port 3 and DOCK1(USB SW)
USBRBIAS
----->Ext USB3 Port 1
----->Ext USB3 Port 3 IO/B
PERN1/USB3RN3 PERP1/USB3RP3 PETN1/USB3TN3 PETP1/USB3TP3
USBRBIAS USBRBIAS RSVD RSVD
PERN2/USB3RN4 PERP2/USB3RP4 PETN2/USB3TN4 PETP2/USB3TP4
OC0/GPIO40 OC1/GPIO41 OC2/GPIO42 OC3/GPIO43
RSVD RSVD PCIE_RCOMP PCIE_IREF
AJ10 AJ11 AN10 AM10
AL3 AT1 AH2 AV3
CAD NOTE: Route single-end 50-ohms and max 500-mils length. Avoid routing next to clock pins or under stitching capacitors. Recommended minimum spacing to other signal traces is 15 mils.
USBRBIAS PAD~D T14 @ PAD~D T15 @
USB_OC0# USB_OC1# USB_OC2# USB_OC3#
USB_OC0# USB_OC1# USB_OC2# USB_OC3#
C
RC159 22.6_0402_1%
<28> <28>
PCIE_PRX_GLANTX_N3 PCIE_PRX_GLANTX_P3
PERN5_L0 PERP5_L0
1
<30> <30>
MMI -->
F10 E10
2
UC1K PCIE_PRX_MMITX_N5 PCIE_PRX_MMITX_P5
<33> <35> <33> <9>
+3.3V_ALW_PCH
USB_OC1#
1 10K_0402_5%
B
2 RC166
Rev1p2
11 OF 19
+3.3V_ALW_PCH RP5
<12,30>
<7> PCH_SMB_ALERT# MEDIACARD_PWREN
USB_OC2# USB_OC0# PCH_SMB_ALERT# MEDIACARD_PWREN
8 7 6 5
1 2 3 4 10K_8P4R_5%
A
A
DELL CONFIDENTIAL/PROPRIETARY PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 5
4
3
2
Compal Electronics, Inc. Title
MCP(6/12) Size
Document Number
Rev 0.3
LA-9431P Date:
Friday, May 17, 2013
Sheet 1
11
of
59
5
4
3
2
1
+3.3V_RUN
RP2 H_THERMTRIP#
+3.3V_RUN D
2
1
2
1
MPHYP_PWR_EN 100K_0402_5% SIO_EXT_SCI# 100K_0402_5%
RC170 RC199
1
2
1
P1 PCH_AUDIO_EN AU2 SIO_EXT_WAKE# PM_LANPHY_ENABLEAM7 AD6 PCH_GPIO15 Y1 T3 PCH_GPIO17 AD5 AN5 EC_WAKE# AD7 AN3 NFC_IRQ
<36,9> SIO_EXT_WAKE# PM_LANPHY_ENABLE <28> LAN_RST# @ T139 PAD~D
PM_LANPHY_ENABLE 10K_0402_5%
<37> EC_WAKE# <20> PCH_NFC_RST <20> NFC_IRQ
EC_WAKE# 10K_0402_5%
RC206
<30> <11,30>
+3.3V_ALW_PCH suppoer DSW mode
MEDIACARD_RST# AG6 MEDIACARD_PWRENAP1 AL4 SLATE_MODE_R AT5 NFC_DET# AK4 PCH_GPIO44 AB6 U4 PCH_GPIO48 Y3 PCH_GPIO49 TOUCH_PANEL_INTR# P3 Y2 MPHYP_PWR_EN AT3 KB_DET# AH4 PCH_GPIO14 AM4 3.3V_CAM_EN# AG5 SIO_EXT_SMI# AG3 PCH_GPIO46
MEDIACARD_RST# MEDIACARD_PWREN <20>
NFC_DET#
<30>
2
1
2
1
MEDIACARD_IRQ# @ T140 PAD~D @ T141 PAD~D <22> TOUCH_PANEL_INTR# <39> MPHYP_PWR_EN <38,9> KB_DET# @ T138 PAD~D <22> 3.3V_CAM_EN# <37> SIO_EXT_SMI#
PCH_GPIO44 10K_0402_5% MEDIACARD_IRQ# 10K_0402_5%
RC200 RC205
C
<31> 2
1
2
1
2
1
2
1
3.3V_CAM_EN# 100K_0402_5% NFC_IRQ 100K_0402_5% MPHYP_PWR_EN 10K_0402_5% PCH_AUDIO_EN 10K_0402_5%
RC211
@
RC210 RC169 R C169 RC215
<25> <37>
PCH_GPIO9 PCH_GPIO10
@ T137 PAD~D mSATA_DEVSLP HDD_DEVSLP SIO_EXT_SCI# <26> SPKR
SIO_EXT_SCI# SPKR
AM3 AM2 P2 C4 L2 N5 V2
BMBUSY/GPIO76 GPIO8 LAN_PHY_PWR_CTRL/GPIO12 GPIO15 GPIO16 GPIO17 GPIO24 GPIO27 GPIO28 GPIO26 GPIO56 GPIO57 GPIO58 GPIO59 GPIO44 GPIO47 GPIO48 GPIO49 GPIO50 HSIOPC/GPIO71 GPIO13 GPIO14 GPIO25 GPIO45 GPIO46
CPU/ MISC
10K_8P4R_5% RP8
D60 V4 T4 AW15 AF20 AB21
THERMTRIP RCIN/GPIO82 SERIRQ PCH_OPI_RCOMP RSVD RSVD
1 0_0402_5% H_THERMTRIP#_R @ RC172 2 SIO_RCIN# SIO_RCIN# <37> IRQ_SERIRQ IRQ_SERIRQ <29,36,37> PCH_OPI_COMP @ T18 PAD~D @ T19 PAD~D
H_THERMTRIP#
GPIO
LPIO
GPIO9 GPIO10 DEVSLP0/GPIO33 SDIO_POWER_EN/GPIO70 DEVSLP1/GPIO38 DEVSLP2/GPIO39 SPKR/GPIO81
10 OF 19
PCH_GPIO83 PCH_GPIO84 PCH_GPIO85 BBS_BIT PCH_GPIO87 3.3V_TP_EN
PCH_GPIO83 100_0402_5%
8 7 6 5
MEDIACARD_RST# PCH_GPIO46 SUSACK# SIO_EXT_SMI#
PCH_BATLOW# AC_PRESENT
1
LCD_CBL_DET#
LCD_CBL_DET#
I2C0_SDA I2C0_SCL I2C1_SDA_TCH_PAD I2C1_SCL_TCH_PAD USH_DET# CAM_MIC_CBL_DET# PCH_GPIO66 TPM_ID0 TPM_ID1 SLP_ME_CSW_DEV#
2 2
USH_DET# <29> CAM_MIC_CBL_DET#
SLP_ME_CSW_DEV#
<36>
1 0_0402_5% 1 0_0402_5%
1
<21> <38>
<38>
1
1
2 2
2
1
2
RC180 @ 10K_0402_5%
IRQ_SERIRQ 10K_0402_5% USH_DET# 10K_0402_5% LCD_CBL_DET# 10K_0402_5% CPPE# 100K_0402_5% CAM_MIC_CBL_DET# 10K_0402_5% CPUSB# 100K_0402_5% I2C1_SDA_TCH_PAD 2.2K_0402_5% I2C1_SCL_TCH_PAD 2.2K_0402_5% TPM_ID0 10K_0402_5% TPM_ID1 20K_0402_5% SLP_ME_CSW_DEV# 10K_0402_5% 3.3V_HDD_EN 10K_0402_5% I2C0_SDA 2.2K_0402_5% I2C0_SCL 2.2K_0402_5% PCH_GPIO87 10K_0402_5%
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
RC178 RC282 RC189 RC185 RC193 RC191 RC201 RC203 RC284 RC285 RC289 B
RC295 RC204 2
1
1
2
RC208 RC216
2
1 2
I2C1_SCL_VMM
<21>
1
1
I2C1_SDA_VMM
TOUCH_PANEL_INTR#
SPKR
RC168
+3.3V_RUN
RC181 10K_0402_5%
@ RC222 1K_0402_5%
RC190 1K_0402_5%
@ RC287 1K_0402_5%
@ RC288 1K_0402_5% GPIO66
PCH_GPIO15
2
<22>
I2C1_SCL_TCH_PAD
BBS_BIT
1 R24
C
<36,9>
+3.3V_RUN
1
PCH_OPI_COMP 49.9_0402_1%
<22>
+3.3V_RUN
RC218 10K_0402_5%
PCH_GPIO66
+PCH_VCCDSW3_3
1 2 3 4
+1.05V_VCCST
I2C1_SDA_TCH_PAD
+3.3V_ALW_PCH
8 7 6 5
2 H_THERMTRIP# 1K_0402_5%
Rev1p2
@
+3.3V_RUN
@RC283 @ RC283 1K_0402_5%
+3.3V_RUN
PCH_GPIO9 SLATE_MODE_R PCH_BATLOW# AC_PRESENT
2 7@RC292
3.3V_TS_EN <22> 3.3V_HDD_EN <31> CPPE# <31> CPUSB# <31>
CPPE# CPUSB#
I2C1_SCL_TCH_PAD @ RC176 SUSACK#
+3.3V_ALW_PCH
<37>
reference PDG0.9
10K_8P4R_5%
2
D
10K_8P4R_5% R6 L6 N6 L8 R7 L5 N7 K2 J1 K3 J2 G1 K4 G2 J3 J4 F2 F3 G4 F1 E3 F4 D3 E4 C3 E2
GSPI0_CS/GPIO83 GSPI0_CLK/GPIO84 GSPI0_MISO/GPIO85 GSPI0_MOSI/GPIO86 GSPI1_CS/GPIO87 GSPI1_CLK/GPIO88 GSPI1_MISO/GPIO89 GSPI_MOSI/GPIO90 UART0_RXD/GPIO91 UART0_TXD/GPIO92 UART0_RTS/GPIO93 UART0_CTS/GPIO94 UART1_RXD/GPIO0 UART1_TXD/GPIO1 UART1_RST/GPIO2 UART1_CTS/GPIO3 I2C0_SDA/GPIO4 I2C0_SCL/GPIO5 I2C1_SDA/GPIO6 I2C1_SCL/GPIO7 SDIO_CLK/GPIO64 SDIO_CMD/GPIO65 SDIO_D0/GPIO66 SDIO_D1/GPIO67 SDIO_D2/GPIO68 SDIO_D3/GPIO69
I2C1_SDA_TCH_PAD @ RC174
1
1 2 3 4
RP9
RP7
2
8 7 6 5
3.3V_TS_EN PCH_GPIO84 PCH_GPIO85 3.3V_TP_EN
ESD request
<9> <37,9>
+3.3V_ALW_PCH
1 2 3 4
B
1 2 3 4
10K_8P4R_5%
<28> 2
2
HASWELL_MCP_E
UC1J
+PCH_VCCDSW3_3
RC197
1
CC91
2 EC_WAKE# 0_0402_5%
@RC301 @ RC301
8 7 6 5
PIRQ#_TPM PCH_GPIO83 SIO_RCIN#
PIRQ#_TPM
@
1
LAN_WAKE#
100P_0402_50V8J
<28,37>
<10>
GPIO15
GPIO86
GPIO81
TOP-BLOCK SWAP OVERRIDE
BOOT BIOS STRAP BIT BBS
TLS CONFIDENTIALITY
NO REBOOT STRAP
Low depop RC288 (DEFAULT) :Enable High pop RC288:Diable
HIGH LOW(DEFAULT)
HIGH LOW(DEFAULT)
HIGH LOW(DEFAULT)
LPC SPI
503118_503118_LPT_LP_PCH_EDS_Rev1_0
non use GPIO: GPIO0 GPIO3 GPIO10 GPIO14 GPIO17 GPIO21 GPIO22 GPIO24 GPIO36 GPIO38 GPIO48 GPIO49 GPIO51 GPIO54 GPIO59 GPIO60 GPIO66 GPIO70 GPIO73 GPIO79 GPIO87 GPIO93 GPIO94
A
A
DELL CONFIDENTIAL/PROPRIETARY PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 5
4
3
2
Compal Electronics, Inc. Title
MCP(7/12) Size
Document Number
Rev 0.3
LA-9431P Date:
Friday, May 17, 2013
Sheet 1
12
of
59
5
4
3
2
1
CFG STRAPS for CPU D
D
2 UC1S
EAR-STALL/NOT STALL RESET SEQUENCE AFTER PCU PLL IS LOCKE
HASWELL_MCP_E
CFG0
CFG16 CFG18 CFG17 CFG19
CFG8 CFG9 CFG10
AA62 U63 AA61 U62 CFG_RCOMP
A5
@ T33 PAD~D @ T35 @ T37 @ T38 @ T39
V63
E1 D1 J20 H18 B12
PAD~D PAD~D PAD~D PAD~D TDI_IREF
CFG0 CFG1 CFG2 CFG3 CFG4 CFG5 CFG6 CFG7 CFG8 CFG9 CFG10 CFG11 CFG12 CFG13 CFG14 CFG15
RSVD_TP RSVD_TP RSVD_TP RSVD_TP RSVD RSVD_TP RSVD_TP RSVD_TP
RESERVED
RSVD RSVD RSVD PROC_OPI_RCOMP
CFG16 CFG18 CFG17 CFG19
RSVD RSVD
CFG_RCOMP
VSS VSS
RSVD RSVD RSVD
RSVD RSVD RSVD RSVD TD_IREF 19 OF 19
2 RC235 1 RC236
1 2
CFG_RCOMP 49.9_0402_1% TDI_IREF 8.2K_0402_1%
PAD~D T20 @ PAD~D T21 @
C63 C62 B43
PAD~D T22 @ PAD~D T23 @ PAD~D T24 @
A51 B51
PAD~D T25 @ PAD~D T26 @
L60
PAD~D T27 @
N60
PAD~D T28 @
W23 Y22 AY15
CFG1 1
<9> <9> <9> <9>
CFG3 CFG4
1:(Default) Normal Operation; No stall 0:Lane Reversed
2
CFG0 CFG1 CFG2 CFG3 CFG4 CFG5 CFG6 CFG7 CFG8 CFG9 CFG10 CFG11 CFG12 CFG13 CFG14 CFG15
AV63 AU63
@ RC233 1K_0402_1%
C
<9> <9> <9> <9> <9> <9> <9> <9> <9> <9> <9> <9> <9> <9> <9> <9>
AC60 AC62 AC63 AA63 AA60 Y62 Y61 Y60 V62 V61 V60 U60 T63 T62 T61 T60
CFG0 CFG1
@ RC232 1K_0402_1%
1
CFG0
C
PAD~D T29 @ PAD~D T30 @ PROC_OPI_RCOMP
AV62 D58
PAD~D T31 PAD~D T32
@ @
PCH/PCH LESS MODE SELECTION
P22 N21
CFG1
P20 R20
PAD~D T34 PAD~D T36
1:(Default) Normal Operation 0:Lane Reversed
@ @
Rev1p2
PROC_OPI_RCOMP 1 49.9_0402_1%
2 RC237
B
B
CFG4 1 2
1 2
2
1 2
@ RC241 1K_0402_1%
@ RC239 1K_0402_1%
@ RC240 1K_0402_1%
1
CFG8
RC238 1K_0402_1%
CFG9 CFG10
Display Port Presence Strap
A
SAFE MODE BOOT 1: POWER FEATURES ACTIVATED DURING RESET CFG10 0: POWER FEATURES (ESPECIALLY CLOCK GATINE ARE NOT ACTIVATED
NO SVID PROTOCOL CAPABLE VR CONNECTED 1: VRS support SVID protocol are present 0:No VR support SVID is present CFG9 The chip will not generate(OR Respond to) SVID activity
ALLOW THE USE OF NOA ON LOCKED UNITS 1: Enable(Default): Noa will be disable in locked units and enable in un-locked units CFG8 0: Enable Noa will be available pegardless of the locking of the unit
CFG4
1 : Disabled; No Physical Display Port attached to Embedded Display Port 0 : Enabled; An external Display Port device is connected to the Embedded Display Port
A
DELL CONFIDENTIAL/PROPRIETARY PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 5
4
3
2
Compal Electronics, Inc. Title
MCP(8/12) Size
Document Number
Rev 0.3
LA-9431P Date:
Friday, May 17, 2013
Sheet 1
13
of
59
5
4
3
D
2
1
0_0402_5%
1
D
1 @ RC254
HASWELL_MCP_E
UC1Q AY2 DC_TEST_AY2_AW2 AY3 DC_TEST_AY3_AW3 AY60 DC_TEST_AY60 DC_TEST_AY61_AW61 AY61 DC_TEST_AY62_AW62 AY62 B2 TP_DC_TEST_B2 B3 DC_TEST_A3_B3 B61 DC_TEST_A61_B61 B62 B63 DC_TEST_B62_B63 C1 C2 DC_TEST_C1_C2
2
DAISY_CHAIN_NCTF_AY2 DAISY_CHAIN_NCTF_AY3 DAISY_CHAIN_NCTF_AY60 DAISY_CHAIN_NCTF_AY61 DAISY_CHAIN_NCTF_AY62 DAISY_CHAIN_NCTF_B2 DAISY_CHAIN_NCTF_B3 DAISY_CHAIN_NCTF_B61 DAISY_CHAIN_NCTF_B62 DAISY_CHAIN_NCTF_B63 DAISY_CHAIN_NCTF_C1 DAISY_CHAIN_NCTF_C2
DAISY_CHAIN_NCTF_A3 DAISY_CHAIN_NCTF_A4 DAISY_CHAIN_NCTF_A60 DAISY_CHAIN_NCTF_A61 DAISY_CHAIN_NCTF_A62 DAISY_CHAIN_NCTF_AV1 DAISY_CHAIN_NCTF_AW1 DAISY_CHAIN_NCTF_AW2 DAISY_CHAIN_NCTF_AW3 DAISY_CHAIN_NCTF_AW61 DAISY_CHAIN_NCTF_AW62 DAISY_CHAIN_NCTF_AW63 17 OF 19 Rev1p2
A3 A4
DC_TEST_A3_B3 DC_TEST_A4
A60 A61 A62 AV1 AW1 AW2 AW3 AW61 AW62 AW63
DC_TEST_A60 DC_TEST_A61_B61 DC_TEST_A62 DC_TEST_AV1 DC_TEST_AW1 DC_TEST_AY2_AW2 DC_TEST_AY3_AW3 DC_TEST_AY61_AW61 DC_TEST_AY62_AW62 DC_TEST_AW63
2
2 0_0402_5% 2 0_0402_5%
1 @ RC266 1 @ RC268
4
3 2 0_0402_5%
1 @ RC269
C
C
Package Daisy Chain: 1.B2-PKG-C1-PCB-C2-PKG-B3-PCB-A3-PKG-A4 2.A62-PKG-A61-PCB-B61-PKG-B62-PCB-B63-PKG-A60 3.AY60-PKG-AW61-PCB-AY61-PKG-AW62-PCB-AY62-PKG-AW63 4.AW1-PKG-AW3-PCB-AY3-PKG-AW2-PCB-AY2-PKG-AV1
UC1R
@T50 @T52 @T54 @T55
PAD~D PAD~D PAD~D PAD~D
AT2 RSVD_AT2 RSVD_AU44 AU44 RSVD_AV44 AV44 D15 RSVD_D15
@T58 @T60 @T62
PAD~D PAD~D PAD~D
RSVD_F22 RSVD_H22 RSVD_J21
F22 H22 J21
HASWELL_MCP_E
RSVD RSVD RSVD RSVD
RSVD RSVD RSVD RSVD
RSVD RSVD RSVD RSVD RSVD RSVD RSVD
RSVD RSVD RSVD
N23 R23 T23 U10
RSVD_N23 RSVD_R23 RSVD_T23 RSVD_U10
PAD~D PAD~D PAD~D PAD~D
T48 T49 T51 T53
AL1 AM11 AP7 AU10 AU15 AW14 AY14
RSVD_AL1 RSVD_AM11 RSVD_AP7 RSVD_AU10 RSVD_AU15 RSVD_AW14 RSVD_AY14
PAD~D PAD~D PAD~D PAD~D PAD~D PAD~D PAD~D
T56 T57 T59 T61 T63 T64 T65
@ @ @ @ @ @ @ @ @ @ @
B
B
Rev1p2
18 OF 19
A
A
DELL CONFIDENTIAL/PROPRIETARY PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 5
4
3
2
Compal Electronics, Inc. Title
MCP(9/12) Size
Document Number
Rev 0.3
LA-9431P Date:
Friday, May 17, 2013
Sheet 1
14
of
59
5
4
3
2
1
+1.05V_RUN
2 22U_0603_6.3V6M
+3.3V_RUN 1
1
@
2
+VCC_CORE
@
+1.05V_RUN 1 C458
2 22U_0603_6.3V6M
1 C459
2 22U_0603_6.3V6M
1 C460
2 22U_0603_6.3V6M
+VCC_CORE +3.3V_RUN
1
@
@
@
+1.05V_VCCST
2 2
1 0_0402_5%
2 3
NC
VCC
A Y
5
1 @ CC24
4
2 0.1U_0402_25V6
H_VCCST_PWRGD
+1.05V_RUN 1 C461
@ T66 +1.35V_MEM @ T67
2 22U_0603_6.3V6M
GND
1
2
@ T68 @ T69
+VCC_CORE PAD~D PAD~D VCCSENSE
74AUP1G07GW_TSSOP5
RC244 75_0402_1%
<46>
CAD Note: Place the PU resistors close to CPU RC224 close to CPU 300 - 1500mils
<9> <46> <46>
H_VCCST_PWRGD H_VR_EN H_VR_READY
1 1 1
H_VCCST_PWRGD @RC245 @ RC245 H_VR_EN @RC246 @ RC246 H_VR_READY @RC247 @ RC247
<46>
2
VIDALERT_N
H_CPU_SVIDALRT# RC248
<9>
@ T74 @ T75 @ T76 @ T77 @ T78 @ T79 @ T80 @ T81 @ T82 @ T83 @ T84 @ T85 @ T86
1 2
RC249 110_0402_1%
B
CAD Note: Place the PU resistors close to CPU RC249close to CPU 300 - 1500mils VIDSOUT
VIDSOUT
PAD~D PAD~D PAD~D PAD~D PAD~D PAD~D PAD~D PAD~D PAD~D PAD~D PAD~D PAD~D PAD~D
+1.05V_VCCST
+VCC_CORE
+VCC_CORE reference ULT CRB 1 2
RC250 100_0402_1%
VCC_SENSE
E63 AB23 A59 E20 AD23 AA23 AE59
H_CPU_SVIDALRT# L62 N63 VIDSCLK L63 VIDSOUT 2 0_0402_5% VCCST_PWRGD B59 2 0_0402_5% VR_EN F60 2 0_0402_5% VR_READY C59
CPU_PWR_DEBUG#
CPU_PWR_DEBUG#
+1.05V_VCCST
SVID DATA
<46>
1
43_0402_5%
F59 N58 AC58
VIDSCLK
2
1
@ T70 PAD~D +VCCIO_OUT +VCCIOA_OUT @ T71 PAD~D @ T72 PAD~D @ T73 PAD~D
ESD Request
+1.05V_VCCST
SVID ALERT
L59 J58
PAD~D PAD~D
AH26 AJ31 AJ33 AJ37 AN33 AP43 AR48 AY35 AY40 AY44 AY50
CC22
@ RC263
1K_0402_5% RC243 1
1 RESET_OUT#
2
1
2
1
2
@
1
2
D
HASWELL_MCP_E
UC1L
H_VCCST_PWRGD 100P_0402_50V8J
UC4
<37,9>
2
1
+1.35V_MEM
+1.35V_MEM
H_VR_READY RC256 +3.3V_ALW
C
2
@
+VCC_CORE
RC259 10K_0402_5% 2
2 1
2
1
+3.3V_RUN
+VCC_CORE
RC255 10K_0402_5%
H_VR_EN 2 10K_0402_5%
2
1
@
1
@
2
@
+1.05V_VCCST
2
2 22U_0603_6.3V6M
1
CC21 10U_0603_6.3V6M
1 C454
1
CC20 10U_0603_6.3V6M
@
1
CC13 2.2U_0402_6.3V6M
RC258 10K_0402_5%
D
+1.35V_MEM
CC12 2.2U_0402_6.3V6M
1 +VCC_CORE
RESISTOR STUFFING OPTIONS ARE PROVIDED FOR TESTING PURPOSES
CC19 10U_0603_6.3V6M
2 22U_0603_6.3V6M
CC18 10U_0603_6.3V6M
1 C453
CC17 10U_0603_6.3V6M
EMC@
CPU_PWR_DEBUG#
CC16 10U_0603_6.3V6M
0_0603_5%
Reference ULT DDRDG_080912 change to10uX6 2.2uX4 CC52 2.2U_0402_6.3V6M
2 @ RC242
VDDQ DECOUPLING
+1.35V_MEM
+5V_ALW
@
+VCCIO_OUT
+3.3V_ALW 1 C452
@
+1.05V_RUN
EMC@
CC81 2.2U_0402_6.3V6M
2
RC253 150_0402_1%
1
+1.35V_MEM
D63 H59 P62 P60 P61 N59 N61 T59 AD60 AD59 AA59 AE60 AC59 AG58 U59 V59 AC22 AE22 AE23 AB57 AD57 AG57 C24 C28 C32
RSVD RSVD
VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC
VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VCC RSVD RSVD VCC_SENSE RSVD VCCIO_OUT VCCIOA_OUT RSVD RSVD RSVD VIDALERT VIDSCLK VIDSOUT VCCST_PWRGD VR_EN VR_READY
HSW ULT POWER
VSS PWR_DEBUG VSS RSVD_TP RSVD_TP RSVD_TP RSVD_TP RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD VCCST VCCST VCCST VCC VCC VCC VCC VCC VCC
C
B
Rev1p2
12 OF 19 +1.05V_RUN
C36 C40 C44 C48 C52 C56 E23 E25 E27 E29 E31 E33 E35 E37 E39 E41 E43 E45 E47 E49 E51 E53 E55 E57 F24 F28 F32 F36 F40 F44 F48 F52 F56 G23 G25 G27 G29 G31 G33 G35 G37 G39 G41 G43 G45 G47 G49 G51 G53 G55 G57 H23 J23 K23 K57 L22 M23 M57 P57 U57 W57
+1.05V_VCCST PJP11 1
VCCSENSE
VCCSENSE
2
1
2
1
2
CC26 1U_0402_6.3V6K
CAD Note: RC250 SHOULD BE PLACED CLOSE TO CPU
CC50 22U_0603_6.3V6M
PAD-OPEN1x1m
@
<46>
A
A
DELL CONFIDENTIAL/PROPRIETARY PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 5
4
3
2
Compal Electronics, Inc. Title
MCP(10/12) Size
Document Number
Rev 0.3
LA-9431P Date:
Friday, May 17, 2013
Sheet 1
15
of
59
5
4
+1.05V_MODPHY 1
2
+1.05V_M
0_0805_5%
2
1
+ 2
@
1 + 2
@
1 + 2
CC72 330U_D3_2.5VY_R6M
1
CC71 330U_D3_2.5VY_R6M
2
+1.05V_RUN
CC73 330U_D3_2.5VY_R6M
2
1
CC29 1U_0402_6.3V6K
2
1
CC27 1U_0402_6.3V6K
1
CC74 1U_0402_6.3V6K
CC29 place near K9; CC27 place near L10 CC74 place near M9 VCCHSIO S0 Iccmax = 1.838A
@
@ RC262
D
3
+1.05V_MODPHY_PCH
@
D
+1.05V_MODPHY +PCH_AUSB3PLL
AC9 AA9 AH10 V8 W9
VCCSUS3_3 VCCSUS3_3 VCCDSW3_3 VCC3_3 VCC3_3
GPIO/LCC
+PCH_DCPSUS1
1
2
1
2
2
@
CC46 CC47 place near AE9
1
2
1
2
2
1
2
VCCSDIO VCCSDIO
CC59 place near K14 1
CC45 place near U8
U8 T9
1
LPT LP POWER SUS OSCILLATOR
DCPSUS4
AB8
+PCH_DCPSUS4
2 +1.05V_RUN
USB2
RSVD VCC1_05 VCC1_05
AC20 AG16 AG17
@
2
1 RC275
CC60 place near AG16
2
2
2
CC65 place near AG19
+PCH_RTC_VCCSUS3_3
+3.3V_ALW_PCH 2
1 @ RC261
0_0402_5%
+3.3V_ALW 2
1 @ RC264
0_0402_5% 1
2
+PCH_VCCDSW3_3
CC30 1U_0402_6.3V6K
1
Rev1p2
C
1
CC60 1U_0402_6.3V6K
+3.3V_ALW_PCH
SDIO/PLSS
2
1
+3.3V_RUN
+1.5V_THERMAL
CC45 1U_0402_6.3V6K
1
CC63 close to Pin J17 CC64 close to Pin R21
VCCCLK VCCCLK VCCACLKPLL VCCCLK VCCCLK VCCCLK RSVD RSVD RSVD VCCSUS3_3 VCCSUS3_3
1
2
+PCH_VCCDSW 5.11_0402_1%
CC59 0.1U_0402_10V7K
+PCH_VCC1P05
J18 K19 A20 J17 R21 T21 K18 M20 V21 AE20 AE21
13 OF 19
+3.3V_ALW_PCH
VCCTS1_5 VCC3_3 VCC3_3
J15 K14 K16
+PCH_VCCDSW
1
2
2
@
CC65 1U_0402_6.3V6K +PCH_VCCDSW_R
CORE
+1.05V_M
+1.05V_RUN
+3.3V_RUN +1.05V_RUN
CC64 1U_0402_6.3V6K
2
VRM/USB2/AZALIA
THERMAL SENSOR
CC63 1U_0402_6.3V6K
1
@ CC62 10U_0603_6.3V6M
2
@ CC61 1U_0402_6.3V6K
@ CC66 1U_0402_6.3V6K
2
1
AXALIA/HDA
J11 H11 H15 AE8 AF22 AG19 AG20 AE9 AF9 AG8 AD10 AD8
CC34 10U_0603_6.3V6M
1
+PCH_VCCDSW3_3
+PCH_VCCACLKPLL 1
VCC1_05 VCC1_05 VCC1_05 VCC1_05 VCC1_05 DCPSUSBYP DCPSUSBYP VCCASW VCCASW VCCASW DCPSUS1 DCPSUS1
CC47 22U_0805_6.3V6M
CC43 place near V8 CC43 22U_0603_6.3V6M
@
2
CC66 place near AH13 CC61 CC62 place near J13 DcpSus2 S0 Iccmax = 25mA DcpSus3 S0 Iccmax = 10mA
1
+3.3V_RUN
2
0_0603_5%
DCPSUS2
CC34 and CC33 place near J11; CC37 place near AE8
USB3
2
1
+PCH_DCPSUS 1
B
AH13
+3.3V_ALW_PCH
VCCHDA
1 +1.05V_M
CC33 1U_0402_6.3V6K
CC44 place near AH14
DCPSUS3
AG14 AG13
1
+3.3V_M
CC40 place near Y8
Y8
CC37 1U_0402_6.3V6K
1
CC28 place near AC9
RC276
J13 AH14
2 +1.05V_M
VCCSPI
OPI
CC35,CC38, CC39 place near AG10 CC35 1U_0402_6.3V6K
+PCH_DCPSUS
CC28 22U_0603_6.3V6M
2
SPI
AH11 +PCH_RTC_VCCSUS3_3 AG10 AE7 +DCPRRTC 1 2 CC36 0.1U_0402_10V7K
CC46 1U_0402_6.3V6K
CC44 0.1U_0402_10V7K
2
1
VCCSUS3_3 VCCRTC DCPRTC
RTC
CC39 0.1U_0402_10V7K
+3.3V_ALW_PCH
CC56 1U_0402_6.3V6K
1
CC56 place near AA21 VCCAPLL S0 Iccmax = 57mA
CC55 100U_1206_6.3V6M
1 2 2.2UH_LQM2MPN2R2NG0L_30%
RSVD VCCAPLL VCCAPLL
+RTC_CELL mPHY
VCCASW VCCASW
+V1.05S_APLLOPI
LC5
+V1.05S_APLLOPI
Y20 AA21 W21
VCCHSIO VCCHSIO VCCHSIO VCC1_05 VCC1_05 VCCUSB3PLL VCCSATA3PLL
CC38 0.1U_0402_10V7K
2
+PCH_AUSB3PLL +PCH_ASATA3PLL
K9 L10 M9 N8 P9 B18 B11
+1.05V_MODPHY_PCH
CC40 0.1U_0402_10V7K
2
1
CC31 1U_0402_6.3V6K
2
1
HASWELL_MCP_E
UC1M +1.05V_RUN
CC49 22U_0603_6.3V6M
CC49 place near B11 VCCSATA3PLL S0 Iccmax = 42mA
CC77 22U_0603_6.3V6M
1
+1.05V_RUN
2
+PCH_ASATA3PLL
LC2
1 2 2.2UH_LQM2MPN2R2NG0L_30%
C
1
CC42 22U_0603_6.3V6M
+1.05V_MODPHY
2
CC76 22U_0603_6.3V6M
1
CC42 place near B18 VCCUSB3PLL S0 Iccmax = 41mA
@
LC1 1 2 2.2UH_LQM2MPN2R2NG0L_30%
CC30 place near AH11 VCCSUS3_3 S0 Iccmax = 63mA
B
2
@ RC265
0_0402_5%
+PCH_DCPSUS1
+1.05V_M
+3.3V_ALW
1
2
+1.05V_RUN
@
0_0402_5%
CC32 place near AH10 VCCDSW3_3 S0 Iccmax = 114mA
2 1U_0402_6.3V6K @ CC54
@ RC267
2
CC32 1U_0402_6.3V6K
1
1 @ RC272
0_0402_5% 1
CC54 place near AD10 DCPSUS1 S0 Iccmax = 109mA
2
+PCH_VCC1P05 +PCH_DCPSUS4
A
2
1
1
2
2
@
@
@
+1.05V_M
LC4
2 1 2.2UH_LQM2MPN2R2NG0L_30% CC75 100U_1206_6.3V6M
2
1
1U_0402_6.3V6K CC53
CC51 place near J18 VCCCLK S0 Iccmax = 200mA
CC79 100U_1206_6.3V6M
1
CC51 1U_0402_6.3V6K
LC3 1 2 2.2UH_LQM2MPN2R2NG0L_30%
CC53 place near AB8 DCPSUS4 S0 Iccmax = 1mA
+PCH_VCCACLKPLL +1.05V_RUN
DELL CONFIDENTIAL/PROPRIETARY
LC6
2
5
CC78 100U_1206_6.3V6M
1
CC58 place near A20 VCCACLKPLL S0 Iccmax = 31mA
1
2
CC58 1U_0402_6.3V6K
1 2 2.2UH_LQM2MPN2R2NG0L_30%
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 4
3
2
Compal Electronics, Inc. Title
MCP(11/12) Size
Document Number
Date:
Friday, May 17, 2013
Rev 0.3
LA-9431P Sheet 1
16
of
59
A
5
4
3
2
1
D
D
14 OF 19
AJ35 AJ39 AJ41 AJ43 AJ45 AJ47 AJ50 AJ52 AJ54 AJ56 AJ58 AJ60 AJ63 AK23 AK3 AK52 AL10 AL13 AL17 AL20 AL22 AL23 AL26 AL29 AL31 AL33 AL36 AL39 AL40 AL45 AL46 AL51 AL52 AL54 AL57 AL60 AL61 AM1 AM17 AM23 AM31 AM52 AN17 AN23 AN31 AN32 AN35 AN36 AN39 AN40 AN42 AN43 AN45 AN46 AN48 AN49 AN51 AN52 AN60 AN63 AN7 AP10 AP17 AP20
AP22 AP23 AP26 AP29 AP3 AP31 AP38 AP39 AP48 AP52 AP54 AP57 AR11 AR15 AR17 AR23 AR31 AR33 AR39 AR43 AR49 AR5 AR52 AT13 AT35 AT37 AT40 AT42 AT43 AT46 AT49 AT61 AT62 AT63 AU1 AU16 AU18 AU20 AU22 AU24 AU26 AU28 AU30 AU33 AU51 AU53 AU55 AU57 AU59 AV14 AV16 AV20 AV24 AV28 AV33 AV34 AV36 AV39 AV41 AV43 AV46 AV49 AV51 AV55
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
HASWELL_MCP_E
UC1P
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS 15 OF 19 Rev1p2 VSS
AV59 AV8 AW16 AW24 AW33 AW35 AW37 AW4 AW40 AW42 AW44 AW47 AW50 AW51 AW59 AW60 AY11 AY16 AY18 AY22 AY24 AY26 AY30 AY33 AY4 AY51 AY53 AY57 AY59 AY6 B20 B24 B26 B28 B32 B36 B4 B40 B44 B48 B52 B56 B60 C11 C14 C18 C20 C25 C27 C38 C39 C57 D12 D14 D18 D2 D21 D23 D25 D26 D27 D29 D30 D31
D33 D34 D35 D37 D38 D39 D41 D42 D43 D45 D46 D47 D49 D5 D50 D51 D53 D54 D55 D57 D59 D62 D8 E11 E17 F20 F26 F30 F34 F38 F42 F46 F50 F54 F58 F61 G18 G22 G3 G5 G6 G8 H13
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
HASWELL_MCP_E
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS_SENSE 16 OF 19 Rev1p2 VSS
H17 H57 J10 J22 J59 J63 K1 K12 L13 L15 L17 L18 L20 L58 L61 L7 M22 N10 N3 P59 P63 R10 R22 R8 T1 T58 U20 U22 U61 U9 V10 V3 V7 W20 W22 Y10 Y59 Y63
C
V58 AH46 V23 E62 AH16
VSSSENSE
<46>
RC260 100_0402_1%
B
UC1O VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
1
C
HASWELL_MCP_E
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
2
UC1N A11 A14 A18 A24 A28 A32 A36 A40 A44 A48 A52 A56 AA1 AA58 AB10 AB20 AB22 AB7 AC61 AD21 AD3 AD63 AE10 AE5 AE58 AF11 AF12 AF14 AF15 AF17 AF18 AG1 AG11 AG21 AG23 AG60 AG61 AG62 AG63 AH17 AH19 AH20 AH22 AH24 AH28 AH30 AH32 AH34 AH36 AH38 AH40 AH42 AH44 AH49 AH51 AH53 AH55 AH57 AJ13 AJ14 AJ23 AJ25 AJ27 AJ29
CAD Note: RC260 SHOULD BE PLACED CLOSE TO CPU
B
Rev1p2
A
A
DELL CONFIDENTIAL/PROPRIETARY PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 5
4
3
2
Compal Electronics, Inc. Title
MCP(12/12) Size
Document Number
Rev 0.3
LA-9431P Date:
Friday, May 17, 2013
Sheet 1
17
of
59
Reverse Type
+DIMM1_VREF_DQ +1.35V_MEM
+1.35V_MEM
DDR_A_D[0..63]
<8>
DDR_A_DQS[0..7]
<8>
DDR_A_D44 DDR_A_D41 DDR_A_DQS#5 DDR_A_DQS5
DDR_A_MA[0..15]
DDR_A_D43 DDR_A_D47
Note: Check voltage tolerance of VREF_DQ at the DIMM socket
DDR_A_D51 DDR_A_D50
2
1
2
1
2
CD11 1U_0402_6.3V6K
2
1
CD10 1U_0402_6.3V6K
2
1
CD9 1U_0402_6.3V6K
2
1
CD8 1U_0402_6.3V6K
1
CD7 1U_0402_6.3V6K
2
CD6 1U_0402_6.3V6K
1
CD5 1U_0402_6.3V6K
2
CD4 1U_0402_6.3V6K
1 C
<8>
DDR_CKE0_DIMMA <8>
DDR_A_BS2
DDR_CKE0_DIMMA DDR_A_BS2 DDR_A_MA12 DDR_A_MA9 DDR_A_MA8 DDR_A_MA5 DDR_A_MA3 DDR_A_MA1
+1.35V_MEM <8> <8>
2
2
+ 2
<8>
DDR_A_BS0
<8> <8>
DDR_A_WE# DDR_A_CAS#
DDR_CS1_DIMMA#
DDR_A_MA10 DDR_A_BS0 DDR_A_WE# DDR_A_CAS# DDR_A_MA13 DDR_CS1_DIMMA#
DDR_A_D2 DDR_A_D6
Layout Note: Place near JDIMM1.203,204
DDR_A_D21 DDR_A_D20
DDR_A_D17 DDR_A_D16 +0.675V_DDR_VTT DDR_A_D36 DDR_A_D33
2
1
2
DDR_A_DQS#4 DDR_A_DQS4
CD31 10U_0603_6.3V6M
2
1
CD30 10U_0603_6.3V6M
2
1
CD29 0.1U_0402_25V6
2
1
CD28 0.1U_0402_25V6
1
CD27 0.1U_0402_25V6
2
CD26 0.1U_0402_25V6
1
DDR_A_D34 DDR_A_D38 DDR_A_D62 DDR_A_D58
DDR_A_D60 DDR_A_D61 @RD5 @ RD5
2 0_0402_5%
1
2
+3.3V_RUN 1
1
@
2
2
CD24 0.1U_0402_25V6
0_0402_5%
CD25 2.2U_0402_6.3V6M
@RD6 @ RD6
A
1
+0.675V_DDR_VTT
205
G1
G2
1 2
DDR3_DRAMRST#_CPU
<9>
+1.35V_MEM DDR_A_D42 DDR_A_D46 DDR_A_D52 DDR_A_D53
CAD NOTE PLACE THE CAP NEAR TO DIMM RESET PIN
+SM_VREF_DQ0_DIMM1
DDR_A_DQS#6 DDR_A_DQS6
DDR_CKE1_DIMMA
+SM_VREF_DQ0
RC173
DDR_A_D54 DDR_A_D55
DDR_CKE1_DIMMA
<8>
1
2 1
2_0402_1%
CC70 0.022U_0402_16V7K
2
RC195 24.9_0402_1%
DDR_A_MA15 DDR_A_MA14
C
DDR_A_MA11 DDR_A_MA7 DDR_A_MA6 DDR_A_MA4 DDR_A_MA2 DDR_A_MA0 M_CLK_DDR1 M_CLK_DDR#1 DDR_A_BS1 DDR_A_RAS# DDR_CS0_DIMMA# M_ODT0
M_CLK_DDR1 M_CLK_DDR#1
<8> <8>
DDR_A_BS1 DDR_A_RAS#
<8> <8>
DDR_CS0_DIMMA#
M_ODT1 1 @ RD12
+SM_VREF_CA_DIMM1 DDR_A_D5 DDR_A_D4
DDR_A_D3 DDR_A_D7
DDR3L SODIMM ODT GENERATION
+5V_ALW +1.35V_MEM
<8>
+SM_VREF_CA_DIMM
1
2
1
2
CD13 0.1U_0402_25V6
B
D
@
CD12
DDR_A_DQS#0 DDR_A_DQS0
74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204
2
2.2U_0402_6.3V6M
DDR_A_D0 DDR_A_D1
CKE1 VDD2 A15 A14 VDD4 A11 A7 VDD6 A6 A4 VDD8 A2 A0 VDD10 CK1 CK1# VDD12 BA1 RAS# VDD14 S0# ODT0 VDD16 ODT1 NC2 VDD18 VREF_CA VSS28 DQ36 DQ37 VSS30 DM4 VSS31 DQ38 DQ39 VSS33 DQ44 DQ45 VSS35 DQS#5 DQS5 VSS38 DQ46 DQ47 VSS40 DQ52 DQ53 VSS42 DM6 VSS43 DQ54 DQ55 VSS45 DQ60 DQ61 VSS47 DQS#7 DQS7 VSS50 DQ62 DQ63 VSS52 EVENT# SDA SCL VTT2
DDR_A_D45 DDR_A_D40
2 0_0402_5%
@RC279 @ RC279
2 0_0402_5%
QD1 BSS138-G_SOT23-3 1
3
R28
<8>
M_CLK_DDR0 M_CLK_DDR#0
CKE0 VDD1 NC1 BA2 VDD3 A12/BC# A9 VDD5 A8 A5 VDD7 A3 A1 VDD9 CK0 CK0# VDD11 A10/AP BA0 VDD13 WE# CAS# VDD15 A13 S1# VDD17 NCTEST VSS27 DQ32 DQ33 VSS29 DQS#4 DQS4 VSS32 DQ34 DQ35 VSS34 DQ40 DQ41 VSS36 DM5 VSS37 DQ42 DQ43 VSS39 DQ48 DQ49 VSS41 DQS#6 DQS6 VSS44 DQ50 DQ51 VSS46 DQ56 DQ57 VSS48 DM7 VSS49 DQ58 DQ59 VSS51 SA0 VDDSPD SA1 VTT1
1
1
DDR3_DRAMRST#
220K_0402_5%~D
2
1 1
CD22 330U_D3_2.5VY_R6M
2
1
CD21
2
1
10U_0603_6.3V6M CD20
2
1@
10U_0603_6.3V6M CD19
2
1
10U_0603_6.3V6M CD18
1
10U_0603_6.3V6M CD17
1@
10U_0603_6.3V6M CD16
10U_0603_6.3V6M CD15
2
10U_0603_6.3V6M CD14
10U_0603_6.3V6M
1
M_CLK_DDR0 M_CLK_DDR#0
73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 201 203
DDR_A_D27 DDR_A_D26
<19>
RC221 1.8K_0402_1%
DDR_A_D49 DDR_A_D48
+1.35V_MEM
DDR3_DRAMRST#
RC217 1.8K_0402_1%
Layout Note: Place near JDIMM1
RD3 470_0402_5%
DDR_A_D25 DDR_A_D24
1
<8>
DDR_A_D15 DDR_A_D11
2
DDR_A_D30 DDR_A_D31
DDR_A_DQS#[0..7]
+1.35V_MEM
S
<8>
DDR_A_DQS#3 DDR_A_DQS3
DDR_A_D9 DDR_A_D12 DDR_A_DQS#1 DDR_A_DQS1
CD3 0.1U_0402_25V6
All VREF traces should have 10 mil trace width
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72
1 2 G
DDR_A_D29 DDR_A_D28
VSS1 DQ4 DQ5 VSS3 DQS#0 DQS0 VSS6 DQ6 DQ7 VSS8 DQ12 DQ13 VSS10 DM1 RESET# VSS12 DQ14 DQ15 VSS14 DQ20 DQ21 VSS16 DM2 VSS17 DQ22 DQ23 VSS19 DQ28 DQ29 VSS21 DQS#3 DQS3 VSS24 DQ30 DQ31 VSS26
1
DDR_A_D14 DDR_A_D10
VREF_DQ VSS2 DQ0 DQ1 VSS4 DM0 VSS5 DQ2 DQ3 VSS7 DQ8 DQ9 VSS9 DQS#1 DQS1 VSS11 DQ10 DQ11 VSS13 DQ16 DQ17 VSS15 DQS#2 DQS2 VSS18 DQ18 DQ19 VSS20 DQ24 DQ25 VSS22 DM3 VSS23 DQ26 DQ27 VSS25
2
2
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71
1
1
CD2 0.1U_0402_25V6
2
D
CD1 2.2U_0402_6.3V6M
1
DDR_A_D13 DDR_A_D8
2-3A to 1 DIMMs/channel
CONN@
2
JDIMM1
D
2 0_0402_5%
Populate RD1, De-Populate RD7 for Intel DDR3 VREFDQ multiple methods M1 Populate RD7, De-Populate RD1 for Intel DDR3 VREFDQ multiple methods M3
1
1
1 @ RD1
2
0.675V_DDR_VTT_ON
1 1 R31 1
@R32 2M_0402_5%
DDR_A_D18 DDR_A_D19
2 M_ODT0 66.5_0402_1% 2 M_ODT1 66.5_0402_1% 2 66.5_0402_1% 2 66.5_0402_1%
R29 R30
2
+SM_VREF_DQ0_DIMM1
3
H=4mm
2
4
R33
M_ODT2
<19>
M_ODT3
<19> B
1
5
DDR_A_DQS#2 DDR_A_DQS2 +1.35V_MEM
DDR_A_D22 DDR_A_D23 DDR_A_D37 DDR_A_D32
@CD23 @ CD23 0.1U_0402_25V6 2
U5 1 <9>
2
DDR_PG_CTRL
3
DDR_A_D35 DDR_A_D39 DDR_A_D63 DDR_A_D59
NC
VCC
A Y
5
1
4
0.675V_DDR_VTT_ON
0.675V_DDR_VTT_ON
74AUP1G07GW_TSSOP5
DDR_A_DQS#7 DDR_A_DQS7 DDR_A_D56 DDR_A_D57
DDR_XDP_WAN_SMBDAT DDR_XDP_WAN_SMBCLK
<19,31,7,9> <19,31,7,9>
+0.675V_DDR_VTT
A
206
FOX_AS0A621-U4R6-7H
DELL CONFIDENTIAL/PROPRIETARY Compal Electronics, Inc. Title PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
DDRIII-SODIMM SLOT1 Size
4
3
2
Document Number
Rev 0.3
LA-9431P Date:
5
<43>
GND
Friday, May 17, 2013
Sheet 1
18
of
59
3
2
H=4mm +1.35V_MEM
+1.35V_MEM
<8>
DDR_B_DQS#[0..7] DDR_B_D[0..63]
<8>
DDR_B_DQS[0..7]
<8>
All VREF traces should have 10 mil trace width
DDR_B_D26 DDR_B_D27 DDR_B_D40 DDR_B_D41
DDR_B_MA[0..15]
DDR_B_DQS#5 DDR_B_DQS5 DDR_B_D46 DDR_B_D42
Layout Note: Place near JDIMM2
DDR_B_D56 DDR_B_D57
DDR_B_D59 DDR_B_D58
+1.35V_MEM
DDR_B_D13 DDR_B_D15 DDR_B_D25 DDR_B_D24
+SM_VREF_CA_DIMM DDR3_DRAMRST# DDR_B_D30 DDR_B_D31
1
DDR_B_D45 DDR_B_D44
DDR_B_D47 DDR_B_D43 DDR_B_D61 DDR_B_D60
2
DDR3_DRAMRST#
<18>
CAD NOTE PLACE THE CAP NEAR TO DIMM RESET PIN
DDR_B_MA3 DDR_B_MA1
+1.35V_MEM <8> <8>
2
1
2
1
2
1 + 2
<8> <8> <8> <8>
DDR_B_MA10 DDR_B_BS0
DDR_B_BS0
DDR_B_WE# DDR_B_CAS#
DDR_B_WE# DDR_B_CAS#
DDR_B_MA13 DDR_CS3_DIMMB#
DDR_CS3_DIMMB#
DDR_B_DQS#0 DDR_B_DQS0 DDR_B_D3 DDR_B_D7 B
Layout Note: Place near JDIMM2.203,204
DDR_B_D21 DDR_B_D20
DDR_B_D22 DDR_B_D23 DDR_B_D36 DDR_B_D33
+0.675V_DDR_VTT
DDR_B_DQS#4 DDR_B_DQS4
2
1
2
CD59 10U_0603_6.3V6M
2
1
CD58 10U_0603_6.3V6M
2
1
CD57 0.1U_0402_25V6
2
1
CD56 0.1U_0402_25V6
1
CD55 0.1U_0402_25V6
2
CD54 0.1U_0402_25V6
1
DDR_B_D35 DDR_B_D39 DDR_B_D52 DDR_B_D49
DDR_B_D48 DDR_B_D53 @ RD11 2 +3.3V_RUN
1 0_0402_5% 1
+3.3V_RUN 0_0402_5%
+0.675V_DDR_VTT
2
@
1
2
CD60 0.1U_0402_25V6
1
CD61 2.2U_0402_6.3V6M
A
2 @ RD10
205
G1
G2
<8> +SM_VREF_DQ1_DIMM2
DDR_B_MA11 DDR_B_MA7
RC126
DDR_B_MA6 DDR_B_MA4 DDR_B_MA2 DDR_B_MA0 M_CLK_DDR3 M_CLK_DDR#3 DDR_B_BS1 DDR_B_RAS# DDR_CS2_DIMMB# M_ODT2 M_ODT3
M_CLK_DDR3 M_CLK_DDR#3 DDR_B_BS1 DDR_B_RAS#
<8> <8>
DDR_CS2_DIMMB# M_ODT2 <18> M_ODT3
1
2
1
2_0402_1%
2
CC69 0.022U_0402_16V7K
RC128 24.9_0402_1%
+SM_VREF_CA_DIMM 1
DDR_B_D2 DDR_B_D6
C
2
<8>
<18>
+SM_VREF_CA_DIMM2 DDR_B_D5 DDR_B_D0
+SM_VREF_DQ1
1
<8> <8>
2 0_0402_5%
@ RD13
1
2
CD44 0.1U_0402_25V6
DDR_B_D4 DDR_B_D1
DDR_CKE3_DIMMB
DDR_B_MA15 DDR_B_MA14
CD43 2.2U_0402_6.3V6M
CD53 330U_D3_2.5VY_R6M
2
1
CD52 10U_0603_6.3V6M
1
CD51 10U_0603_6.3V6M
2
@
CD50 10U_0603_6.3V6M
2
1
CD49 10U_0603_6.3V6M
1
CD48 10U_0603_6.3V6M
2
@
CD47 10U_0603_6.3V6M
1
CD46 10U_0603_6.3V6M
2
CD45 10U_0603_6.3V6M
1
M_CLK_DDR2 M_CLK_DDR#2
M_CLK_DDR2 M_CLK_DDR#2
DDR_CKE3_DIMMB
RC132 1.8K_0402_1%
DDR_B_MA8 DDR_B_MA5
CKE1 VDD2 A15 A14 VDD4 A11 A7 VDD6 A6 A4 VDD8 A2 A0 VDD10 CK1 CK1# VDD12 BA1 RAS# VDD14 S0# ODT0 VDD16 ODT1 NC2 VDD18 VREF_CA VSS28 DQ36 DQ37 VSS30 DM4 VSS31 DQ38 DQ39 VSS33 DQ44 DQ45 VSS35 DQS#5 DQS5 VSS38 DQ46 DQ47 VSS40 DQ52 DQ53 VSS42 DM6 VSS43 DQ54 DQ55 VSS45 DQ60 DQ61 VSS47 DQS#7 DQS7 VSS50 DQ62 DQ63 VSS52 EVENT# SDA SCL VTT2
RC83 24.9_0402_1%
2
DDR_B_MA12 DDR_B_MA9
CKE0 VDD1 NC1 BA2 VDD3 A12/BC# A9 VDD5 A8 A5 VDD7 A3 A1 VDD9 CK0 CK0# VDD11 A10/AP BA0 VDD13 WE# CAS# VDD15 A13 S1# VDD17 NCTEST VSS27 DQ32 DQ33 VSS29 DQS#4 DQS4 VSS32 DQ34 DQ35 VSS34 DQ40 DQ41 VSS36 DM5 VSS37 DQ42 DQ43 VSS39 DQ48 DQ49 VSS41 DQS#6 DQS6 VSS44 DQ50 DQ51 VSS46 DQ56 DQ57 VSS48 DM7 VSS49 DQ58 DQ59 VSS51 SA0 VDDSPD SA1 VTT1
CC67 0.022U_0402_16V7K
+1.35V_MEM
74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204
2
DDR_B_BS2
DDR_B_BS2
2
DDR_B_D63 DDR_B_D62
1
DDR_CKE2_DIMMB <8>
1
DDR_B_DQS#7 DDR_B_DQS7
2
2
<8>
2
2_0402_1%
RC130 1.8K_0402_1%
2
1
CD42 1U_0402_6.3V6K
2
1
CD41 1U_0402_6.3V6K
2
1
CD40 1U_0402_6.3V6K
2
1
CD39 1U_0402_6.3V6K
2
1
CD38 1U_0402_6.3V6K
2
1
CD37 1U_0402_6.3V6K
2
1
CD36 1U_0402_6.3V6K
C
CD35 1U_0402_6.3V6K
1
73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 201 203
DDR_CKE2_DIMMB
D
+SM_VREF_CA
RC68 1
@
1
+1.35V_MEM
DDR_B_DQS#1 DDR_B_DQS1
RC69 1.8K_0402_1%
<8>
Note: Check voltage tolerance of VREF_DQ at the DIMM socket
Reverse Type
DDR_B_D12 DDR_B_D9
CD34 0.1U_0402_25V6
DDR_B_DQS#3 DDR_B_DQS3
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72
RC67 1.8K_0402_1%
DDR_B_D28 DDR_B_D29
VSS1 DQ4 DQ5 VSS3 DQS#0 DQS0 VSS6 DQ6 DQ7 VSS8 DQ12 DQ13 VSS10 DM1 RESET# VSS12 DQ14 DQ15 VSS14 DQ20 DQ21 VSS16 DM2 VSS17 DQ22 DQ23 VSS19 DQ28 DQ29 VSS21 DQS#3 DQS3 VSS24 DQ30 DQ31 VSS26
1
DDR_B_D10 DDR_B_D11
CONN@
2
2
DDR_B_D8 DDR_B_D14
VREF_DQ VSS2 DQ0 DQ1 VSS4 DM0 VSS5 DQ2 DQ3 VSS7 DQ8 DQ9 VSS9 DQS#1 DQS1 VSS11 DQ10 DQ11 VSS13 DQ16 DQ17 VSS15 DQS#2 DQS2 VSS18 DQ18 DQ19 VSS20 DQ24 DQ25 VSS22 DM3 VSS23 DQ26 DQ27 VSS25
1
1
CD33 0.1U_0402_25V6
D
2
CD32 2.2U_0402_6.3V6M
1
Populate RD4, De-Populate RD8 for Intel DDR3 VREFDQ multiple methods M1 Populate RD8, De-Populate RD4 for Intel DDR3 VREFDQ multiple methods M3
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71
1
JDIMM2 2 0_0402_5%
@RD7 @ RD7
2
+DIMM2_VREF_DQ 1
+SM_VREF_DQ1_DIMM2
1
2-3A to 1 DIMMs/channel
1
4
2
5
B
DDR_B_D16 DDR_B_D17 DDR_B_DQS#2 DDR_B_DQS2 DDR_B_D19 DDR_B_D18 DDR_B_D37 DDR_B_D32
DDR_B_D34 DDR_B_D38 DDR_B_D51 DDR_B_D55 DDR_B_DQS#6 DDR_B_DQS6 DDR_B_D54 DDR_B_D50
DDR_XDP_WAN_SMBDAT DDR_XDP_WAN_SMBCLK
<18,31,7,9> <18,31,7,9>
+0.675V_DDR_VTT
206 A
FOX_AS0A621-U4R6-7H
DELL CONFIDENTIAL/PROPRIETARY Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
Title
DDRIII-SODIMM SLOT2 Size
4
3
2
Rev 0.3
LA-9431P Date:
5
Document Number Friday, May 17, 2013
Sheet 1
19
of
59
5
4
3
2
1
D
D
+3.3V_ALW_PCH 0.1U_0402_25V6
@ C388 2
PLTRST_NFC# PCH_NFC_RST
1 2
TC7SH08FU_SSOP5~D
B
U29
O A
C
4
NFC_RST
G
<9> <12>
+3.3V_ALW_PCH
3
C
P
5
1
CONN@ JNFC1
@T87 @T88
1
2 NFC_DET# 100K_0402_5%
R38
<7> <7>
NFC_SMBCLK NFC_SMBDATA <12> @T89 <12>
1 @ R37
PAD~D PAD~D
TP_NFC_SWP_PWR_RSVD TP_NFC_RSVD4 NFC_RST NFC_SMBCLK NFC_SMBDATA TP_NFC_RSVD3
NFC_IRQ PAD~D NFC_DET#
2 TP_NFC_RSVD3 0_0402_5%
TP_NFC_RSVD1 NFC_DET#
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 GND GND
+3.3V_ALW_PCH
1
2
C1 0.1U_0402_16V4Z
+3.3V_ALW_PCH
@
C1 close to JNFC1 16 17
E-T_6718K-Y15N-01L
ST change to 6718K-Y15N-01L
B
B
A
A
DELL CONFIDENTIAL/PROPRIETARY PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 5
4
3
2
Compal Electronics, Inc. Title
NFC/Sensor Hub Conn Size
Document Number
Date:
Friday, May 17, 2013
Rev 0.3
LA-9431P Sheet 1
20
of
59
2
1
+1.05V_RUN_VMM
+3.3V_RUN_VMM
L4 1
2
2
B
1
2
C24 .01U_0402_16V7K
2
1
C23 .01U_0402_16V7K
2
1
C22 0.1U_0402_25V6
1
C21 1U_0603_10V6K
BLM18AG102SN1D_2P
+1.05V_VMM_VDDTX
E10 C7 C6 H11 E12 D12 J10 K8 K9 K10
+3.3V_RUN_VMM J2
L5 1
2
2
1
2
C3 C4 C11 C12 K3 K4 K11 K12 J4
C29 .01U_0402_16V7K
2
1
C28 .01U_0402_16V7K
2
1
C27 0.1U_0402_25V6
+3.3V_RUN_VDDIO
1
C26 1U_0603_10V6K
BLM18AG102SN1D_2P
1V Digital
VDDXT1V VDDLP VDDRXA0 VDDRXA1 VDDRXA2 VDDTX0A0 VDDTX0A1 VDDTX0A2 VDDTX1A0 VDDTX1A1 VDDTX1A2 VGA_AVDD VGA_AVDD VGA_AVDD VGA_AVDD
2
2
1 1
2
1
BLM18AG102SN1D_2P VMM_SPI_CS# VMM_SPI_DIN VMM_SPI_WP#
0.1U_0402_10V7K 0.1U_0402_10V7K 0.1U_0402_10V7K 0.1U_0402_10V7K 0.1U_0402_10V7K 0.1U_0402_10V7K 0.1U_0402_10V7K 0.1U_0402_10V7K 0.1U_0402_10V7K 0.1U_0402_10V7K
DP12412_P0 DP12412_N0 DP12412_P1 DP12412_N1 DP12412_P2 DP12412_N2 DP12412_P3 DP12412_N3 DP12412_AUX DP12412_AUX#
1 1 1 1 1 1 1 1 1 1
2 2 2 2 2 2 2 2 2 2
DP12412_P0_C DP12412_N0_C DP12412_P1_C DP12412_N1_C DP12412_P2_C DP12412_N2_C DP12412_P3_C DP12412_N3_C DP12412_AUX_C DP12412_AUX#_C
C155 C156 C157 C158 C159 C160 C161 C162 C19 C20 SRCDET
<27>
DP12412_HPD
DP12412_HPD
<9>
R63
8 7 6 5
CS# VCC DO(IO1) HOLD#(IO3) WP#(IO2) CLK GND DI(IO0)
VMM_SPI_HOLD VMM_SPI_CLK VMM_SPI_DO
1 1M_0402_5%
VMM_MESCL VMM_MESDA VMM_SPI_WP#
B5 B6 B1
VMM_SPI_CS# VMM_SPI_CLK VMM_SPI_DIN VMM_SPI_DO
A4 B3 B4 A3
VMM_GPIO6 VMM_GPIO7 VMM_GPIO8 VMM_GPIO9 LP_CTL
RxP0 RxN0 RxP1 RxN1 RxP2 RxN2 RxP3 RxN3 RxAUXP RXAUXN RxSRCDET RxHPD
Tx0P0 Tx0N0 Tx0P1 Tx0N1 Tx0P2 Tx0N2 Tx0P3 Tx0N3 CAD0 Tx0AUXP Tx0AUXN Tx0DDCSCL Tx0DDCSDA Tx0HPD
RSTN_IN
Tx1P0 Tx1N0 Tx1P1 Tx1N1 Tx1P2 Tx1N2 Tx1P3 Tx1N3 CAD1 Tx1AUXP Tx1AUXN Tx1DDCSCL Tx1DDCSDA Tx1HPD
MESCL MESDA ROMWP SPICS SPICLK SPIDI SPIDO
D14 D13 C14 C13 B14 B13 C1 M12 M13 L3 B2 A5
GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6/INT GPIO7/MSCL GPIO8/MSDA GPIO9 LP_CTL LP_EN
VGA_VSYNC VGA_HSYNC VGA_RP VGA_RN VGA_GP VGA_GN VGA_BP VGA_BN VGA_SCL VGA_SDA
1
+1.05V_RUN_VMM
G1 G2 F1 F2 E1 E2 D1 D2 H1 H2 C2 J1
A13
PLTRST_VMM2320#
2
2 0_0402_5%
DOCKED
DOCKED
+5V_ALW DOCKED +3.3V_RUN
3 4 5 6 7
ON1
CT1
VBIAS
GND
ON2
CT2
VIN2 VIN2
VOUT2 VOUT2 GPAD
14 13
+1.05V_RUN_VMM_U31
12
C433 1
1 C432
2 0.1U_0402_10V7K
1
2 470P_0402_50V7K
2
11 10
C394 1
9 8
2 470P_0402_50V7K
IN GND
OUT GND
4
27MHZ_12PF_X1E000021042600
SSDA SSCL
1
2
CLK_27M_IN
K1
CLK_27M_OUT
L1
TRSTN TCK TMS TMS2 TDI TDO
XIN XOUT
2
TPS22966DPUR_SON14_2X3~D 1
PJP13
R65
2
1 2.2K_0402_5%
1
B7 A7 B8 A8 B9 A9 B10 A10 A14 B11 A11 B12 VMM_DPC_CTRLCLK A12 VMM_DPC_CTRLDAT A6 E13 E14 F13 F14 G13 G14 H13 H14 M14 J13 J14 K13 L14 K14
DPC_LANE_P0 <34> DPC_LANE_N0 <34> DPC_LANE_P1 <34> DPC_LANE_N1 <34> DPC_LANE_P2 <34> DPC_LANE_N2 <34> DPC_LANE_P3 <34> DPC_LANE_N3 <34> DPC_CA_DET <24,34> SW_DPC_AUX <24> SW_DPC_AUX# <24> VMM_DPC_CTRLCLK <24> VMM_DPC_CTRLDAT <24> DPC_DOCK_HPD <34>
VMM_DPB_CTRLCLK VMM_DPB_CTRLDAT
L9 M9 M6 L6 M7 L7 M8 L8 L4 M4
VMM2310_TX2P0 VMM2310_TX2N0 VMM2310_TX2N3
M3 M5 L5
VMM2310_HDP VMM2310_AUXN VMM2310_AUXP
VMM2310_TX2N1 VMM2310_SCL VMM2310_SDA
PAD~D
A1 A2
T40 @
I2C1_SDA_VMM I2C1_SCL_VMM
M11 M10 L12 L13 L11 L10
<12> <12>
I2C debug port to VMM2320 +3.3V_RUN_VMM
1
+3.3V_RUN_VMM
R40 1
VMM_MESDA R42
1
SW_DPB_AUX# VMM_DPC_CTRLCLK 1 R49 VMM_DPC_CTRLDAT 1 R46 1 SW_DPC_AUX# R91
PAD-OPEN1x1m
XB: non Vpro use A2 part Vpro use A3 part
2 2.2K_0402_5% 2 2.2K_0402_5% 2 1M_0402_5%
R44 1
VMM_GPIO6 R52
1
VMM_GPIO7 R53
1
VMM_GPIO8 R54
SW_DPC_AUX SW_DPB_AUX LP_CTL
1 @ R207
2 100K_0402_5%
RED_DOCK GREEN_DOCK BLUE_DOCK
A
1 VMM2310_TX2N3 @ R73
2 RED_DOCK 0_0402_5%
1 VMM2310_TX2N2 @ R75
2 GREEN_DOCK 0_0402_5%
GREEN_DOCK
1 VMM2310_TX2N1 @ R76
2 BLUE_DOCK 0_0402_5%
BLUE_DOCK
RED_DOCK
B
VMM2310_TX2N2
+3.3V_RUN_VMM
C392 0.1U_0402_10V7K
DPB_LANE_P0 <34> DPB_LANE_N0 <34> DPB_LANE_P1 <34> DPB_LANE_N1 <34> DPB_LANE_P2 <34> DPB_LANE_N2 <34> DPB_LANE_P3 <34> DPB_LANE_N3 <34> DPB_CA_DET <24,34> SW_DPB_AUX <24> SW_DPB_AUX# <24> VMM_DPB_CTRLCLK <24> VMM_DPB_CTRLDAT <24> DPB_DOCK_HPD <34>
VMM_MESCL IDTVMM2320BKG8_BGA168
2
+3.3V_RUN_VMM_U31
15
2
VGA_DET VGA_IREF VGA_NC
RX_STS TX0_STS TX1_STS TX2_STS
2
2 VOUT1 VOUT1
3
C43 22P_0402_50V8J
<27,28,32,36>
VIN1 VIN1
C42 22P_0402_50V8J
1 2
R66 1M_0402_5%
Y1 1
K2 L2 M1 M2
1
1 CLK_27M_IN_R @ R107
PJP12 PAD-OPEN1x1m +1.05V_RUN U31
2
0.1U_0402_25V6
U6A <27> <27> <27> <27> <27> <27> <27> <27> <27> <27>
IDTVMM2320BKG8_BGA168 +3.3V_RUN_VDDA
1 2 3 4
EEPROM
C34 1
U7
W25X10CLSNIG _SO8
J5 J11 J12 K5 H10 J6 J7 J8 J9
VSS VSS VSS VSS VGA_AVSS VGA_AVSS VGA_AVSS VGA_AVSS VGA_AVSS
+3.3V_RUN_VMM R64 10K_0402_5%
2
G6 G7 G8 G9 G10 G11 H4 D4
VSS VSS VSS VSS VSS VSS VSS VSS
VDDSA VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDXT3V
2
F8 F9 F10 F11 G4 G5
VSS VSS VSS VSS VSS VSS
1 V Analog
J3 E5 H3 F3 D3
VDDTX0 VDDTX0 VDDTX1 VDDTX1
1
C5 D5 D6 D7 D8 D9 D10 D11 E4 E11 F4 F5 F6 F7
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
3.3V IO
2
C8 C9 F12 G12
VDDRX VDDRX
VDDRX_33 VDDTX0_33 VDDTX1_33 VGA_AVDD33 VGA_AVDD33
+3.3V_RUN_VDDA 1 1
C16 1U_0603_10V6K
2
1
C18 .01U_0402_16V7K
1
C17 0.1U_0402_25V6
2 +1.05V_RUN_VMM
C25 1U_0603_10V6K
1
VDD VDD VDD VDD VDD VDD VDD VDD
H5 C10 H12 K6 K7
C15 0.1U_0402_25V6
E3 G3
3.3V Analog
C14 .01U_0402_16V7K
2
E6 E7 E8 E9 H6 H7 H8 H9
C13 .01U_0402_16V7K
2
1
C12 .01U_0402_16V7K
2
1
C10 .01U_0402_16V7K
2
1
C11 0.1U_0402_25V6
2
1
C9 0.1U_0402_25V6
2
1
C8 1U_0603_10V6K
1
C132 10U_0603_6.3V6M
BLM18AG102SN1D_2P
+1.05V_VMM_VDD
+3.3V_RUN_VMM
L2
U6B 2
2
L1 1
1 R92 1 R47
2 1M_0402_5% 2 1M_0402_5%
1 R311 1 R312 1 R351
2 150_0402_1% 2 150_0402_1% 2 150_0402_1%
1 R69 VMM_DPB_CTRLCLK 1 R70 VMM_DPB_CTRLDAT 1 R72 SRCDET
<34>
2 2.2K_0402_5% 2 2.2K_0402_5% 2 1M_0402_5% 2 2.2K_0402_5% 2 2.2K_0402_5% 2 2.2K_0402_5% 2 1M_0402_5% 2 2.2K_0402_5% 2 2.2K_0402_5%
+3.3V_RUN_VMM
VMM2310_HDP R74
<34>
2
1 10K_0402_5%
A
<34>
1 VMM2310_SCL @ R77
2 CLK_DDC2_DOCK 0_0402_5%
1 VMM2310_SDA @ R81
2 DAT_DDC2_DOCK 0_0402_5%
VMM2310_TX2N0 1 @ R84
2 HSYNC_DOCK 0_0402_5%
HSYNC_DOCK
<34>
VMM2310_TX2P0 1 @ R88
2 VSYNC_DOCK 0_0402_5%
VSYNC_DOCK
<34>
CLK_DDC2_DOCK
<34>
DAT_DDC2_DOCK
VMM2310_AUXN 1 R85
2 3.74K_0402_1%
<34>
DELL CONFIDENTIAL/PROPRIETARY Compal Electronics, Inc. Title PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
2
1
IDT VMM2320 DP and VGA SW Size
Document Number
Date:
Friday, May 17, 2013
Rev 0.3
LA-9431P Sheet
21
of
59
5
4
3
2
1
+3.3V_TSP
2 0.1U_0603_50V7K
EMC@LE1 EMC@ LE1 1 DISP_ON
2
2
3
2
1
2
1
ESD depop location(EMC)
D
BIA_PWM BLM15BB221SN1D_2P~D
EDP_CPU_HPD LCD_TST
1
@
<12>
+BL_PWR_SRC 1 C52
<10>
<36>
+LCDVDD C54 2 C55 2 C59 2 C56 2 C60 2 C57 2
EDP_CPU_AUX#_C EDP_CPU_AUX_C EDP_CPU_LANE_P0_C EDP_CPU_LANE_N0_C EDP_CPU_LANE_P1_C EDP_CPU_LANE_N1_C
0.1U_0402_10V7K 0.1U_0402_10V7K 0.1U_0402_10V7K 0.1U_0402_10V7K 0.1U_0402_10V7K 0.1U_0402_10V7K
<12> Pin Pin Pin Pin
+3.3V_CAM
2
@ 2
Close to JEDP1.40
JLED1
+3.3V_RUN
1
@
2
Close to JEDP1.2
1 2 3 4 5 6 7 8
+5V_ALW <40> BATT_WHITE_LED# <40> BATT_YELLOW_LED# <40> PANEL_HDD_LED# <40> BREATH_WHITE_LED# <12> TOUCH_PANEL_INTR#
@
1 2 3 4 5 6 GND GND
For LCDVDD 2
1
VIN 2
D2 <36>
LCD_VCC_TEST_EN
ENVDD_PCH
2
BIA_PWM_EC
EDP_BIA_PWM
3
BIA_PWM_EC
<37>
2 R96 100K_0402_5%
1
APL3512ABI-TRG_SOT23-5
2
<10>
PANEL_BKEN_EC
<36>
BAT54CW_SOT323-3
2
2
BAT54CW_SOT323-3
4
EN
1
1
1 R95 10K_0402_5% B
PANEL_BKLEN
1
DISP_ON
5
R104 100K_0402_5%
BAT54CW_SOT323-3
<10>
3
EN_LCDPWR
3
D21
1
BIA_PWM
GND SS
1 <10,36>
EDP_BIA_PWM
VOUT
2
D10 3
+3.3V_ALW U9
1
10U_0603_6.3V6M
ACES_50450-0067N-P01 check
+LCDVDD
@ C431
@ C430 0.01U_0402_16V7K
Close to JLED1.1
CONN@
C64 0.1U_0402_25V6
2
1
C62 0.1U_0402_25V6
Close to JEDP1.33
1
+3.3V_TSP
C3 C 3 0.1U_0402_16V4Z
1
@
C
29 for cable detact GND 17 ~20 for BL_GND 3, 10 for eDP High speed GND 14,15 for LCD_GND
+5V_ALW
C68 0.1U_0402_25V6
@
EDP_CPU_AUX# <10> EDP_CPU_AUX <10> EDP_CPU_LANE_P0 <10> EDP_CPU_LANE_N0 <10> EDP_CPU_LANE_P1 <10> EDP_CPU_LANE_N1 <10>
2
LCD_CBL_DET# +3.3V_RUN
1 1 1 1 1 1
CONN@
C63 0.1U_0402_25V6
Close to 2 JEDP1.11,12
CAM_MIC_CBL_DET#
2 1K_0402_5%
@
<26>
@
IO_LOOP 1 R108
<11> <11>
D8 L30ESDL5V0C3-2_SOT23-3
USBP3_DUSBP3_D+
+LCDVDD
1
<26>
DMIC_CLK
CE2
JEDP1
DMIC0 +3.3V_CAM
100P_0402_50V8J CE1
C
USBP7USBP7+
100P_0402_50V8J
D
ACES_50398-04071-001 45 40 40 39 44 G5 39 38 43 G4 G3 38 42 37 37 36 41 G2 G1 36 35 35 34 34 33 33 32 32 31 31 30 30 29 29 28 28 27 27 26 26 25 25 24 24 23 23 22 22 21 21 20 20 19 19 18 18 17 17 16 16 15 15 14 14 13 13 12 12 11 11 10 10 9 9 8 8 7 7 6 6 5 5 4 4 3 3 2 2 1 1
B
Touch Screen Connector +3.3V_CAM
1
S
D
1 2
2 G
3
6 1
S
Q17A DMN66D0LDW-7_SOT363-6
2 G
4
D
3
S
D
2
2 G
1 2
5
A
2
4
3
2 3
USBP3_D+
<37>
EN_INVPWR
EN_INVPWR
FDC654P: P CHANNAL
DELL CONFIDENTIAL/PROPRIETARY
USBP3_D-
Panel backlight power control by EC
DLW21HN900SQ2L_4P 1 2 @ R100 0_0402_5%
5
Q17B DMN66D0LDW-7_SOT363-6
L8
1
1 @ R101
3
S
4
2
3.3V_TS_EN
G
USBP3-
<12>
S
<11>
1
1
D
2 1 47K_0402_5%
check Resistor
USBP3+
3
G
Q4 L2N7002WT1G_SC-70-3
2 0_0402_5%
change back to CCD_OFF at Goliad project <11>
+3.3V_TSP_Q 1
2
R99
EMC@
2
+3.3V_RUN Q1 LP2301ALT1G_SOT23-3
C65 0.1U_0603_50V7K
PWR_SRC_ON
1
A
1
R97 100K_0402_5%
PJP10 PAD-OPEN1x1m
D
2
+BL_PWR_SRC
C61 0.1U_0402_25V6
1 @ R106
3.3V_CAM_EN#
2
R94 10K_0402_5%
2 0_0402_5%
40mil
6 5 2 FDC654P-G_SSOT-6 1
G
1 @ R102
1
4
S
3
C66 1000P_0402_50V7K
<12>
40mil
C67 0.1U_0402_25V6
1
1
CCD_OFF
+PWR_SRC
+3.3V_RUN
Q3 LP2301ALT1G_SOT23-3
D
PJP9 PAD-OPEN1x1m
+3.3V_CAM_Q
<36>
+3.3V_RUN
Q2
2
1
+3.3V_TSP
For Webcam
Compal Electronics, Inc. PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
2 0_0402_5%
4
3
2
Title
eDP & CAM &TS Conn Size
Document Number
Date:
Friday, May 17, 2013
Rev 0.3
LA-9431P Sheet 1
22
of
59
5
4
3
2
1
EMC@ L9 EMC@L9 1 2 9NH_0402HS-9N0EJTS_5% L10 @
4
1
2
4
3
2
TMDSB_CON_CLK
3
TMDSB_CON_CLK#
DLW21SN900HQ2L-0805_4P
1
EMC@ L11 EMC@L11 1 2 9NH_0402HS-9N0EJTS_5%
D
2
1
2
L13 @
<10>
DDI1_LANE_N2
2 C209
1 TMDS_N0_C 0.1U_0402_10V7K
4
1
2
4
3
2
TMDSB_CON_P0
3
TMDSB_CON_N0
DLW21SN900HQ2L-0805_4P
1
EMC@L14 EMC@ L14 1 2 9NH_0402HS-9N0EJTS_5%
2
EMC@L15 EMC@ L15 1 2 9NH_0402HS-9N0EJTS_5%
1
2
2
U48
+VHDMI_VCC
1 GND
1
1
AP2330W-7_SC59-3
2
C
<10>
JHDMI1 CONN@
2
TMDSB_CON_P1
CPU_DPB_CTRLDAT_R CPU_DPB_CTRLCLK_R
1 TMDS_P1_C 0.1U_0402_10V7K
1
DDI1_LANE_N1
2 C270
1 TMDS_N1_C 0.1U_0402_10V7K
4
1
2
3
4
3
TMDSB_CON_N1
HDMI_CEC TMDSB_CON_CLK#
DLW21SN900HQ2L-0805_4P
1
EMC@L17 EMC@ L17 1 2 9NH_0402HS-9N0EJTS_5%
2
EMC@L18 EMC@ L18 1 2 9NH_0402HS-9N0EJTS_5%
1
2
@C278 @ C278 1.8P_0402_50V8
2 C269
2
HDMI_HPD_SINK
@C277 @ C277 1.8P_0402_50V8
DDI1_LANE_P1
1
EMI depop location(EMC)
L16 @ <10>
@
C88 10U_0603_6.3V6M
1 TMDS_P0_C 0.1U_0402_10V7K
@
C87 0.1U_0402_10V7K
2 C199
@ C276 1.8P_0402_50V8
DDI1_LANE_P2
@ C275 1.8P_0402_50V8
<10>
C333 0.1U_0402_16V4Z
EMI depop location(EMC)
EMC@L12 EMC@ L12 1 2 9NH_0402HS-9N0EJTS_5%
D
+5V_RUN
1
1 TMDS_CLK#_C 0.1U_0402_10V7K
IN
DDI1_LANE_N3
2 C191
OUT
1
@ C274 1.8P_0402_50V8
1 TMDS_CLK_C 0.1U_0402_10V7K
@ C273 1.8P_0402_50V8
2 C103
3
<10>
DDI1_LANE_P3
2
<10>
TMDSB_CON_CLK TMDSB_CON_N0 TMDSB_CON_P0 TMDSB_CON_N1 TMDSB_CON_P1 TMDSB_CON_N2
EMI depop location(EMC)
TMDSB_CON_P2
19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
HP_DET +5V DDC/CEC_GND SDA SCL Reserved CEC CKGND CK_shield GND CK+ GND D0GND D0_shield D0+ D1D1_shield D1+ D2D2_shield D2+
C
20 21 22 23
LCN_AUF05-1922S10-0019 L19 @ 2 C271
1 TMDS_P2_C 0.1U_0402_10V7K
1
<10>
DDI1_LANE_N0
2 C272
1 TMDS_N2_C 0.1U_0402_10V7K
4
1
2
4
3
2
TMDSB_CON_P2
3
TMDSB_CON_N2
DLW21SN900HQ2L-0805_4P
1
EMC@ L20 EMC@L20 1 2 9NH_0402HS-9N0EJTS_5%
2
1
2
@ C382 1.8P_0402_50V8
DDI1_LANE_P0
@ C279 1.8P_0402_50V8
<10>
EMI depop location(EMC) +3.3V_RUN
B
B
+5V_RUN HDMI_CEC
2
1 10K_0402_5%
1 1 1 1 1 1 1 1
2 2 2 2 2 2 2 2
2 +5V_HDMI_DDC 2.2K_0402_5%
CPU_DPB_CTRLDAT_R
1 R470
2 2.2K_0402_5%
G
4
3 D
CPU_DPB_CTRLDAT
S
<10>
Q120A DMN66D0LDW-7_SOT363-6
TMDS_P2_C TMDS_N2_C TMDS_P1_C TMDS_N1_C TMDS_P0_C TMDS_N0_C TMDS_CLK_C TMDS_CLK#_C
+3.3V_RUN
R465 R468 R467 R469 R462 R463 R464 R466
R460
1
470_0402_1% 470_0402_1% 470_0402_1% 470_0402_1% 470_0402_1% 470_0402_1% 470_0402_1% 470_0402_1%
2 10K_0402_5%
HDMI_OB
1
1 R471
D
S
CPU_DPB_CTRLCLK
CPU_DPB_CTRLCLK_R
5
<10>
6
2
1
G
2
Q120B DMN66D0LDW-7_SOT363-6
1
@
D
3
2
@
R472 0_0402_5%
D65 RB751VM-40TE-17_SOD323-2
+3.3V_RUN
1
@ R473
S
2 G
Q29 L2N7002WT1G_SC-70-3
G
2
A
DELL CONFIDENTIAL/PROPRIETARY
1
A
R475 1M_0402_5%
2
+3.3V_RUN
3
1
1
HDMI_HPD_SINK
D
DPB_HPD
S
<10>
R474
2 20K_0402_5%
Compal Electronics, Inc. Q121 L2N7002WT1G_SC-70-3
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
Title
HDMI Conn Size
Document Number
Rev 0.3
LA-9431P Date:
Friday, May 17, 2013
Sheet
23
of
59
5
4
3
2
1
+3.3V_RUN_VMM
AUX/DDC SW for DPB to E-DOCK
1
2 C93 0.1U_0402_25V6
U11 D
<21>
2
SW_DPB_AUX
C94 <34>
<21>
DPB_DOCK_AUX 2
SW_DPB_AUX# <34>
C95 DPB_DOCK_AUX#
1 2
1 SW_DPB_AUX_C 0.1U_0402_10V7K DPB_DOCK_AUX
BE0 A0
3
B0
4 5
1 SW_DPB_AUX#_C 0.1U_0402_10V7K DPB_DOCK_AUX#
7
A2
GND
B2
VMM_DPB_CTRLCLK
<21>
VMM_DPB_CTRLDAT
<21>
11 10
B3 BE2
B1
D
12
A3
BE1 A1
6
14 13
VCC BE3
9 8
PI3C3125LEX_TSSOP14~D
+3.3V_RUN_VMM
2
1
R60 100K_0402_5%
DPB_CA_DET
1 <21,34>
D
3
DPB_CA_DET#
S
2 G
DPB_CA_DET
Q10 BSS138W-7-F_SOT323-3
C
AUX/DDC SW for DPC to E-DOCK
C
+3.3V_RUN_VMM 1
2 C97 0.1U_0402_25V6
U13 <21>
SW_DPC_AUX <34>
<21>
SW_DPC_AUX# <34>
2 C98 DPC_DOCK_AUX 2 C99 DPC_DOCK_AUX#
1 SW_DPC_AUX_C 0.1U_0402_10V7K DPC_DOCK_AUX 1 SW_DPC_AUX#_C 0.1U_0402_10V7K DPC_DOCK_AUX#
1 2 3 4 5 6 7
B
BE0 A0
VCC BE3
B0
A3
BE1 A1
B3 BE2
B1
A2
GND
B2
14 13 12
VMM_DPC_CTRLCLK
<21>
11 10 9
VMM_DPC_CTRLDAT
<21>
8 B
PI3C3125LEX_TSSOP14~D
1
S
1 2
R56 100K_0402_5% D
3
+3.3V_RUN_VMM
DPC_CA_DET#
<21,34>
DPC_CA_DET
DPC_CA_DET
2 G
Q6 BSS138W-7-F_SOT323-3
A
A
DELL CONFIDENTIAL/PROPRIETARY 1 R120 1 R121
5
2 DPB_CA_DET 1M_0402_5% 2 DPC_CA_DET 1M_0402_5%
Compal Electronics, Inc. PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
4
3
2
Title
DP SW_DP125 Size
Document Number
Date:
Friday, May 17, 2013
Rev 0.3
LA-9431P Sheet 1
24
of
59
5
4
3
+3.3V_HDD
2
Mini mSATA H=4 1 @ R155
2 HDD_DEVSLP 10K_0402_5%
+3.3V_HDD
+3.3V_HDD JMINI3 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51
D
<29,31,36,37,9> <7>
PCH_PLTRST#_EC CLK_PCI_LPDEBUG
<6> <6>
SATA_PRX_DTX_P1_C SATA_PRX_DTX_N1_C
<6> <6>
SATA_PTX_DRX_N1_C SATA_PTX_DRX_P1_C
PCH_PLTRST#_EC 2 C108 2 C109
1 1 .01U_0402_16V7K .01U_0402_16V7K
SATA_PRX_DTX_P1 SATA_PRX_DTX_N1
C106 2 C105 2
1 .01U_0402_16V7K 1 .01U_0402_16V7K
SATA_PTX_DRX_N1 SATA_PTX_DRX_P1
+3.3V_HDD
1
2
C114 0.1U_0402_25V6
2
C113 0.1U_0402_25V6
1
1
@
<6>
HDD_DET#
HDD_DET#
53
CONN@
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52
GND1
GND2
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52
LPC_LFRAME# LPC_LAD3 LPC_LAD2 LPC_LAD1 LPC_LAD0
LPC_LFRAME# LPC_LAD3 LPC_LAD2 LPC_LAD1 LPC_LAD0
HDD_DEVSLP
D
<29,36,37,7> <29,36,37,7> <29,36,37,7> <29,36,37,7> <29,36,37,7>
HDD_DEVSLP
<12>
54
LCN_DAN08-52406-0500
C
C
Place near JMINI3
RING2 ,RING2_L AUD_HP_OUT_L ,AUD_HP_OUT_L1 AUD_HP_OUT_R ,AUD_HP_OUT_R1 SLEEVE ,EXT_MIC Trace width to 15mils.
1
+3.3V_RUN
Combo Jack
R480 10K_0402_5%
JHP1 CONN@
2 <26> <26>
B
RING2 AUD_HP_OUT_L
RING2 AUD_HP_OUT_L
@ R491 2 EMC@L51 2
7 3
1 0_0402_5% 1 BLM18AG221SN1D_2P
RING2_L AUD_HP_OUT_L1
B
1
Normal Open
5
<26> <26>
AUD_HP_OUT_R SLEEVE
AUD_HP_OUT_R SLEEVE
EMC@L52 2 2 @ R492
1 BLM18AG221SN1D_2P 1 0_0402_5%
AUD_HP_NB_SENSE
6
AUD_HP_OUT_R1 SLEEVE_L
2 4
2
3
2
3
EMC@ D32
1
1
AUD_HP_NB_SENSE
<26,36>
1
L03ESDL5V0CC3-2_SOT23-3
1
AUD_HP_NB_SENSE
R481 100K_0402_5% 2
@
EMI depop location(EMC)
EMC@ D31 L03ESDL5V0CC3-2_SOT23-3
2
EMC@ D30 L03ESDL5V0CC3-2_SOT23-3
2
@
1
C443 220P_0402_50V7K
2
@
1
C442 220P_0402_50V7K
@
1
C441 220P_0402_50V7K
2
C440 220P_0402_50V7K
1
2
3
SINGA_2SJ3080-003111F
A
A
DELL CONFIDENTIAL/PROPRIETARY Compal Electronics, Inc. Title PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 5
4
3
2
Min Card/mSATA/Combo Jack Size
Document Number
Date:
Friday, May 17, 2013
Rev 0.3
LA-9431P Sheet 1
25
of
59
1
+5V_RUN_AUDIO
9
<6>
PCH_AZ_CODEC_SDOUT
PCH_AZ_CODEC_SDOUT
<6>
PCH_AZ_CODEC_SYNC
5 10
Place R136 close to codec 1 R136
PCH_AZ_CODEC_SDIN0
<6>
6
2 33_0402_5%
8
PCH_AZ_SDIN0_R PCH_AZ_CODEC_RST#
PCH_AZ_CODEC_RST#
11
AVDD1 AVDD2/HVDD(3.3)
DVDD-IO
PVDD2 PVDD1
DVDD
Sense A Sense B LINE1-L/RING2 LINE1-R/SLEEVE LINE1-VREFO
BIT-CLK SDATA-OUT
HPOUT-L/MIC-CAP AVSS2/HPOUT-L HP-OUT-R
SYNC SDATA-IN
SPK-L+ SPK-L-
RESET#
Close to U17
EMI depop location(EMC)
<34> <34> <34>
DAI_BCLK# DAI_DO#
<34> <34>
Close to U17 pin6
16 17 18 24
19
1
BCLK: Audio serial data bus bit clock input/output LRCK: Audio serial data bus word clock input/output @ R149 33_0402_5%
<36>
AUD_NB_MUTE#
AUD_NB_MUTE# +3.3V_RUN_AUDIO
2 1
1
1
49
Place closely to Pin 13.
1
1 R152 39.2K_0402_1%
MIC1-L
CBN
1 2
1
2
1 R187 1 R197
RING2 RING2 SLEEVE
+VREFOUT
40 41
1 2 C385 10U_0603_6.3V6M 1 2 AUD_OUT_L 2 18_0402_5% AUD_OUT_R R162 1 R166 18_0402_5% INT_SPK_L+ INT_SPK_L-
44 43
INT_SPK_R+ INT_SPK_R-
31 33 32
12
AUD_PC_BEEP
2 4 46 48
1 DMIC_CLK_L EMC@ R170
37
1
35
2
2 C145 2 C146
SLEEVE
2 2.2K_0402_5%
2 2.2K_0402_5%
SLEEVE/RING2/AUD_HP_OUT_R/AUD_HP_OUT_L please keep 15mils trace AUD_HP_OUT_L AUD_HP_OUT_L <25> AUD_HP_OUT_R AUD_HP_OUT_R <25>
1 @ R194 1 @ R153 1 R147 1 R151
1 0.1U_0402_25V6 1 0.1U_0402_25V6 2 DMIC_CLK 33_0402_5%
1 @ R186 C134 2.2U_0603_6.3V6K
<25> <25>
2 10K_0402_5% 2 10K_0402_5% 2 1K_0402_5% 2 1K_0402_5%
+VREFOUT
1
SPKR
<12>
BEEP
<37>
2
DMIC_CLK <22> DMIC0 <22>
2 0_0402_5% EN_I2S_NB_CODEC#
DMIC_CLK
<36>
1
Place C134 close to Codec
MIC1-R
2 CBP/AVSS2
EAPD/PD LDO-CAP JDREF CPVEE VREF
DVSS PVSS
MIC1-VREFO AVSS1
GND
36 21 22 34 25
B
+ALC290_LDO_CAP
@
Place close to Codec place close to pin2
+ALC3226_CPVEE +ALC3226_VREF
30 26
2
1
1
2
1
2
EMI depop location(EMC) 1
2
place at Codec bottom side @ PJP4 1 2
C142 0.1U_0402_25V6 1 2
2
PAD-OPEN1x1m
3
C144 0.1U_0402_25V6
5
AUD_HP_NB_SENSE
2
D S
4
<25,36>
EMI Request(EMC) +5V_RUN_AUDIO
@
1
G
2
1
C408 10U_0603_6.3V6M
1
C137 0.1U_0402_25V6
Q20A DMN66D0LDW-7_SOT363-6
DMN66D0LDW-7_SOT363-6 Q20B
6
MONO-OUT/CBP
RING2 SLEEVE
Notes: Keep PVDD supply and speaker traces routed on the DGND plane. Keep away from AGND and other analog signals
2
C141 0.1U_0402_25V6 1 2
AUD_SENSE_A
D
G
S
1
I2S_DIN
28 29 23
ALC3226-CG_QFN48_7X7 place at AGND and DGND plane
2
I2S_LRCK
2
1
C140 10U_0603_6.3V6M
2
EMI depop location(EMC)
GPIO0/DMIC-CLK GPIO1/DMIC-DATA DMIC1/GPIO2 GPIO3
I2S_DOUT
AUD_SENSE_A AUD_SENSE_B
R39 20K_0402_1%
R150
42
I2S_SCLK
1
+VREFOUT
13 14
C138 2.2U_0603_6.3V6K
2 10K_0402_5%
7
PCBEEP
+VDDA_PVDD
C169 2.2U_0603_6.3V6K
2
1
@ C136 10P_0402_50V8J
47
SPK-R+ SPK-RI2S_MCLK
1
2
45 39
C167 0.1U_0402_25V6
@C135 @C135 0.1U_0402_10V7K
20
C410 1U_0603_10V6K
2
@ R148 47_0402_5%
2
DAI_DI
15
PCH_AZ_CODEC_BITCLK
1
PCH_AZ_CODEC_SDOUT
DAI_LRCK#
2 I2S_MCLK 22_0402_5% 2 I2S_BCLK 22_0402_5% Place R142 close to codec 2 I2S_DO 33_0402_5% 2 I2S_LRCLK 0_0402_5% 2 I2S_DI# 0_0402_5%
2
C130 22P_0402_50V8J
Close to U17 pin5
1 R137 1 R139 1 R142 1 @ R143 1 @ R144
DAI_12MHZ#
27 38
C131 1U_0603_10V4Z
<6>
B
PCH_AZ_CODEC_BITCLK
PCH_AZ_CODEC_BITCLK
DREG_OUT
@
3
<6>
2
U17
1
1
2
2
2
C122 10U_0603_6.3V6M
2
1
C123 0.1U_0402_25V6
2
2
1
@ R130 0_0805_5%
place close to pin45
C128 10U_0603_6.3V6M
1
1000P_0402_50V7K
2
C127
1
1000P_0402_50V7K
2
1000P_0402_50V7K
1
GND GND ACES_50209-0040N-001
@
C126
1000P_0402_50V7K
2
C125
C124
1
@
1
@
place close to pin39 C129 0.1U_0402_25V6
@
1
2
C116 10U_0603_6.3V6M
2
5 6
@
1
2
@ R140 0_0603_5%
+VDDA_AVDD2 C150 0.1U_0402_25V6
1
+DVDD_CORE 1
1
C117 10U_0603_6.3V6M
1 2 3 4
C121 10U_0603_6.3V6M
1 2 3 4
INT_SPKR_L+ INT_SPKR_LINT_SPKR_R+ INT_SPKR_R-
C120 0.1U_0402_25V6
BLM18PG330SN1_2P BLM18PG330SN1_2P BLM18PG330SN1_2P BLM18PG330SN1_2P
C405 1U_0603_10V6K
2 2 2 2
1
C119 0.1U_0402_25V6
1 1 1 1
+3.3V_RUN_AUDIO
CONN@ JSPK1 C118 1U_0603_10V6K
EMC@ L22 EMC@ L23 EMC@ L24 EMC@ L25
INT_SPK_L+ INT_SPK_LINT_SPK_R+ INT_SPK_R-
DVDD_IO should match with HDA Bus level
C115 0.1U_0402_25V6
+3.3V_RUN_AUDIO
40 mils trace keep 10 mil spacing
+5V_RUN_AUDIO
1 2 PBY160808T-600Y-N_2P place close to pin38
+VDDA_AVDD1
2
Internal Speakers Header
+3.3V_RUN_AUDIO
L21
1
place close to pin27
2
2
SLEEVE
PJP24 PAD-OPEN1x1m
+RTC_CELL
Add for solve pop noise and detect issue
1 2 3
6
4
S
S
G
1
D
D
2
Q21B DMN66D0LDW-7_SOT363-6
G
DOCK_HP_DET
5
DOCK_MIC_DET
DMN66D0LDW-7_SOT363-6 Q123B 1 6
1
1
R159 100K_0402_5%
2
2
2
1
+3.3V_RUN_AUDIO
S
R157 20K_0402_1%
D
<36>
RUN_ON
2 0_0402_5%
3 4 5 6 7
2
1 @ R213
VIN1 VIN1 ON1 VBIAS
VOUT1 VOUT1 CT1 GND
ON2
CT2
VIN2 VIN2
VOUT2 VOUT2
2 PCH_AZ_CODEC_RST# 0_0402_5%
GPAD
2
1 2
+3.3V_ALW G
R156 39.2K_0402_1% R158 100K_0402_5%
5
<36,37,39>
1 @ R154
+5V_ALW
S
+3.3V_RUN_AUDIO
2
DMN66D0LDW-7_SOT363-6 Q123A 4 3
D
AUD_SENSE_B
G
Place closely to Pin 14
R202 100K_0402_5%
1
U18 A
14 13
2 0.1U_0402_10V7K A
C147 1
2 470P_0402_50V7K
10
C148 1
2 1000P_0402_50V7K
9 8
+3.3V_RUN_AUDIO_U18
11
2 1
15
TPS22966DPUR_SON14_2X3~D
1 @ R220
1 @ C188
+5V_RUN_AUDIO_U18
12
2
2 AUD_NB_MUTE# 0_0402_5%
1
+3.3V_RUN_AUDIO
PJP25 PAD-OPEN1x1m @ C139 0.1U_0402_10V7K
Realtek feedback Prevent the Noise from Combo Jack while system entry into S3 / S4 /S
DELL CONFIDENTIAL/PROPRIETARY
<36>
Compal Electronics, Inc.
Q21A DMN66D0LDW-7_SOT363-6 PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
2
1
Title
Azalia (HD) Codec-ALC3226 Size
Document Number
Date:
Friday, May 17, 2013
Rev 0.3
LA-9431P Sheet
26
of
59
5
4
3
2
1
D
D
XB use SA00006ZP00 (S IC AP2337SA-7 SOT-23 3P LOAD SWITCH) +3.3V_RUN
2 R167 1 R168
<10> <10>
CPU_DPC_AUX# CPU_DPC_AUX
<10>
DOCKED
DPC_HPD
2
C451 0.1U_0402_25V6
1
@
ESD solution for black screen issue
13 14 5 18 1 17 22 43
GPU_SEL D0D0+ D1D1+ D2D2+ D3D3+
D0-B D0+B D1-B D1+B D2-B D2+B D3-B D3+B AUX-B AUX+B HPD_B
AUXAUX+ AUX_HPD_SEL HPD GND GND GND HGND
OE
1 1 1 1 1 1 1 1
2 2 2 2 2 2 2 2
0.1U_0402_10V7K 0.1U_0402_10V7K 0.1U_0402_10V7K 0.1U_0402_10V7K 0.1U_0402_10V7K 0.1U_0402_10V7K 0.1U_0402_10V7K 0.1U_0402_10V7K
mDP_LANE_N0_C mDP_LANE_P0_C mDP_LANE_N1_C mDP_LANE_P1_C mDP_LANE_N2_C mDP_LANE_P2_C mDP_LANE_N3_C mDP_LANE_P3_C
Dock
0
mini DP
DP12412_N0 DP12412_P0 DP12412_N1 DP12412_P1 DP12412_N2 DP12412_P2 DP12412_N3 DP12412_P3 DP12412_AUX# DP12412_AUX DP12412_HPD
25
2 R161
1 4.7K_0402_5%
<21> <21> <21> <21> <21> <21> <21> <21> <21> <21> <21>
JmDP1 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
mDP_AUX#_C mDP_LANE_N2_C mDP_AUX_C mDP_LANE_P2_C
+3.3V_RUN
mDP_LANE_N3_C mDP_LANE_N1_C mDP_LANE_P3_C mDP_LANE_P1_C DPB_MB_P14 mDP_LANE_N0_C mDP_CA_DET mDP_LANE_P0_C mDP_HPD
+3.3V_RUN 1
1
2
B
AUX/DDC SW for DPC to Mini DP
C
+VDISPLAY_VCC
1
33 32 31 30 29 28 27 26 19 20 15
function
1
U50
AP2337SA-7 SOT-23
PI3VDP12412ZHEX_TQFN42_9X3P5~D
DOCKED
2
OUT
2 3 4 6 7 8 9 10 11
D0-A D0+A D1-A D1+A D2-A D2+A D3-A D3+A AUX-A AUX+A HPD_A
C163 C164 C165 C166 C168 C170 C172 C173
GND
DOCKED
DOCKED DDI2_LANE_N0 DDI2_LANE_P0 DDI2_LANE_N1 DDI2_LANE_P1 DDI2_LANE_N2 DDI2_LANE_P2 DDI2_LANE_N3 DDI2_LANE_P3
VDD VDD VDD
mDP_LANE_N0 mDP_LANE_P0 mDP_LANE_N1 mDP_LANE_P1 mDP_LANE_N2 mDP_LANE_P2 mDP_LANE_N3 mDP_LANE_P3 mDP_AUX# mDP_AUX mDP_HPD
2 C411 0.1U_0402_25V6
C174 0.1U_0402_10V7K 2 1 mDP_AUX SW_mDP_AUX_C mDP_AUX_C 2 mDP_AUX# C175
1 SW_mDP_AUX#_C 0.1U_0402_10V7K mDP_AUX#_C
C171 .01U_0402_16V7K
1 R165
<21,28,32,36> <10> <10> <10> <10> <10> <10> <10> <10>
2 mDP_HPD 100K_0402_5% 2 mDP_AUX_C 100K_0402_5% 1 mDP_CA_DET 1M_0402_5% 2 DPB_MB_P14 5.1M_0402_5%
2
42 41 40 39 38 37 36 35 24 23 16
3
1 R164
2
U19 12 21 34
1
2
C
2
@
1
C154 0.1U_0402_25V6
2 mDP_AUX#_C 100K_0402_5%
1
C153 0.1U_0402_25V6
2 1 R163
1
C152 0.1U_0402_25V6
1
C151 4.7U_0603_6.3V6K
+3.3V_RUN
IN
@
C383 0.1U_0402_16V4Z
+3.3V_RUN
CONN@
DP_PWR GND AUX_CH_N LANE2_N AUX_CH_P LANE2_P GND GND LANE3_N LANE1_N LANE3_P LANE1_P GND GND CONFIG2 LANE0_N CONFIG1 LANE0_P HOT-PLUG GND
GND4 GND3 GND2 GND1
24 23 22 21
B
ACON_MAR2C-20K1800
U49 1 2
BE0 A0
3
VCC BE3
B0
4 5
A3
BE1 A1
6 7
B3 BE2
B1
A2
GND
B2
14 13 12
CPU_DPC_CTRLCLK
<10>
11 10 9
CPU_DPC_CTRLDAT
<10>
8
PI3C3125LEX_TSSOP14~D
D
1 2
R67 100K_0402_5%
1
+3.3V_RUN
A
A
mDP_CA_DET#
2 G
5
DELL CONFIDENTIAL/PROPRIETARY Compal Electronics, Inc.
Q31 BSS138W-7-F_SOT323-3 3
mDP_CA_DET
Title
S PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 4
3
2
mDP/DP12412 Size
Document Number
Date:
Friday, May 17, 2013
Rev 0.3
LA-9431P Sheet 1
27
of
59
5
4
3
2
1
+3.3V_RUN
<11>
PCIE_PTX_GLANRX_P3
<11>
PCIE_PTX_GLANRX_N3 <7>
LAN_SMBCLK
2
LAN_WAKE#
28 31 2 3
MDI_PLUS3 MDI_MINUS3
SMB_CLK SMB_DATA LANWAKE_N LAN_DISABLE_N
LOM_ACTLED_YEL# LOM_SPD100LED_ORG# LOM_SPD10LED_GRN#
2 0_0402_5%
26 27 25
LED0 LED1 LED2
RES_BIAS
1
1
1 2
2
25MHZ_18PF_7V25000034
1
2
2
GND
LAN_TEST_EN
30 12
JTAG_TDI JTAG_TDO JTAG_TMS JTAG_TCK
VDD3P3_15 VDD3P3_19 VDD3P3_29
XTAL_OUT XTAL_IN
20 21
LAN_TX2+ LAN_TX2-
23 24
LAN_TX3+ LAN_TX3-
6
VCT_LAN_R1
1
+RSVD_VCC3P3_1
5
2
D
+0.9V_LAN @ R175 2
1 0_0402_5%
R178 2
VDD0P9_43 VDD0P9_11 VDD0P9_40 VDD0P9_22 VDD0P9_16 VDD0P9_8
Pin 6 is SVR_EN in Clarkville
1 4.7K_0402_5%
+3.3V_LAN 1
reference INTEL r217 circuit version1.7
4
2 @ R181
+3.3V_LAN_OUT
15 19 29
1 +0.9V_LAN
47 46 37
1 0_0603_5%
+3.3V_LAN
2
1
2
1
2
1
2
1
2
Note: +1.0V_LAN will work at 0.95V to 1.15V
43 11 40 22 16 8
+3.3V_LAN
TEST_EN RBIAS
2
Place C117, C180 and L26 close to U21
2
PJP20 PAD-OPEN1x1m
+3.3V_ALW CTRL0P9 VSS_EPAD
R185 3.01K_0402_1%
GND
1
R184 1K_0402_5%
2
IN
C190 33P_0402_50V8J
C189 33P_0402_50V8J
4
OUT
9 10
XTALO XTALI
2
3
32 34 33 35
TP_LAN_JTAG_TDI TP_LAN_JTAG_TDO TP_LAN_JTAG_TMS TP_LAN_JTAG_TCK
R206 1M_0402_5% Y3
C
VDD3P3_IN
VDD0P9_47 VDD0P9_46 VDD0P9_37
JTAG
PAD~D PAD~D
1
1 @ R183
RSVD_VCC3P3_1
LAN_DISABLE#_R
Pin 2 is WAKE_EN in Clarkville
@ T92 @ T93
XTALO_R
SVR_EN_N
VDD3P3_4
2
TP_LAN_JTAG_TMS 10K_0402_5% 2 TP_LAN_JTAG_TCK 10K_0402_5% 1 LAN_WAKE#_R 4.7K_0402_5%
PERp PERn
MDI_PLUS2 MDI_MINUS2
LAN_TX1+ LAN_TX1-
C182 1U_0603_10V6K
2
<36>
@ R182 10K_0402_5%
1
SMBus Device Address 0xC8
PETp PETn
17 18
C187 22U_0805_6.3V6M
LAN_SMBDATA
41 42
MDI_PLUS1 MDI_MINUS1
C186 0.1U_0402_10V7K
<7> <12,37>
38 39
MDI_PLUS0 MDI_MINUS0
PE_CLKP PE_CLKN
C185 0.1U_0402_10V7K
2 0_0402_5%
2 C179 2 C176 1 C178 1 C181 1 @ R174 1 @ R177 1 @ R179
CLK_REQ_N PE_RST_N
1
PCIE_PRX_GLANTX_N3
44 45
1
7
REGCTL_PNP10
C
49
U22 1 2
WGI218LM-SLK3A-B1_QFN48_6X6~D <36,9>
SIO_SLP_LAN#
2 @ R196
1 0_0402_5%
3 4
+5V_ALW <36>
MCARD_WWAN_PWREN
VOUT1 VOUT1
ON1
CT1
VBIAS
5
MCARD_WWAN_PWREN
VIN1 VIN1
6 7
GND
ON2
CT2
VIN2 VIN2
VOUT2 VOUT2 GPAD
1 R50
LAN ANALOG SWITCH
2
MCARD_WWAN_PWREN 100K_0402_5%
2
<11>
CLK_PCIE_LAN CLK_PCIE_LAN# 1 PCIE_PRX_GLANTX_P3_C 0.1U_0402_10V7K 1 PCIE_PRX_GLANTX_N3_C 0.1U_0402_10V7K 2 PCIE_PTX_GLANRX_P3_C 0.1U_0402_10V7K 2 PCIE_PTX_GLANRX_N3_C 0.1U_0402_10V7K 2 LAN_SMBCLK_R 0_0402_5% 2 LAN_SMBDATA_R 0_0402_5% 2 LAN_WAKE#_R 0_0402_5% LAN_DISABLE#_R
LAN_TX0+ LAN_TX0-
C184 0.1U_0402_10V7K
1 @ R180
+3.3V_LAN 1 @ R171 1 @ R172 2 @ R176
1 13 14
C183 0.1U_0402_10V7K
PM_LANPHY_ENABLE
@ R173 10K_0402_5%
1
+3.3V_LAN
CLK_PCIE_LAN CLK_PCIE_LAN# PCIE_PRX_GLANTX_P3
48 36
MDI
2
2 0_0402_5%
LANCLK_REQ#
<7> <7> <11>
2 LANCLK_REQ#_R 0_0402_5% PLT_LAN_RST#
PCIE
1 3
1 @ R145
<10,7>
@
1 @ R169
SMBUS
PLT_LAN_RST#
LED
4
D
<12>
L26
P
1
5 A
TC7SH08FU_SSOP5~D
2
U21
G
O
2
PLTRST_LAN#
1
REGCTL_PNP10 4.7UH_CBC2012T4R7M_20%
C180 10U_0603_6.3V6M
B
@
R25 100K_0402_5%
<9>
1
LAN_RST#
U20
XB use SA000066W3L(S IC WGI218LM SLK3A B1 QFN 48P PHY )
C177 0.1U_0402_10V7K
<12>
2 1 @ C406 0.1U_0402_10V7K
R331 10K_0402_5%
2
+0.9V_LAN
14 13
1 C426
+3.3V_LAN_U22
12
1
2 470P_0402_50V7K
1
2 470P_0402_50V7K
C407
2 0.1U_0402_10V7K
11 10 C427 9 8
2
+3.3V_mSATA_WWAN_U22
15
1 +3.3V_mSATA_WWAN
1 PJP21
TPS22966DPUR_SON14_2X3~D 2
PAD-OPEN1x1m
@ C425 0.1U_0402_10V7K
+3.3V_LAN
LOM_ACTLED_YEL# LOM_SPD100LED_ORG# LOM_SPD10LED_GRN#
13 15 16 42 5
DOCKED
1: TO DOCK
43
A3+
C0+ C0-
A3-
C1+ C1-
SEL
C2+ C2-
LEDA0 LEDA1 LEDA2
C3+ C3LEDC0 LEDC1 LEDC2
PD
17 18 41
LOM_SPD10LED_GRN#
2
SW_ACTLED_YEL# SW_100_ORG# SW_10_GRN#
36 35
DOCK_LOM_TRD0+ DOCK_LOM_TRD0-
32 31
DOCK_LOM_TRD1+ DOCK_LOM_TRD1-
27 26
DOCK_LOM_TRD2+ DOCK_LOM_TRD2-
23 22
DOCK_LOM_TRD3+ DOCK_LOM_TRD3-
19 20 40
<35> <35>
1
DOCK_LOM_ACTLED_YEL# DOCK_LOM_SPD100LED_ORG# DOCK_LOM_SPD10LED_GRN#
B
0.1U_0402_10V7K
O A
DOCK_LOM_TRD0+ DOCK_LOM_TRD0-
<34> <34>
DOCK_LOM_TRD1+ DOCK_LOM_TRD1-
<34> <34>
DOCK_LOM_TRD2+ DOCK_LOM_TRD2-
<34> <34>
DOCK_LOM_TRD3+ DOCK_LOM_TRD3-
<34> <34>
DOCK_LOM_ACTLED_YEL# DOCK_LOM_SPD100LED_ORG# DOCK_LOM_SPD10LED_GRN#
SW_ACTLED_YEL#
Q32B DMN66D0LDW-7_SOT363-6 1 6 LAN_ACTLED_YEL#
4
WLAN_LAN_DISB#
<36>
U24 NL17SZ08DFT2G_SSOP5~D
LAN_ACTLED_YEL#
<35>
MASK_BASE_LEDS#
<40>
SW_10_GRN#
Q33B DMN66D0LDW-7_SOT363-6 1 6 LED_10_GRN# D
12
LEDB0 LEDB1 LEDB2
SW_LAN_TX3+ SW_LAN_TX3-
LOM_SPD100LED_ORG#
S
DOCKED
11
A2-
SW_LAN_TX3+ SW_LAN_TX3-
<35> <35>
MASK_BASE_LEDS# <34> <34> <34>
PAD_GND SW_100_ORG#
LED_10_GRN#
<35>
G
DOCKED
LAN_TX3+R 12NH_0603CS-120EJTS_5% LAN_TX3-R 12NH_0603CS-120EJTS_5%
A2+
25 24
SW_LAN_TX2+ SW_LAN_TX2-
B
@ C198 1 2
2
<21,27,32,36>
2
9 10
B3+ B3-
SW_LAN_TX2+ SW_LAN_TX2-
<35> <35>
MASK_BASE_LEDS# Q33A DMN66D0LDW-7_SOT363-6 4 3
Q32A DMN66D0LDW-7_SOT363-6 4 3 LED_100_ORG#
LED_100_ORG#
<35>
G
5
0: TO RJ45
D
2
LAN_TX2+R 12NH_0603CS-120EJTS_5% LAN_TX2-R 12NH_0603CS-120EJTS_5%
A1-
29 28
SW_LAN_TX1+ SW_LAN_TX1-
+3.3V_LAN
S
1 LAN_TX3+ EMC@ L33 1 LAN_TX3EMC@ L34
2
B2+ B2-
<35> <35>
G
2
A1+
SW_LAN_TX0+ SW_LAN_TX0-
5
1 LAN_TX2+ EMC@ L31 1 LAN_TX2EMC@ L32
7
A0-
SW_LAN_TX1+ SW_LAN_TX1-
P
6
LAN_TX1+R 12NH_0603CS-120EJTS_5% 2 LAN_TX1-R 12NH_0603CS-120EJTS_5%
SW_LAN_TX0+ SW_LAN_TX0-
34 33
G
2
B1+ B1-
38 37
3
1 LAN_TX1+ EMC@ L29 1 LAN_TX1EMC@ L30
3
B0+ B0-
A0+
D
2
S
LAN_TX0+R 12NH_0603CS-120EJTS_5% 2 LAN_TX0-R 12NH_0603CS-120EJTS_5%
G
2
2
1 LAN_TX0+ EMC@ L27 1 LAN_TX0EMC@ L28
D
VDD VDD VDD VDD VDD VDD VDD
U23
B
S
2
39 30 21 14 8 4 1
2
1
C194 0.1U_0402_25V6
1
C193 0.1U_0402_25V6
2
Layout Notice : Place bead as close PI3L500 as possible
C192 0.1U_0402_25V6
1
A
A
5
PI3L720ZHEX_TQFN42_9X3P5~D
MASK_BASE_LEDS#
DELL CONFIDENTIAL/PROPRIETARY PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 5
4
3
2
Compal Electronics, Inc. Title
LAN Lewisville / LAN SW Size
Document Number
Date:
Friday, May 17, 2013
Rev 0.3
LA-9431P Sheet 1
28
of
59
5
4
3
2
1
D
D
+3.3V_RUN
+3.3V_RUN_TPM @ PJP5 1
2 +3.3V_RUN_TPM
PAD-OPEN1x1m
28 26 23 20 17
LPCPD#
V_BAT NBO_13 NBO_14
LAD0 LAD1 LAD2 LAD3
GPIO6 <7> CLK_PCI_TPM_TCM <25,36,37,7> LPC_LFRAME# <25,31,36,37,9> PCH_PLTRST#_EC <12,36,37> IRQ_SERIRQ <10,36,37,9> CLKRUN#
LPC_LFRAME# IRQ_SERIRQ CLKRUN#
21 22 16 27 15
LCLK LFRAME# LRESET# SERIRQ CLKRUN#
TESTBI TESTI
ATEST_1 ATEST_2 ATEST_3
GND_4 GND_11 GND_18 GND_25
2
2
2
USH board conn
2 USH_SMBCLK 2.2K_0402_5% 2 USH_SMBDAT 2.2K_0402_5% 2 USH_PWR_STATE# 1M_0402_5% <11> <11> <37> <37> <36>
12 13 14
CONN@ JUSH1 USBP4USBP4+
USH_SMBCLK USH_SMBDAT BCM5882_ALERT#
USH_SMBCLK USH_SMBDAT
+3.3V_SUS 6 +3.3V_RUN +5V_RUN
9 8
<36> <10> NC_7
1 2 3
@
1 R190 1 R191 1 R195
<9> PLTRST_USH# USH_PWR_STATE# CONTACTLESS_DET#
7 <12>
4 11 18 25
USH_DET#
USH_PWR_STATE#
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
+5V_RUN
1
2
@
+3.3V_RUN +3.3V_SUS
1
2
@
1
2
C206 0.1U_0402_25V6
LPC_LAD0 LPC_LAD1 LPC_LAD2 LPC_LAD3
2 SP_TPM_LPC_EN_R 0_0402_5% LPC_LAD0 LPC_LAD1 LPC_LAD2 LPC_LAD3
2
1
C207 0.1U_0402_25V6
<25,36,37,7> <25,36,37,7> <25,36,37,7> <25,36,37,7>
2 10_0402_5%
10 19 24
1
C208 0.1U_0402_25V6
1 @ R193
VCC_0 VCC_1 VCC_2
SB3V
1
C204 0.1U_0402_25V6
SP_TPM_LPC_EN
5
1
C384 2200P_0402_50V7K
C
PCH_TPM_LPC_EN 1 @ R198
2
U25
C202 2200P_0402_50V7K
<36>
PCH_TPM_LPC_EN
1
C203 2200P_0402_50V7K
<7>
@
C201 4700P_0402_25V7K
2
C200 0.1U_0402_25V6
1
+3.3V_SUS
+3.3V_RUN_TPM
ATMEL TPM for E4
@
C
GND GND
21 22
E-T_6718K-Y20N-00L
AT97SC3204-X4A12-ABF _TSSOP28
ST change to 6718K-Y20N-00L
XB use SA00004WQ50(S IC AT97SC3204-X4A12-ABF TSSOP 28P TPM)
B
B
A
A
DELL CONFIDENTIAL/PROPRIETARY Compal Electronics, Inc. PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
USH board conn / TPM Size
Document Number
Date:
Friday, May 17, 2013
Rev 0.3
LA-9431P Sheet 1
29
of
59
A
B
C
D
E
+3.3V_RUN
<11> <11>
PCIE_PRX_MMITX_P5 PCIE_PRX_MMITX_N5 <7> <7>
<7>
2
2 1
R205 2 0.1U_0402_10V7K 2 0.1U_0402_10V7K
2 PE_REXT 191_0402_1% PCIE_PTX_MMIRX_P5_C PCIE_PTX_MMIRX_N5_C
4
C235 1 C236 1 C237 1 C238 1
2 0.1U_0402_10V7K 2 0.1U_0402_10V7K
PCIE_PRX_MMITX_P5_C PCIE_PRX_MMITX_N5_C
7 8
6 5
2 3
CLK_PCIE_MMI# CLK_PCIE_MMI
15 14
MEDIACARD_PWREN
<12>
AUX _33VIN
SD_SKT_33VOUT
MAIN_LDO_VIN
SD_SKT_18VOUT
22
+3.3V_RUN_CARD
24
+1.8V_RUN_CARD
2
2 1
SD_SKT_33VIN
1
2
SD_33VCCD
@
2
1
4
SD/MMCDAT1
1
4
3
1
2
16
MEDIACARD_IRQ#
17
MMICLK_REQ#
18
IO_LDOSEL
3
SD/MMCDAT0_D
2
DLW21SN900SQ2L-0805_4P 1
SD/MMCDAT1_D
2
@ R297
0_0402_5%
MAIN_LDO_12VOUT CORE_12VCCD SD_WPI SD_CD#
UHSII_12VCCAIN/NC UHSII_12VCCAIN/NC UHSII_12VCCAIN/NC
SD_CLK SD_CMD
PE_12VCCAIN MMC_D7 MMC_D6 MMC_D5 MMC_D4 SD_D3 SD_D2 SD_D1 SD_D0
PE_REXT PE_RXP PE_RXM PE_TXP PE_TXM
SD_RCLK_M/NC SD_RCLK_P/NC SD_D1P/NC SD_D1M/NC SD_D0M/NC SD_D0P/NC
PE_REFCLKM PE_REFCLKP PE_RST#_GATE# MAIN_LDO_EN
SD_REXT/NC
20 21
SDWP SD/MMCCD#
43 45
SD/MMCCLK_R SD/MMCCMD
39 40 44 46 47 48 37 38
EMC@ R230 1
2 10_0402_5%
2 0_0402_5% 2 0_0402_5%
SD/MMCDAT3_R SD/MMCDAT2_R
2
SD_UHS2_D1P SD_UHS2_D1N SD_UHS2_D0N SD_UHS2_D0P R211 1
SD_UHS2_D0N
1
4
3
1
2
3
SD_UHS2_D0P_D
2
SD_UHS2_D0N_D 2
DLW21SN900SQ2L-0805_4P 1
2
@ R315
0_0402_5%
@ R333 1
EMI depop location(EMC)
29 30 32 33 34 35 26
@ R410 1 @ R341 1
4
SD/MMCCLK
1
SD/MMCDAT3 SD/MMCDAT2 SD/MMCDAT1 SD/MMCDAT0
2 0_0402_5%
L47 @ SD_UHS2_D0P
@
2 1
2 1
2 1
36 31 28
PE_RST# <11,12>
2 0_0402_5%
L46 @ SD/MMCDAT0
C255 5P_0402_50V8C
PCIE_PTX_MMIRX_P5 PCIE_PTX_MMIRX_N5
@ R231 1
1
2 1
2 1
2 1
2 2 1
1
41
1 <11> <11>
+SD_IO_LDO
1
C228 C229 near U27.24
@ R306 1
C234 0.1U_0402_25V6
C233 0.1U_0402_25V6
C232 0.1U_0402_25V6
C231 0.1U_0402_25V6
2
+1.2V_LDO_AIN C230 4.7U_0603_6.3V6K
2
1
1
1 2
1 2
1 2
1
1 2
1 2
2
1
2
2 1
1
10
+AUX_LDO
25
C222 1U_0402_6.3V6K
11
12
C221 4.7U_0603_6.3V6K
23
L36
@
AUX_LDO_CAP
UHSII_33VCCAIN/NC SD_IO_LDO_CAP
42
13
1 2 BLM15AG601SN1D_2P
OZ777FJ2LN
PE_33VCCAIN
C216 0.1U_0402_25V6
C226 0.1U_0402_25V6
C225 4.7U_0603_6.3V6K
C219 0.1U_0402_25V6
C224 4.7U_0603_6.3V6K
1
9 27
@
please routing daisy chain 1. from U27.38 (SD_D0) -> U27.32 (SD_RCLK_P) -> L46.4 2. From U27.37 (SD_D1) -> U27.33 (SD_RCLK_N) -> L46.1
C220 4.7U_0603_6.3V6K
C218 0.1U_0402_25V6
C217 0.1U_0402_25V6
C223 4.7U_0603_6.3V6K
2
U27
@
C228 4.7U_0603_6.3V6K
homestay ES1(no SD4.0) SSI ES2(symbol should be update 26~36 pin swap)
use 3.3V
+1.2V_LDO
@
C227 near U27.22
+3.3V_RUN
C229 0.1U_0402_25V6
C215 0.1U_0402_25V6
+1.2V_LDO
C214 0.1U_0402_25V6
C210 close to U27.42 C211 C212 close to U27.23
+3.3V_RUN_AIN C213 4.7U_0603_6.3V6K
C212 0.1U_0402_25V6
C211 4.7U_0603_6.3V6K
C210 0.1U_0402_25V6
1
C227 0.1U_0402_25V6
L35
1 2 BLM15AG601SN1D_2P
+1.8V_RUN_CARD
1
+3.3V_RUN_CARD C215 close to U27.9 C213 C214 close to U27.35
2
+3.3V_RUN
2 0_0402_5%
L48 @ SD_UHS2_D1P
1
SD_UHS2_D1N
4
1
2
4
3
2
SD_UHS2_D1P_D
3
SD_UHS2_D1N_D
DLW21SN900SQ2L-0805_4P
2 4.7K_0402_1%
1
2
@ R337
0_0402_5%
DEV_WAKE# CLKREQ#
LED#
IO0_LDOSEL
GND
19 49
OZ777FJ2LN_QFN48_6X6 MMC+ need confirm
Near to JSD1 3
@ R443 1
+3.3V_RUN_CARD +1.8V_RUN_CARD
+3.3V_RUN_CARD
2 0_0402_5%
JSD1 CONN@ SD/MMCCMD SD/MMCCLK
4 14 2 5
SD/MMCCD# SDWP
18 19
SD/MMCDAT0_D SD/MMCDAT1_D SD/MMCDAT2_R SD/MMCDAT3_R SD_UHS2_D0P_D SD_UHS2_D0N_D SD_UHS2_D1P_D SD_UHS2_D1N_D
7 8 9 1 11 12 16 15
+3.3V_RUN
5
1
1
3
TC7SH08FU_SSOP5~D
2
1
2
@
3 6 10 13 17
+1.8V_RUN_CARD
2
2
@ R214 100K_0402_5%
2
1
PE_RST#
G
A
4
2
2
O
R493
MEDIACARD_RST#
B
R27 100K_0402_5%
<12> IO_LDOSEL
1
PLTRST_MMI#
@
1M_0402_5%
<9>
1
SD/MMCCD# C256 0.1U_0402_25V6
R212 100K_0402_5%
1
@U26 @ U26
P
1
@ C341 @C341 2
C240 4.7U_0603_6.3V6K
1
C239 0.1U_0402_25V6
0.1U_0402_25V6
2
+3.3V_RUN
O2 request 1
2
3
CARD DETECT WRITE PROTEC DAT0/RCLK+ DAT1/RCLKDAT2 CD/DAT3 D0+ DOD1+ D1VSS1 VSS2 VSS3 VSS4 VSS5
GND1 GND2 GND3 GND4 GND5 GND6 GND7
20 21 22 23 24 25 26
ALPS_SCDADA0101_NR
C247 4.7U_0603_6.3V6K
2
C246 0.1U_0402_25V6
1
VDD/VDD1 VDD2 CMD CLK
4
4
DELL CONFIDENTIAL/PROPRIETARY Compal Electronics, Inc. Title PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. A
B
C
D
Card Reader OZ777FJ2 Size
Document Number
Date:
Friday, May 17, 2013
Rev 0.3
LA-9431P Sheet E
30
of
59
5
4
3
2
1
+3.3V_WLAN
<6> <6>
SATA_PRX_mSATATX_P3 SATA_PRX_mSATATX_N3
<6> <6>
3@ C244 1 SATA_PTX_mSATARX_N3 1 SATA_PTX_mSATARX_P3 C245 3@
<36>
2 2
0.1U_0402_10V7K SATA_PTX_mSATARX_N3_C SATA_PTX_mSATARX_P3_C 0.1U_0402_10V7K
HW_GPS_DISABLE2#
53
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52
GND1
+3.3V_mSATA_WWAN
1
+3.3V_WLAN
GND2
JMINI1 PCIE_WAKE# +SIM_PWR
UIM_DATA UIM_CLK UIM_RESET UIM_VPP
WWAN_RADIO_DIS#
MINI_CARD_RST#
<36>
MINI2CLK_REQ#
<7> <7>
CLK_PCIE_MINI2# CLK_PCIE_MINI2
<36,37> <11> <11>
WWAN_SMBCLK WWAN_SMBDAT USBP6USBP6+
<7>
<11> <11>
<11> <11>
EC5048_TX <37> MSCLK PCIE_PRX_WLANTX_N4 PCIE_PRX_WLANTX_P4
PCIE_PTX_WLANRX_N4 PCIE_PTX_WLANRX_P4 <12>
LED_WWAN_OUT# mSATA_DEVSLP
mSATA_DEVSLP
C242 1 1 C243
0.1U_0402_10V7K 2PCIE_PTX_WLANRX_N4_C 2PCIE_PTX_WLANRX_P4_C 0.1U_0402_10V7K
CPPE#
<12> <7> PCH_CL_CLK1 <7> PCH_CL_DATA1 <7> PCH_CL_RST1#
@ R223 1
54
2 0_0402_5%
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51
BT_RADIO_DIS#_R 53
CONN@
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52
GND1
GND2
2
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52
1
1
2
1
2
2
1
2
1
1
2
C262 4.7U_0603_6.3V6K
CLK_PCIE_MINI1# CLK_PCIE_MINI1
CLK_PCIE_MINI1# CLK_PCIE_MINI1
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52
C261 0.1U_0402_25V6
<7> <7>
D
MINI1CLK_REQ#
MINI1CLK_REQ#
+3.3V_WLAN
CONN@
C260 0.1U_0402_25V6
<7>
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51
PCIE_WAKE#
C259 0.047U_0402_16V4Z
+3.3V_mSATA_WWAN JMINI2
PCIE_WAKE#
C258 0.047U_0402_16V4Z
+3.3V_mSATA_WWAN <37>
Mini WLAN/WIiGi/BT H=3.6
@ C257 0.1U_0402_25V6
Mini WWAN/GPS/LTE/mSATA H=3.6
2 D
MSDATA
C241 4700P_0402_25V7K HOST_DEBUG_TX
<37>
WLAN_RADIO_DIS#_R MINI_CARD_RST#
WIGIG60GHZ_DIS#_R USBP2USBP2+ CPUSB#
WIMAX_LED# WLAN_LED# BT_LED# 1 2 @ R222 0_0402_5%
<11> <11> <12>
MSDATA
<37>
WIMAX_LED# STUDY FOR DEBUG 54
LCN_DAN08-52216-0100 1 @R160 @ R160
2 mSATA_DEVSLP 10K_0402_5%
LCN_DAN08-52216-0100 +3.3V_mSATA_WWAN
1 @ R215
+3.3V_mSATA_WWAN
2 0_0402_5%
1 2
2
2
2
1 + 2
1 + 2
<36>
C254 150U_B2_6.3VM_R35M
2
1
3@ C253 150U_B2_6.3VM_R35M
2
1
3@ C252 33P_0402_50V8J
2
WWAN_SMBCLK
1
3@ C251 22U_0805_6.3V6M
DDR_XDP_WAN_SMBDAT
1 0_0402_5% 1 0_0402_5%
3@ C250 33P_0402_50V8J
<18,19,7,9>
2 @ R218 2 @ R219
1
3@ C249 0.047U_0402_16V4Z
DDR_XDP_WAN_SMBCLK
1
3@ C248 0.047U_0402_16V4Z
<18,19,7,9>
@ R217 2.2K_0402_5%
C
@ R216 2.2K_0402_5%
1
D12 1
WLAN_RADIO_DIS#
2
WLAN_RADIO_DIS#_R
RB751S40T1G_SOD523-2
C
@
1 @ R224
2 0_0402_5% D13
<36>
1
WIGIG60GHZ_DIS#
2
WIGIG60GHZ_DIS#_R
PWR Rail
Primary Power
Voltage Tolerance
Peak
Normal
+3.3V
+-9%
1000
750
+3.3Vaux
+-9%
330
250
Aux Power Normal
RB751S40T1G_SOD523-2
WWAN_SMBDAT 1 @ R225
2 0_0402_5%
250 (Wake enable) 5 (Not wake enable)
D14 <36>
1
BT_RADIO_DIS#
2
BT_RADIO_DIS#_R
RB751S40T1G_SOD523-2
LED control circuit
1
+3.3V_HDD
+3.3V_WLAN PJP22 PAD-OPEN1x1m
3.3V_ALW for LID power
UIM_CLK
<40,41>
+COINCELL
VOUT2 VOUT2 GPAD
1
2
4
2
+3.3V_WLAN_U3
15
PJP23
3
1
+3.3V_WLAN
1
WLAN_LED#
PAD-OPEN1x1m
1 @ C422 0.1U_0402_10V7K
WIRELESS_LED#
<36,40>
DMN66D0LDW-7_SOT363-6
2
9 8
S
WIMAX_LED# 10
Q22B 6
DMN66D0LDW-7_SOT363-6 Q30B
1
BT_LED#
2
AUX_EN_WOWL 100K_0402_5%
5
2 470P_0402_50V7K
G
1 C409
B
Q22A D
0.1U_0402_10V7K
11
TPS22966DPUR_SON14_2X3~D
R51
2
2 470P_0402_50V7K
G
VIN2 VIN2
1 @ C428
1 C429
D
6 7
CT2
+3.3V_HDD_U3
12
S
GND
ON2
14 13
2
CT1
VBIAS
5
AUX_EN_WOWL
AUX_EN_WOWL
ON1
4
+5V_ALW <36>
12 11 10 9 8 7 6 5 4 3 2 1 JSH1
VOUT1 VOUT1
G
UIM_DATA UIM_VPP UIM_RESET
3
6 D
+SIM_PWR
12 11 10 9 8 7 6 5 4 3 2 1
3.3V_HDD_EN
2 0_0402_5%
S
<36,40>
+3.3V_ALW LID_CL#
<12>
GND2 GND1
1 @R129 @ R129
R228 1 2 100K_0402_5%
14 13
R227 1 2 100K_0402_5%
VIN1 VIN1
CONN@
2
U3 1 2 B
R229 1 2 100K_0402_5%
+3.3V_ALW
DMN66D0LDW-7_SOT363-6 +3.3V_mSATA_WWAN
O
4
5
4
G D
DELL CONFIDENTIAL/PROPRIETARY
MINI_CARD_RST# 1
A
2
TC7SH08FU_SSOP5~D
B
@ U30 R26 100K_0402_5%
2
MPCIE_RST#
A
DMN66D0LDW-7_SOT363-6 5
1
PCH_PLTRST#_EC <6,7>
3 S
@ C338 2 1
P
<25,29,36,37,9>
Q30A
4
LED_WWAN_OUT# 0.1U_0402_25V6
G
2
+3.3V_RUN
@
3
A
C50 0.1U_0402_16V4Z
1
2 0_0402_5%
ST change to 6718K-Y12N-01L & swap pin
5
1 @R131 @ R131
+3.3V_ALW
R226 1 2 100K_0402_5%
E-T_6718K-Y12N-01L
Compal Electronics, Inc.
@
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
3
2
Title
Mini Card/SIM Card Size
Document Number
Date:
Friday, May 17, 2013
Rev 0.3
LA-9431P Sheet 1
31
of
59
5
4
3
2
1
D
D
C
C
SA000064200 +3.3V_SUS
1
Dock
0
M/B
1
2
1
2
@
1
2
C416 0.1U_0402_25V6
function
USB3TP3 USB3TN3 USB3RP3 USB3RN3 USBP5+ USBP5-
2
@
C414 0.1U_0402_25V6
DOCKED
<11> <11> <11> <11> <11> <11>
1
C417 0.1U_0402_25V6
check port mapping
2
@
C415 0.1U_0402_25V6
2
1
C418 0.1U_0402_25V6
2
1
C419 0.1U_0402_25V6
1
C420 4.7U_0603_6.3V6K
B
U33 3 9 12 16 20 29
1 2 4 5 6 7 8
VDD VDD VDD VDD VDD VDD
TX+ TXRX+ RXD+ DUSB_ID
TX+A TX-A RX+A RX-A D+A D-A USB_IDA TX+B TX-B RX+B RX-B D+B D-B USB_IDB
OE# <21,27,28,36>
DOCKED
10 32
SS_SEL HS_SEL
GND GND HGND
31 30 27 26 19 18 17
SW_USB3TP3 SW_USB3TN3 SW_USB3RP3 SW_USB3RN3 SW_USBP5+ SW_USBP5-
<33> <33> <33> <33> <33> <33>
25 24 23 22 15 14 13
DOCK_USB3TP3 DOCK_USB3TN3 DOCK_USB3RP3 DOCK_USB3RN3 DOCK_USBP5+ DOCK_USBP5-
<34> <34> <34> <34> <34> <34>
B
11 21 28 33
PI3USB3102ZLEX_TQFN32_6X3
A
A
DELL CONFIDENTIAL/PROPRIETARY Compal Electronics, Inc. PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Mini Card PWR Size
Document Number
Date:
Friday, May 17, 2013
Rev 0.3
LA-9431P Sheet 1
32
of
59
4
3
2
L37 EMC@
<32>
SW_USB3RN3 SW_USB3RP3
4
3
USB3RN3_D-
1
2
USB3RP3_D+
+USB_PWR D15 1
9
USB3RN3_D-
USB3RP3_D+
2
8
USB3RP3_D+
USB3TN3_D-
4
7
USB3TN3_D-
1
USB3TP3_D+
5
6
USB3TP3_D+
+
USBP5_DUSBP5_D+
SW_USB3TN3
<32>
SW_USB3TP3
2 C282 2 C283
1 SW_USB3TN3_C 0.1U_0402_10V7K
4
1 SW_USB3TP3_C 0.1U_0402_10V7K
1
3
2
USB3TN3_D3
2
USB3TP3_D+
TVWDF1004AD0_DFN9
2
USB3RN3_DUSB3RP3_D+
1 @ R239
1
DLW21SN670HQ2L_4P 1 2 @ R237 0_0402_5%
USB3TN3_DUSB3TP3_D+ EMC@D16 EMC@ D16 L30ESDL5V0C3-2_SOT23-3
L38 EMC@ <32>
1
C281 0.1U_0402_25V6
D
2 0_0402_5%
JUSB2 1 2 3 4 5 6 7 8 9
EMC@
USB3RN3_D-
C280 150U_B2_6.3VM_R35M
DLW21SN670HQ2L_4P 1 2 @ R235 0_0402_5% 1 @ R236
1
3
<32>
2
5
2 0_0402_5%
VBUS DD+ GND SSRXSSRX+ GND SSTXSSTX+
CONN@
GND GND GND GND
10 11 12 13 D
SANTA_373070-1
+USB_PWR
+5V_ALW L39 SW_USBP5+
<32>
SW_USBP5-
SW_USBP5+
1
SW_USBP5-
4
EMC@
1
2
4
3
2
USBP5_D+
3
USBP5_D-
U32
1
1 @ R240
2
2 0_0402_5%
C
C284 10U_0603_6.3V6M
DLW21HN900SQ2L_4P 1 2 @ R238 0_0402_5%
1
2
C285 0.1U_0402_25V6
<32>
<36>
1 2 3 4
ESATA_USB_PWR_EN#
GND VOUT VIN VOUT VIN VOUT EN FLG
8 7 6 5
USB_OC2#
<11>
G547I2P81U_MSOP8
C
2
+5V_ALW
R243 100K_0402_5% +5V_USB_CHG_PWR
1 2 0_0402_5%
PWRSHARE_EN#
USB_PWR_SHR_EN#
8 7 6 5
SB# SW_USBP0SW_USBP0+
+3.3V_ALW
<36> DOCKED_LIO_EN <11> USBP0+ <11> USBP0-
VCC S D+ DOE#
1D+ 1D2D+ 2DGND
1 2 3 4 5
SW_USBP0+ SW_USBP0-
1 DOCK_USBP0+ DOCK_USBP0-
<34> <34> 2
1 2 3 4 9
PWRSHARE_EN PS_USBP0_DPS_USBP0_D+ 1 SEL R244
2 +5V_ALW 10K_0402_5%
JUSB1
D
2 G S
1 +
SLG55594AVTR_TDFN8_2X2 2
1
2
USB3RN2_DUSB3RP2_D+
NX3DV221GM_XQFN10U10_2X1P55
DOCKED_LIO_EN
1
check port mapping B
function
1
Dock
0
M/B
1 2 3 4 5 6 7 8 9
USBP0_DUSBP0_D+
Q7 L2N7002WT1G_SC-70-3
USB3TN2_DUSB3TP2_D+
CONN@
VBUS DD+ GND SSRXSSRX+ GND SSTXSSTX+
EMC@ D18 L30ESDL5V0C3-2_SOT23-3
2
C322 0.1U_0402_25V6
1
10 9 8 7 6
C287 0.1U_0402_25V6
+5V_ALW
U36
CB CEN TDM DM TDP DP VddSMART-CDP Thermal-Pad
C291 0.1U_0402_25V6
2 0_0402_5%
C290 150U_B2_6.3VM_R35M
1 @ R242
2
U39 <36>
3
1
1 @R241 @ R241
USB_PWR_SHR_VBUS_EN
3
<36>
GND GND GND GND
10 11 12 13
SANTA_373070-1
B
D17
L40
USB3RP2
1
4
3
1
2
USB3RN2_D-
2
USB3RP2_D+
1
9
USB3RN2_D-
USB3RP2_D+
2
8
USB3RP2_D+
USB3TN2_D-
4
7
USB3TN2_D-
USB3TP2_D+
5
6
USB3TP2_D+
1 @ R247
3
2 0_0402_5%
USB3TN2
<11>
USB3TP2
2
1 USB3TN2_C 0.1U_0402_10V7K
4
2
1 USB3TP2_C 0.1U_0402_10V7K
1
C292 C293
A
4
3
1
2
2
TVWDF1004AD0_DFN9
L41 EMC@ <11>
U35
1
DLW21SN900HQ2L-0805_4P 1 2 @ R246 0_0402_5%
3
USB3TN2_D-
PS_USBP0_D+
EMC@ 4
2
USB3TP2_D+
PS_USBP0_D-
1
1
2
PWRSHARE_EN#
1 2 3 4
GND VOUT VIN VOUT VIN VOUT EN FLG
8 7 6 5
USB_OC0#
<11>
G547I2P81U_MSOP8
L42 3
USBP0_D+
2
USBP0_D-
DLW21SN900HQ2L-0805_4P 1 2 @ R248 0_0402_5%
CMM0805-120Y-N_4P 1 2 @R249 @ R249 0_0402_5%
1 @ R250
1 @R251 @ R251
2 0_0402_5%
+5V_USB_CHG_PWR
+5V_ALW
C289 0.1U_0402_25V6
USB3RN2
<11>
3
EMC@
USB3RN2_D-
C288 10U_0603_6.3V6M
<11>
4
EMC@
2 0_0402_5%
A
DELL CONFIDENTIAL/PROPRIETARY Compal Electronics, Inc. PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
Title
USB x2 Size
4
3
2
Rev 0.3
LA-9431P Date:
5
Document Number Friday, May 17, 2013
Sheet 1
33
of
59
3
<21> <21>
DPC_LANE_P0 DPC_LANE_N0
<21> <21>
DPC_LANE_P1 DPC_LANE_N1
<21> <21> <21> <21>
DPC_LANE_P2 DPC_LANE_N2 DPC_LANE_P3 DPC_LANE_N3
C302 2 C295 2
1 0.1U_0402_10V7KDPC_LANE_P0_C 1 0.1U_0402_10V7KDPC_LANE_N0_C
C297 2 C299 2
1 0.1U_0402_10V7KDPC_LANE_P1_C 1 0.1U_0402_10V7KDPC_LANE_N1_C
R253 1 R255 1
2 33_0402_5% 2 33_0402_5%
DPC_DOCK_LANE_P1 DPC_DOCK_LANE_N1
C304 2 C306 2
1 0.1U_0402_10V7KDPC_LANE_P2_C 1 0.1U_0402_10V7KDPC_LANE_N2_C
R257 1 R263 1
2 33_0402_5% 2 33_0402_5%
DPC_DOCK_LANE_P2 DPC_DOCK_LANE_N2
C300 2 C301 2
1 0.1U_0402_10V7KDPC_LANE_P3_C 1 0.1U_0402_10V7KDPC_LANE_N3_C
R265 1 R266 1
2 33_0402_5% 2 33_0402_5%
DPC_DOCK_LANE_P3 DPC_DOCK_LANE_N3
<24> <24> <21>
DPC_DOCK_AUX DPC_DOCK_AUX#
DPC_DOCK_HPD @
<21>
BLUE_DOCK
<21>
RED_DOCK
<21>
DPC_DOCK_HPD
RED_DOCK GREEN_DOCK
GREEN_DOCK
<21> <21>
HSYNC_DOCK VSYNC_DOCK
<37> <37>
CLK_MSE DAT_MSE
1
C
BLUE_DOCK
2
R268 100K_0402_5%
<26> <26>
DAI_BCLK# DAI_LRCK#
<26> <26>
DAI_DI DAI_DO#
<26>
DAI_12MHZ#
<36> <36>
D_LAD0 D_LAD1
<36> <36>
D_LAD2 D_LAD3
<36> <36>
D_LFRAME# D_CLKRUN#
<36> <36> <7>
D_SERIRQ D_DLDRQ1#
CLK_PCI_DOCK
<37> DOCK_SMB_CLK <37> DOCK_SMB_DAT <36,41,48> B
<37> <36,41,48>
DOCK_SMB_ALERT# <41> DOCK_PSID DOCK_PWR_BTN# SLICE_BAT_PRES#
SLICE_BAT_PRES#
145 146 147 2 1
2
@
151 152 153 154 155 156
GND1 PWR1 PWR1
GND2 PWR2 PWR2
Shield_G Shield_G Shield_G Shield_G Shield_G Shield_G
Shield_G Shield_G Shield_G Shield_G Shield_G Shield_G
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144
DOCK_AC_OFF
DOCK_AC_OFF <48> DOCK_LOM_SPD100LED_ORG# <28> DPB_CA_DET <21,24> 2 33_0402_5% DPB_LANE_P0_C R260 1 2 33_0402_5% DPB_LANE_N0_C R261 1
DPB_CA_DET DPB_DOCK_LANE_P0 DPB_DOCK_LANE_N0
R254 1 R256 1
2 33_0402_5% DPB_LANE_P1_C 2 33_0402_5% DPB_LANE_N1_C
C298 2 C303 2
1 0.1U_0402_10V7K 1 0.1U_0402_10V7K
DPB_DOCK_LANE_P2 DPB_DOCK_LANE_N2
R262 1 R264 1
2 33_0402_5% DPB_LANE_P2_C 2 33_0402_5% DPB_LANE_N2_C
C305 2 C307 2
1 0.1U_0402_10V7K 1 0.1U_0402_10V7K
DPB_DOCK_LANE_P3 DPB_DOCK_LANE_N3
R258 1 R267 1
2 33_0402_5% DPB_LANE_P3_C 2 33_0402_5% DPB_LANE_N3_C
C308 2 C309 2
1 0.1U_0402_10V7K 1 0.1U_0402_10V7K
DPB_DOCK_AUX DPB_DOCK_AUX#
DPB_DOCK_AUX DPB_DOCK_AUX#
<24> <24>
ACAV_DOCK_SRC#
<48>
DPB_LANE_P0 DPB_LANE_N0
<21> <21>
DPB_LANE_P1 DPB_LANE_N1
<21> <21>
DPB_LANE_P2 DPB_LANE_N2
<21> <21>
DPB_LANE_P3 DPB_LANE_N3
<21> <21>
DPB_DOCK_HPD DAT_DDC2_DOCK CLK_DDC2_DOCK
1
<21> <21> 2
SATA_PRX_DKTX_P0 SATA_PRX_DKTX_N0
C312 2 C313 2
1 .01U_0402_16V7K 1 .01U_0402_16V7K
SATA_PTX_DKRX_P0 SATA_PTX_DKRX_N0
C314 1 C315 1
2 .01U_0402_16V7K 2 .01U_0402_16V7K
SATA_PRX_DKTX_P0_C SATA_PRX_DKTX_N0_C
DOCK_USBP5+ DOCK_USBP5CLK_KBD DAT_KBD
<32> <32>
DOCK_USB3TN3 DOCK_USB3TP3
<32> <32>
4
4
<21>
ESD depop location(EMC) Close to DOCK Its for Enhance ESD on dock issue.
DOCK_USBP0+
<33>
DOCK_USBP0-
<33>
DLW21SN900SQ2L-0805_4P @ L43 2 1 @ R269 0_0402_5% 2 1 @ R270 0_0402_5%
<37> <37>
DOCK_USB3RN3 DOCK_USB3RP3
3
@
<6> <6>
2
3
<32> <32>
<6> <6>
SATA_PTX_DKRX_P0_C SATA_PTX_DKRX_N0_C 1 1
2
DOCK_USBP0_D+ DOCK_USBP0_D-
C
DPB_DOCK_HPD
EMI solution for E-Docking USB(EMC)
BREATH_LED# <36,40> DOCK_LOM_ACTLED_YEL#
R271 100K_0402_5%
<28>
DOCK_LOM_TRD0+ DOCK_LOM_TRD0-
<28> <28>
DOCK_LOM_TRD1+ DOCK_LOM_TRD1-
<28> <28>
+3.3V_ALW +LOM_VCT DOCK_DET# 1
+LOM_VCT DOCK_LOM_TRD2+ DOCK_LOM_TRD2-
<28> <28>
DOCK_LOM_TRD3+ DOCK_LOM_TRD3-
<28> <28>
DOCK_DCIN_IS+ DOCK_DCIN_ISDOCK_POR_RST#
2
1 R272
2 10K_0402_5%
@ C316 1U_0402_6.3V6K
<47> <47>
B
<37>
D19 1
DOCK_DET_R#
2
DOCK_DET#
<36,48>
RB751S40T1G_SOD523-2 +DOCK_PWR_BAR 1
2
DAI_BCLK#
CLK_PCI_DOCK @ R273 33_0402_5%
1
2
2
2
@ RE5 10_0402_1% 2
@ RE4 10_0402_1%
ESD depop location(EMC)
D
DPB_DOCK_HPD
DAI_12MHZ# WD2F144WB8 JAE_WD2F144WB8-DT
1 0.1U_0402_10V7K 1 0.1U_0402_10V7K
DPB_DOCK_LANE_P1 DPB_DOCK_LANE_N1
148 149 150 157 158 159 160 161 162
C294 2 C296 2
C318 0.1U_0603_50V7K
1
D20 PESD24VS2UT_SOT23-3
@
C317 0.1U_0603_50V7K
2
CE7 4.7U_0805_25V6-K
1
3
+DOCK_PWR_BAR
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144
C311 0.033U_0402_16V7K
+NBDOCK_DC_IN_SS
C310 0.033U_0402_16V7K
1
2
Close to DOCK Its for Enhance ESD on dock issue.
DPC_DOCK_LANE_P0 DPC_DOCK_LANE_N0
DPC_DOCK_AUX DPC_DOCK_AUX#
DPC_DOCK_HPD
ESD depop location(EMC)
DPC_CA_DET
1
D
DOCK_LOM_SPD10LED_GRN# <21,24> DPC_CA_DET 2 33_0402_5% R259 1 2 33_0402_5% R252 1
CONN@
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143
1
<28>
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143
1
1
JDOCK1 DOCK_DET_1
2
2
4
1
5
1 @CE8 @CE8 4.7P_0402_50V8C
2
1 @CE9 @CE9 4.7P_0402_50V8C
2
@ C319 12P_0402_50V8J
EMI depop location(EMC)
A
A
DELL CONFIDENTIAL/PROPRIETARY Compal Electronics, Inc. Title PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 5
4
3
2
E series Dock Connector Size
Document Number
Date:
Friday, May 17, 2013
Rev 0.3
LA-9431P Sheet 1
34
of
59
5
4
3
T94
<28>
SW_LAN_TX1-
<28>
SW_LAN_TX1+
SW_LAN_TX1-
1
SW_LAN_TX1+
2
1:1
TD1+
TX1+
TD1TX1-
D
C324 0.47U_0603_10V7K
2
SW_LAN_TX0-
SW_LAN_TX0-
4 5
SW_LAN_TX0+
6
TXCT1
TDCT2 TD2+
TXCT2 TX2+
1:1
23
NB_LAN_TX1+
22
RJ45 LOM circuit +3.3V_LAN D
Z2805
21 20
Z2807 NB_LAN_TX0-
19
NB_LAN_TX0+
1
2 <28>
SW_LAN_TX0+
TD2-
TX2-
TX3+
TD3TX3-
+3.3V_LAN:20mils
<28>
SW_LAN_TX2-
SW_LAN_TX2+
10 11
SW_LAN_TX2-
TDCT4 TD4+
12
SW_LAN_TX2+
TXCT3 TXCT4 TX4+
1:1
TD4-
TX4-
17 16 15 14
13
10
LAN_ACTLED_YEL_R#
9
NB_LAN_TX3NB_LAN_TX3-
8
NB_LAN_TX3+
7
NB_LAN_TX1-
6
NB_LAN_TX2-
5
NB_LAN_TX2+
4
NB_LAN_TX1+
3
NB_LAN_TX0-
2
NB_LAN_TX0+
1
NB_LAN_TX3+ Z2806 Z2808 NB_LAN_TX2-
NB_LAN_TX2+
<28>
1
TAIMA_IH-115-F
1
<28> 1
2
<28>
TDCT3
18
1
C326 0.47U_0603_10V7K
2
C325 0.47U_0603_10V7K
9
C
2
R274 1 2 150_0402_5%
LAN_ACTLED_YEL#
75_0402_1%
8
SW_LAN_TX3+
1:1
TD3+
75_0402_1%
SW_LAN_TX3+
7
SW_LAN_TX3-
75_0402_1%
<28>
SW_LAN_TX3-
75_0402_1%
<28>
1
1
JLOM1 <28>
1
1
C321 0.1U_0402_10V7K
2
1
<28>
TDCT1
NB_LAN_TX1-
C320 470P_0402_50V7K
1
C323 0.47U_0603_10V7K
3
24
2
LED_10_GRN# LED_100_ORG#
1 R275 1 R276
2 LED_10_GRN_R# 150_0402_5% 2 LED_100_ORG_R# 150_0402_5%
11 13 12
CONN@
Yellow LEDYellow LED+ PR4PR4+ PR2PR3PR3+ PR2+ PR1GND PR1+ GND
15 C
14
Green LEDOrange LEDGreen-Orange LED+
2
<11>
4
USB3RN1
4
USB3RN1_D-
2
USB3RP1_D+
D34
R280 2
+USB_SIDE_PWR
EMC@
DLW21SN900HQ2L-0805_4P
USB3TN1_D-
4
7
USB3TN1_D-
1 @ R484 1 @ R485
USB3TP1_D+
5
6
USB3TP1_D+
1
2
2 0_0402_5% 2 0_0402_5%
JUSB3
3 TVWDF1004AD0_DFN9
1 + 2
2
2 1 USB3TN1_RP_C C448 0.1U_0402_10V7K
4
<11>
USB3TP1
2 1 USB3TP1_RP_C C449 0.1U_0402_10V7K
1
4 1
3 2
3
USB3TN1_D-
2
USB3TP1_D+
1
USB3TN1
USB3RN1_DUSB3RP1_D+
1
L56 EMC@ <11>
1 2 3 4 5 6 7 8 9
USBP1_R_DUSBP1_R_D+
EMC@D33 EMC@ D33 L30ESDL5V0C3-2_SOT23-3
USB3RP1_D+
C445
USB3RN1_D-
8
0.1U_0402_25V6
9
2
C444
1
USB3RP1_D+
150U_B2_6.3VM_R35M
B
3
USB3RN1_D-
1
USB3RP1
3
R279 2
150P_1808_2.5KV8J use 40mil trace if necessary
L55 EMC@ <11>
Symbol update OK
+GND_CHASSIS
3
1 EMC@C327 EMC@ C327
2
GND CHASSIS
R278 2
R277 2
rev1 SANTA_130456-341
USB3TN1_DUSB3TP1_D+
CONN@
VBUS DD+ GND StdA-SSRXStdA-SSRX+ GND-DRAIN StdA-SSTXStdA-SSTX+
GND GND GND GND
B
10 11 12 13
TAITW_PUBAUE-09FLBS1FF4H0
ST change to PUBAUE-09FLBS1FF4H0
DLW21SN900HQ2L-0805_4P L54 1 @R486 @ R486 1 @R487 @ R487
2 0_0402_5% 2 0_0402_5%
<11> <11>
USBP1+ USBP1-
1 4
1 4
EMC@ 2 3
2
USBP1_R_D+
3
USBP1_R_D-
+USB_SIDE_PWR +5V_ALW
A
GND1 GND2
5 6
1
2
1
2
C447 0.1U_0402_25V6
WIRELESS_ON#/OFF
1 2 3 4
C446
<36>
1 2 3 4
10U_0603_10V6M
DLW21HN900SQ2L_4P 1 2 @ R482 0_0402_5% 1 2 @ R483 0_0402_5%
CONN@ JSF1
U52
<36>
ACES_50277-0040N-001
USB_SIDE_EN#
1 2 3 4
GND VOUT VIN VOUT VIN VOUT EN FLG
8 7 6 5
USB_OC1#
<11>
G547I2P81U_MSOP8
A
DELL CONFIDENTIAL/PROPRIETARY Compal Electronics, Inc. PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
To Sniffer Board 5
4
3
2
Title
RJ45 and USBx1 Size
Document Number
Date:
Friday, May 17, 2013
Rev 0.3
LA-9431P Sheet 1
35
of
59
5
4
3
2
1
+3.3V_ALW
1 R281 1 R282
2 ALS_INT# 10K_0402_5% 2 HW_GPS_DISABLE2# 100K_0402_5%
+3.3V_ALW
+3.3V_ALW_U37 PJP6
2 CPU_DETECT# 100K_0402_5% 2 SLICE_BAT_PRES# 100K_0402_5%
1
2
1 @ R304
U37
MCARD_MISC_PWREN PROCHOT_GATE LID_CL_SIO# DOCK_SMB_ALERT# TOUCH_SCREEN_PD#
B52 A49 B53 A50 B54 A51 B55 A52
USB_SIDE_EN# EN_I2S_NB_CODEC# USH_PWR_STATE# EN_DOCK_PWR_BAR PANEL_BKEN_EC ENVDD_PCH LCD_TST PSID_DISABLE# PBAT_PRES# DOCKED DOCK_DET# AUD_NB_MUTE# MCARD_WWAN_PWREN LCD_VCC_TEST_EN CCD_OFF AUD_HP_NB_SENSE ESATA_USB_PWR_EN#
A33 B36 A34 B37 A35 B38 A36 A37 B40 A38 B41 A39 B42 A40 B43 A41 B44
MODULE_ON SLICE_BAT_ON SLICE_BAT_PRES# MODULE_BATT_PRES#
B32 A31 B33 B15 A15 B16 A16
GPIOA0 GPIOA1 GPIOA2 GPIOA3 GPIOA4 GPIOA5 GPIOA6 GPIOA7 GPIOB0 GPIOB1 GPOC2 GPOC3 GPOC4 GPOC5 GPOC6/TACH4 GPIOC7 GPIOD0 GPIOC1 GPIOC0 GPIOB7 GPIOB6 GPIOB5 GPIOB4 GPIOB3 GPIOB2
10K_0402_5% @ T106 PAD~D <48> SLICE_BAT_ON <34,41,48> SLICE_BAT_PRES# @ T107 PAD~D
CHARGE_PBATT
@ T110 PAD~D
WIGIG60GHZ_DIS#
<31> WIGIG60GHZ_DIS# <31,37> EC5048_TX
1 R309 1 R310 1 R313
mCARD_PCIE_SATA# CPU_DETECT# XFR_ID_BIT#
mCARD_PCIE_SATA# <9> CPU_DETECT#
DP_HDMI_HPD
@ T115 PAD~D
2 LCD_TST 100K_0402_5% 2 SYS_LED_MASK# 10K_0402_5% 2 CHARGE_EN 100K_0402_5%
<29>
BCM5882_ALERT#
BCM5882_ALERT# <12,9> SUSACK# @ T118 PAD~D
EDID_SELECT# VGA_ID
<12>
<40>
<33>
SLP_ME_CSW_DEV#
SLP_ME_CSW_DEV#
<28>
B
SYS_LED_MASK#
WIRELESS_ON#/OFF BT_RADIO_DIS# WWAN_RADIO_DIS# SYS_PWROK DGPU_SELECT#
SIO_SLP_WLAN#
<9>
PCH_DPWROK
A59 B62 A58 B61 A56 B59 A55 B58
B47 A45 B48 A46 B49 A47 WIRELESS_LED# USB_PWR_SHR_VBUS_EN B50 A48 WLAN_RADIO_DIS#
WIRELESS_ON#/OFF BT_RADIO_DIS# WWAN_RADIO_DIS# <9> SYS_PWROK
@ T121 PAD~D <9>
A1 B2 A2 B3 A3 B45 A42 B4
LAN_DISABLE#_R CHARGE_EN SYS_LED_MASK# ALS_INT#
LAN_DISABLE#_R
<12,9> SIO_EXT_WAKE# <31,40> WIRELESS_LED# USB_PWR_SHR_VBUS_EN <31> WLAN_RADIO_DIS# <35> <31> <31>
CPU_VTT_ON 1 2 @ R319
0_0402_5%
B13 A13 A53 B57 B14 A14 B17 B18
GPIOD1 GPIOD2 GPIOD3 GPIOD4 GPIOD5 GPIOD6 GPIOD7 GPIOE0/RXD GPIOE1/TXD GPIOE2/RTS# GPIOE3/DSR# GPIOE4/CTS# GPIOE5/DTR# GPIOE6/RI# GPIOE7/DCD# GPIOF0 GPIOF1 GPIOF2 GPIOF3/TACH8 GPIOF4/TACH7 GPIOF5 GPIOF6 GPIOF7 GPIOG0/TACH5 GPIOG1 GPIOG2 GPIOG3 GPIOG4 GPIOG5 GPIOG6 GPIOG7/TACH6
GPIOI0 GPIOI1 GPIOI2/TACH0 GPIOI3 GPIOI4 GPIOI5 GPIOI6 GPIOI7 GPIOJ0 GPIOJ1/TACH1 GPIOJ2/TACH2 GPIOJ3 GPIOJ4 GPIOJ5 GPIOJ6 GPIOJ7 GPIOK0 GPIOK1/TACH3 GPIOK2 GPIOK3 GPIOK4 GPIOK5 GPIOK6 GPIOK7 GPIOL0/PWM7 GPIOL1/PWM8 GPIOL2/PWM0 GPIOL3/PWM1 GPIOL4/PWM3 GPIOL5/PWM2 GPIOL6 GPIOL7/PWM5 GPIOM1 GPIOM3/PWM4 GPIOM4/PWM6 LAD0 LAD1 LAD2 LAD3 LFRAME# LRESET# PCICLK CLKRUN# LDRQ1# SER_IRQ 14.318MHZ/GPIOM0 CLK32/GPIOM2 DLAD0 DLAD1 DLAD2 DLAD3 DLFRAME# DCLKRUN# DLDRQ1# DSER_IRQ BC_INT# BC_DAT BC_CLK
GPIOH0 GPIOH1 SYSOPT1/GPIOH2 SYSOPT0/GPIOH3 GPIOH4 GPIOH5 GPIOH6 GPIOH7
PWRGD OUT65 TEST_PIN CAP_LDO VSS EP DB Version 0.4 ECE5048-LZY_DQFN132_11X11~D
1
ME_FWP
2
@ R326 @R326 1K_0402_5%
5
@ R320 1 2 100K_0402_5%
ME_FWP PCH has internal 20K PD. (suspend power rail)
A23 B63 A60 A61 B65 A62 B66 A63 B67 A64 A5 B6 A6 B7 A7 B8
SIO_SLP_A#
SIO_SLP_A#
2
2
C332 0.1U_0402_25V6
AUX_EN_WOWL SIO_SLP_LAN# SIO_SLP_SUS# MODC_EN DOCK_HP_DET DOCK_MIC_DET
A8 B9 B10 A10 B11 A11 B12 A12
ME_FWP MASK_SATA_LED# USB_PWR_SHR_EN# LED_SATA_DIAG_OUT#
B60 A57 B64 B68 A9 B1 A18 A44
SUS_ON
B34 B39 B51
HW_GPS_DISABLE2# BREATH_LED#
RUN_ON
BAT1_LED# BAT2_LED#
LPC_LAD0 LPC_LAD1 LPC_LAD2 LPC_LAD3 LPC_LFRAME# PCH_PLTRST#_EC CLK_PCI_5048 CLKRUN#
A22 B21 A32 B35
LPC_LDRQ1# IRQ_SERIRQ
B29 B28 A25 A24 B23 A19 B24 A20
D_LAD0 D_LAD1 D_LAD2 D_LAD3 D_LFRAME# D_CLKRUN# D_DLDRQ1# D_SERIRQ
A29 B31 A30
BC_INT#_ECE5048 BC_DAT_ECE5048 BC_CLK_ECE5048
A4
RUNPWROK
B56
SP_TPM_LPC_EN
B19
1 R321 +CAP_LDO
B27 C1
+3.3V_ALW
8 7 6 5
PROCHOT_GATE XFR_ID_BIT# WWAN_RADIO_DIS# SUS_ON
1 2 3 4
100K_0804_8P4R_5%
ME_FWP <6> MASK_SATA_LED# <40> USB_PWR_SHR_EN# <33> LED_SATA_DIAG_OUT# <40>
+3.3V_RUN
RUN_ON <26,37,39> AC_DIS <41,48> SPI_WP#_SEL <7>
D_CLKRUN#
SUS_ON
D_SERIRQ
<39,43>
BAT1_LED#
<40>trace width 20 mils
BAT2_LED#
<40>trace width 20 mils
D_DLDRQ1# LPC_LDRQ1#
<39>
HW_GPS_DISABLE2# <31> BREATH_LED# <34,40> DIS_BAT_PROCHOT# <48>
RUN_ON CPU_VTT_ON
LPC_LAD0 <25,29,37,7> LPC_LAD1 <25,29,37,7> LPC_LAD2 <25,29,37,7> LPC_LAD3 <25,29,37,7> LPC_LFRAME# <25,29,37,7> PCH_PLTRST#_EC <25,29,31,37,9> CLK_PCI_5048 <7> CLKRUN# <10,29,37,9> IRQ_SERIRQ
SLICE_BAT_ON
2 R299 2 R300 2 R301 2 R296
1 100K_0402_5% 1 100K_0402_5% 1 100K_0402_5% 1 10K_0402_5%
2 R303 2 R305
1 100K_0402_5% 1 100K_0402_5%
2 R307
1 100K_0402_5%
C
<12,29,37>
EC_32KHZ_ECE5048
<37>
D_LAD0 <34> D_LAD1 <34> D_LAD2 <34> D_LAD3 <34> D_LFRAME# <34> D_CLKRUN# <34> D_DLDRQ1# <34> D_SERIRQ <34> BC_INT#_ECE5048 BC_DAT_ECE5048 BC_CLK_ECE5048 RUNPWROK
B
<37> <37> <37>
<37,9>
SP_TPM_LPC_EN
2 1K_0402_5%
<29>
+3.3V_ALW
+CAP_LDO trace width 20 mils CLK_PCI_5048
1
2
RP11
AUX_EN_WOWL <31> WLAN_LAN_DISB# <28> SIO_SLP_LAN# <28,9> SIO_SLP_SUS# <9> GPIO_PSID_SELECT <41> PAD~D T101 @ DOCK_HP_DET <26> DOCK_MIC_DET <26>
USH_PWR_ON PAD~D T100 @
FP_POA_EN
A27 A26 B26 B25 A21 B22 A28 B20
B46
<39,44,9>
SIO_SLP_S4# <39,43,9> SIO_SLP_S3# <39,43,9> IMVP_PWRGD <46> IMVP_VR_ON <46> DOCK_AC_OFF_EC <48>
C336 4.7U_0603_6.3V6K
R322 100K_0402_5%
@ R324 33_0402_5%
@ C339 33P_0402_50V8J
2 R325
LID_CL_SIO#
1 10_0402_1%
LID_CL#
<31,40>
1
2
R317 1 2 100K_0402_5%
+3.3V_ALW
A
2
1 C331 0.1U_0402_25V6
D
2 USB_PWR_SHR_EN# 100K_0402_5% 2 USB_SIDE_EN# 10K_0402_5% 2 WIGIG60GHZ_DIS# 100K_0402_5% 2 USB_PWR_SHR_VBUS_EN <33> DOCKED_LIO_EN 100K_0402_5% 2 DOCK_SMB_ALERT# @ T97 PAD~D 100K_0402_5% <47> PROCHOT_GATE 2 WIRELESS_ON#/OFF 100K_0402_5% DOCK_SMB_ALERT# 2 ESATA_USB_PWR_EN# <34,41,48> @ T98 PAD~D 100K_0402_5% 2 BT_RADIO_DIS# 100K_0402_5% <35> USB_SIDE_EN# <26> EN_I2S_NB_CODEC# <29> USH_PWR_STATE# <48> EN_DOCK_PWR_BAR <22> PANEL_BKEN_EC <10,22> ENVDD_PCH <22> LCD_TST <41> PSID_DISABLE# <41,48> PBAT_PRES# <21,27,28,32> DOCKED <34,48> DOCK_DET# <26> AUD_NB_MUTE# <28> MCARD_WWAN_PWREN <22> LCD_VCC_TEST_EN <22> CCD_OFF <25,26> AUD_HP_NB_SENSE <33> ESATA_USB_PWR_EN# 2 SP_TPM_LPC_EN
<6>
1 C334 0.1U_0402_10V7K
1
C
2
1 C330 0.1U_0402_25V6
2
+3.3V_RUN
2
1 C329 0.1U_0402_25V6
1
1 R287 1 R288 1 R289 1 R291 1 R292 1 R293 1 R295 1 R298
1 C328 PAD-OPEN1x1m 10U_0603_6.3V6M
B5 A17 B30 A43 A54
D
2
1
VCC1 VCC1 VCC1 VCC1 VCC1
1 R284 1 R285
1 2
C337 0.047U_0402_16V4Z A
2 VGA_ID
EMI depop location(EMC)
VGA_ID0 Discrete
0
UMA
1
DELL CONFIDENTIAL/PROPRIETARY Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
4
3
2
Title
SIO & GPIO ECE5048 Size
Document Number
Date:
Friday, May 17, 2013
Rev 0.3
LA-9431P Sheet 1
36
of
59
5
4
3
2
1
+RTC_CELL +RTC_CELL 2 0_0402_5%
1
2
DOCK_PWR_BTN#
+1.05V_RUN
D
1
2
R376
C
1
2
1
2
R366 R368 2
1
2
1
2
1
2
R371 R372 @ R373 1
2
R377
<12> SIO_EXT_SMI# <12> SIO_RCIN# <12,29,36> IRQ_SERIRQ <25,29,31,36,9> PCH_PLTRST#_EC <7> CLK_PCI_MEC <25,29,36,7> LPC_LFRAME# <25,29,36,7> LPC_LAD0 <25,29,36,7> LPC_LAD1 <25,29,36,7> LPC_LAD2 <25,29,36,7> LPC_LAD3 <10,29,36,9> CLKRUN# <12> SIO_EXT_SCI#
2
VOL_UP_R 0.1U_0402_25V6
1
2
VOL_DOWN_R 0.1U_0402_25V6
1
2
VOL_MUTE_R 0.1U_0402_25V6
EMC@ C456
A61 A62 B62
MEC_XTAL1 1 MEC_XTAL2_R 2 0_0402_5% 0_0402_5%
MEC_XTAL2 2 @ R378 1 @ R379
ESD Request
SYSPWR_PRES VCI_OVRD_IN VCI_OUT VCI_IN0# VCI_IN1# VCI_IN2# VCI_IN3#
GPIO011/nSMI/GANG_DATA0 GPIO061/LPCPD# SER_IRQ LRESET# PCI_CLK LFRAME# LAD0 LAD1 LAD2 LAD3 CLKRUN# GPIO100/NEC_SCI
VREF_PECI PECI_DAT
XTAL1 XTAL2 GPIO160/32KHZ_OUT
B66
EMC@ C457
EC_32KHZ_ECE5048
A6 A27 A28 B30 A29 B31 A30 B32 A31 B33 A32 A33
AGND
<36> 1 EMC@ C455
SIO_EXT_SMI# SIO_RCIN# IRQ_SERIRQ PCH_PLTRST#_EC CLK_PCI_MEC LPC_LFRAME# LPC_LAD0 LPC_LAD1 LPC_LAD2 LPC_LAD3 CLKRUN# SIO_EXT_SCI#
GPIO123/BCM_A_CLK GPIO122/BCM_A_DAT GPIO121/BCM_A_INT# GPIO032/BCM_E_CLK GPIO031/GPTP-OUT2/BCM_E_DAT GPIO030/GPTP-IN2/BCM_E_INT# GPIO047/LSBCM_D_CLK GPIO046/LSBCM_D_DAT GPIO045/LSBCM_D_INT#
15mil
2 MEC_XTAL1
1 2
1
2
MEC_XTAL2
Y4 32.768KHZ_12.5PF_Q13FC1350000~D
1
2
C365 22P_0402_50V8J
2
R380 100K_0402_5%
B
1
C364 22P_0402_50V8J
+3.3V_ALW
USH_SMBDAT USH_SMBCLK
B51 A48
ACAV_IN <47,48> ALWON <42>
1
2
PECI_EC
43_0402_5%
C358 1
2 2200P_0402_50V7K
C359 1
2 2200P_0402_50V7K
REM_DIODE4_N REM_DIODE4_P
C361 1
2 2200P_0402_50V7K
VCP THERMATRIP2# THERMATRIP3# THSEL_STRAP PROCHOT#_EC 1 2 V_SYS R381 4.7K_0402_5%
1
2
1
2
1
R453 R452 R353 R364 R365 R401 1 2 3 4
C
1
2
1
+3.3V_ALW
1
+1.05V_RUN
1 R403
2 2.2K_0402_5%
2 B
C
Q12 1 MMST3904-7-F_SOT323-3
2
CHIPSET_ID for BID function
E
2 Q13 B MMBT3904WT1G_SC70-3~D
<12>
H_THERMTRIP#
REM_DIODE2_N
VSET_5075
1
REM_DIODE4_P 2
1 THSEL_STRAP R383
2 1K_0402_5% A
1
1
2
C
2
1
C
E
2 Q14 B MMBT3904WT1G_SC70-3~D
2 2
2
1
3
2
THERMATRIP2# REM_DIODE1_N
REM_DIODE4_N
FWP#
1
1 SYSTEM_ID
1
+5V_RUN @
1
2 Q11 B MMBT3904WT1G_SC70-3~D
+3.3V_ALW
2
BOARD_ID
FAN1_PWM FAN1_TACH
C
E
B
1
1 1
+3.3V_ALW
2
1
1 2
2
1 2
1
2
3
G
S
2
V.R
3
4 6 D
+3.3V_ALW
BOARD_ID rise time is measured from 5%~68%.
4
DP4/DN4
3
1 2
1 1
2
@
1
1 1 2
S
X00 X01 *** X02 *** *** *** A00
DIMM
2 G
2
3 D
2
2
R387
C371 0.1U_0402_25V6
4700p 4700p 4700p 4700p 4700p 4700p 4700p 4700p
DP2/DN2
4 3 2 1
ACES_50277-0040N-001
R394 1.58K_0402_1%
240K 130K 62K 33K 8.2K 4.3K 2K 1K
4 3 2 1
CPU
C367 0.1U_0402_25V6
1
1
Align E5,P5 Fan module pin define then swap pin define
GND2 GND1
DP4/DN4 for Skin on Q14, place Q14 close to Vcore VR choke. @C373 @ C373 100P_0402_50V8J
2
1
2
R402 8.2K_0402_5%
@ C372 100P_0402_50V8J
REV
6 5
1: Channel 1 will provide Thermistor Readings 0: Channel 1 will provide Diode Readings Rest=1.58K , Tp=96 degree
@ R399 10K_0402_5%
C368
<31,36>
pin define different with original part
5
2
R451
+1.05V_RUN
REM_DIODE2_P
R393 10K_0402_5%
EC5048_TX
1
R363
8 7 6 5
E
C369 4700P_0402_25V7K
*
HOST_DEBUG_TX
Pin8 5075_TXD for EC Debug pin9 5048_TXD for SBIOS debug
ACES_50521-01041-P01
2
R361
<47>
DP2/DN2 for SODIMM on Q13, place Q13 close to SODIMM and C372 close to Q13
R386 1K_0402_5%
2 0_0402_5%
R392
C368 4700P_0402_25V7K
@ R398 100K_0402_5%
R397 10K_0402_5%
5048_TX should be change Host_debug_tx 1 @ R400
2 0_0402_5%
RB751V40_SC76-2 D1
@ C370 100P_0402_50V8J
2
R392 1K_0402_5%
R391 10K_0402_5%
R385 10K_0402_5%
+3.3V_ALW
JTAG_TDI JTAG_TMS JTAG_CLK JTAG_TDO MSCLK MSDATA HOST_DEB_TX
2
1 @ R374
REM_DIODE1_P
+3.3V_ALW
R388 49.9_0402_1%
10 9 8 7 6 5 4 3 2 1
1
Place under CPU Place C266 close to the Q11 as possible
driven low when +3.3V_RUN is OFF; driven high when +3.3V_RUN is ON
JTAG_TDI JTAG_CLK MSCLK HOST_DEBUG_TX
A
10 9 8 7 6 5 4 3 2 1
1
<47>
DP1/DN1
10K_8P4R_5%
GND2 GND1
1
2
CARD_SMBDAT GPU_SMBDAT GPU_SMBCLK CARD_SMBCLK
+3.3V_ALW2
22U_0805_6.3V6M C7
5
Q5B DMN66D0LDW-7_SOT363-6
RUN_ON
RP1
12 11
<9>
5075 Channel Location
RUNPWROK
RUN_ON#
+3.3V_ALW
CONN@ JDEG1
1
2
MEC5075-LZY_DQFN132_11X11~D
Q5A DMN66D0LDW-7_SOT363-6
Place close pin A21
<26,36,39>
H=0.98
1
2
C283, C285, C286, C287 Place near U51
VSET_5075
R35 10K_0402_5%
R36 100K_0402_5%
2
+3.3V_ALW
EMI depop location(EMC)
8 7 6 5
2
R866 close to U51 at least 250mils
+PECI_VREF PECI_EC_R REM_DIODE1_N REM_DIODE1_P REM_DIODE2_N REM_DIODE2_P
+3.3V_RUN
C357 0.1U_0402_25V6
@ C363 4.7P_0402_50V8C
@ R382 10_0402_1%
R384 100_0402_1%
C362 1U_0402_6.3V6K
@SHORT PADS~D JTAG1 CONN@
1
Place close pin A29
R359
5075 Setting for Thermal Design
DOCK_POR_RST#
2
1
2.2K_0804_8P4R_5%
CONN@ JFAN1
1
R347
ESR <2ohms
CLK_PCI_MEC
1 2 3 4
2 1K_0402_5%
R367
Thermal diode mapping
2
2
R346
RP3
JTAG_RST#
1
DOCK_SMB_DAT 2.2K_0402_5% DOCK_SMB_CLK 2.2K_0402_5% DYN_TUR_CURRNT_SET# 100K_0402_5% LCD_SMBDAT 2.2K_0402_5% LCD_SMBCLK 2.2K_0402_5% BAY_SMBDAT 2.2K_0402_5% BAY_SMBCLK 2.2K_0402_5% DDR_HVREF_RST_GATE 100K_0402_5% THERMATRIP3# 100K_0402_5% DEVICE_DET# 100K_0402_5% HOST_DEBUG_RX 10K_0402_5%
<29> <29> 1
ACAV_IN ALWON POWER_SW_IN# DOCK_PWR_SW# VCI_IN2# POA_WAKE#
R375 B13 A13 B14 A14 A15 B16 A16 B17 B15 A17 A12 B34 A2 B29 A46 B61
2
<47> <47>
A59 A64 A60 B67 A63 B63 B68
2 1
<34> <34>
CHARGER_SMBDAT CHARGER_SMBCLK
1
XB use SA00005IH1L(S IC MEC5075-LZY-SAL00 DQFN 132P EC) 1
C366 4.7U_0603_6.3V6K
32 KHz Clock
DN1-THERM DP1-VREF_T DN2 DP2 DN3 DP3 DN4 DP4 VIN VSET VCP THERMTRIP2# GPIO002/THERMTRIP3# GPIO024/THSEL_STRAP PROCHOT_IN#/PROCHOT_IO# V_ISYS
DOCK_SMB_DAT DOCK_SMB_CLK
1
2
+3.3V_ALW
C360 0.1U_0402_25V6
1 R369
MSDATA 10K_0402_5% PCH_ALW_ON 100K_0402_5% DOCK_POR_RST# 100K_0402_5% EN_INVPWR 100K_0402_5% A_ON 100K_0402_5% RESET_OUT# 8.2K_0402_5% PCH_RSMRST# 10K_0402_5%
A43 B45 A42 B20 A18 B19 A20 B21 A19
DOCK_SMB_DAT DOCK_SMB_CLK LCD_SMBDAT LCD_SMBCLK BAY_SMBDAT BAY_SMBCLK GPU_SMBDAT GPU_SMBCLK CHARGER_SMBDAT CHARGER_SMBCLK CARD_SMBDAT CARD_SMBCLK USH_SMBDAT USH_SMBCLK
R370 100K_0402_5%
<36> BC_CLK_ECE5048 <36> BC_DAT_ECE5048 <36> BC_INT#_ECE5048 <47,48> ACAV_IN_NB <9> SIO_SLP_S5# <26> BEEP <38> BC_CLK_ECE1117 <38> BC_DAT_ECE1117 <38> BC_INT#_ECE1117
BC_CLK_ECE5048 BC_DAT_ECE5048 BC_INT#_ECE5048 ACAV_IN_NB SIO_SLP_S5# BEEP BC_CLK_ECE1117 BC_DAT_ECE1117 BC_INT#_ECE1117
GPIO003/I2C1A_DATA/GANG_MODE GPIO004/I2C1A_CLK/GANG_START GPIO005/I2C1B_DATA/BCM_B_DAT/GANG_STROBE GPIO006/I2C1B_CLK/BCM_B_CLK/GANG_FULL GPIO012/I2C1H_DATA/I2C2D_DATA/GANG_DATA1 GPIO013/I2C1H_CLK/I2C2D_CLK/GANG_DATA2 GPIO130/I2C2A_DATA/BCM_C_DAT GPIO131/I2C2A_CLK/BCM_C_CLK GPIO132/I2C1G_DATA GPIO140/I2C1G_CLK GPIO141/I2C1F_DATA/I2C2B_DATA GPIO142/I2C1F_CLK/I2C2B_CLK GPIO143/I2C1E_DATA GPIO144/I2C1E_CLK
2 10K_0402_5% VOL_DOWN_R R349 1 VOL_DOWN <40> DEVICE_DET# PS_ID PS_ID <41> ALW_PWRGD_3V_5V ALW_PWRGD_3V_5V <42> 1.05V_A_PWRGD 1.05V_A_PWRGD <44> 2 10K_0402_5% VOL_MUTE_R R352 1 VOL_MUTE <40> ME_SUS_PWR_ACK <9> 1.35V_SUS_PWRGD 1.35V_SUS_PWRGD <43> PM_APWROK PM_APWROK <9> RESET_OUT# RESET_OUT# <15,9> PCH_PCIE_WAKE# PCH_PCIE_WAKE# <9> PCH_RSMRST# PCH_RSMRST# <38> AC_PRESENT AC_PRESENT <12,9> SIO_PWRBTN# SIO_PWRBTN# <9>
2
1
2
R408
GPIO050/FAN_TACH1/GTACH GPIO051/FAN_TACH2 GPIO052/FAN_TACH3 GPIO053/PWM0 GPIO054/PWM1 GPIO055/PWM2 GPIO056/PWM3/GPWM
+RTC_CELL POA_WAKE# 100K_0402_5% VCI_IN2# 100K_0402_5%
2
1
@ R362
A_ON PCH_ALW_ON BIA_PWM_EC FAN1_PWM
Q9 @ L2N7002WT1G_SC-70-3
1
2
DOCK_POR_RST# <12> EC_WAKE# <39,44> A_ON <39> PCH_ALW_ON <22> BIA_PWM_EC
A3 B4 A4 B5 B7 A7 B48 B49 A47 B50 B52 A49 B53 A50
<47>
S
3
1
<34>
B22 A21 B23 B24 A23 B25 A24
<46,47,48,9>
1
2
@ R360
FAN1_TACH
D
2
1
@ R358
VOL_MUTE 100K_0402_5% VOL_DOWN 100K_0402_5% VOL_UP 100K_0402_5% FAN1_PWM 10K_0402_5% FAN1_TACH 10K_0402_5%
2 0_0402_5%
H_PROCHOT# D
2 G
FWP#
1
2
DYN_TUR_CURRNT_SET# SIO_SLP_S0# <9> MSDATA <31> MSCLK <31>
MSDATA MSCLK
1 @ R334
PROCHOT#_EC
2
1
A51 B55 B56 A53 A57
B57 B1 A55 A1 B28 B2 A8 B9 A9 B39 A44 B47 A54 B58
SYSTEM_ID BOARD_ID 2 10K_0402_5% VOL_UP_R R338 1 VOL_UP <40> LAN_WAKE# LAN_WAKE# <12,28> HOST_DEBUG_TX HOST_DEBUG_TX <31> HOST_DEBUG_RX RUNPWROK RUNPWROK <36,9> EN_INVPWR EN_INVPWR <22> PCH_SATA_MOD_EN# PAD~D T123 @ SLICE_PERF_EN <48> PCIE_WAKE# PCIE_WAKE# <31> DDR_HVREF_RST_GATE
1
+3.3V_RUN
JTAG_TDI JTAG_TDO JTAG_CLK JTAG_TMS JTAG_RST#
A10 B10 B8 B27 B44 B46 B26 A25 B36 B37 B38 A34 A35 A36 A40 B43 A45 B65
2
CLK_KBD 4.7K_0402_5% DAT_KBD 4.7K_0402_5% CLK_MSE 4.7K_0402_5% DAT_MSE 4.7K_0402_5%
EP
SML1_SMBDATA SML1_SMBCLK <38> CLK_TP_SIO <38> DAT_TP_SIO <34> CLK_KBD <34> DAT_KBD <34> CLK_MSE <34> DAT_MSE <41> PBAT_SMBDAT <41> PBAT_SMBCLK
A5 B6 A37 B40 A38 B41 A39 B42 B59 A56
H_VSS
2
<7> <7>
SML1_SMBDATA SML1_SMBCLK CLK_TP_SIO DAT_TP_SIO CLK_KBD DAT_KBD CLK_MSE DAT_MSE PBAT_SMBDAT PBAT_SMBCLK
C1
2
1
VSS_RO
2
1
B18
2
1
VR_CAP
2
1
B54
2
1
VSS_ADC
2
1 R357
2
@
VSS
2
1 R356
1
C351 0.1U_0402_25V6
1 R355
2
PAD-OPEN1x1m
C356 0.1U_0402_25V6
R354
1
2 C355 0.1U_0402_25V6
2
+5V_RUN
+3.3V_ALW_U38 PJP7 1
C350 0.1U_0402_25V6
2
A58 B3 A11 A26 B35 A41 A52
C354 0.1U_0402_25V6
2
+3.3V_ALW
2
GPIO021/RC_ID1 GPIO020/RC_ID2 GPIO014/GPTP-IN7/RC_ID3 H_VTR GPIO025/UART_CLK GPIO120/UART_TX GPIO124/GPTP-OUT5/UART_RX VTR_ADC VCC_PWRGD GPIO060/KBRST/BCM_B_INT# GPIO101/ECGP_SCLK/GANG_DATA5 VTR GPIO103/ECGP_MISO/GANG_DATA7 VTR GPIO105/ECGP_MOSI VTR GPIO102/BCM_C_INT#/GANG_DATA6 VTR GPIO104 VTR GPIO106 VTR GPIO116/MSDATA/V2P_COUT_LO/TAP_SEL_STRAP GPIO117/MSCLK/V2P_COUT_HI GPIO127/A20M NFWP GPIO007/I2C1D_DATA/PS2_CLK0B/I2C3A_DATA/GANG_BUSY GPIO010/I2C1D_CLK/PS2_DAT0B/I2C3A_CLK/GANG_ERROR GPIO110/PS2_CLK2/GPTP-IN6 GPIO156/LED0 GPIO111/PS2_DAT2/GPTP-OUT6 GPIO157/LED1 GPIO112/PS2_CLK1A GPIO153/LED2 GPIO113/PS2_DAT1A GPIO027/GPTP-OUT1 GPIO114/PS2_CLK0A GPIO026/GPTP-IN1 GPIO115/PS2_DAT0A GPIO001/ECSPI_CS1 GPIO154/I2C1C_DATA/PS2_CLK1B GPIO015/GPTP-OUT7/GANG_DATA3 GPIO155/I2C1C_CLK/PS2_DAT1B GPIO016/GPTP-IN8/GANG_DATA4 GPIO017/GPTP-OUT8 GPIO145/I2C1K_DATA/JTAG_TDI GPIO107/NRESET_OUT GPIO146/I2C1K_CLK/JTAG_TDO GPIO125/GPTP-IN5 GPIO147/I2C1J_DATA/I2C2C_DATA/JTAG_CLK GPIO126 GPIO150/I2C1J_CLK/I2C2C_CLK/JTAG_TMS GPIO151/GPTP-IN4 JTAG_RST# GPIO152/GPTP-OUT4
B11
2
C349 0.1U_0402_25V6
2
2
C348 10U_0603_6.3V6M
1
2
PCIE_WAKE# 10K_0402_5% BC_DAT_ECE5048 100K_0402_5% BC_DAT_ECE1117 100K_0402_5% PBAT_SMBDAT 2.2K_0402_5% PBAT_SMBCLK 2.2K_0402_5% CHARGER_SMBDAT 10K_0402_5% CHARGER_SMBCLK 10K_0402_5% change to 10K by vendor feedback
A22
VBAT
@ R342 100K_0402_5%
2 2
1
C347 1U_0402_6.3V4Z
+3.3V_ALW
C353 0.1U_0402_25V6
1
1 R340 1 R343 1 R344 1 R345 1 R339 1 R348 1 R350
B64
+3.3V_VTR_ADC
+VR_CAP B12
2 0_0402_5%
B60
1 @ R490
@ R335 10K_0402_5%
U38 +3.3V_ALW_U38
<34>
1
1 <40,9>
1
2
POWER_SW#_MB
2 10K_0402_5%
3
1
C352 1U_0402_6.3V4Z
2
C346 0.1U_0402_25V6
1
2
2
2
1
+3.3V_VTR
@ C342 1 2 1U_0402_6.3V6K 1 R330
DOCK_PWR_SW# C344 1U_0402_6.3V6K
2 0_0402_5%
2 10K_0402_5%
C343 1U_0402_6.3V6K
1 @ R336
+3.3V_ALW_U38
@ C340 1 2 1U_0402_6.3V6K
1 R329
POWER_SW_IN#
R328 100K_0402_5%
2
R327 100K_0402_5%
1
1
+RTC_CELL_VBAT C345 0.1U_0402_25V6
1 @ R332
+RTC_CELL
DELL CONFIDENTIAL/PROPRIETARY PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 2
Compal Electronics, Inc. Title
KBC & SIO MEC5075 Size
Document Number
Date:
Friday, May 17, 2013
Rev 0.3
LA-9431P 1
Sheet
37
of
59
5
4
3
2
1
<12>
I2C1_SCL_TCH_PAD <37>
DAT_TP_SIO
<37>
CLK_TP_SIO
2 0_0402_5% 2 0_0402_5% 2 0_0402_5% 2 0_0402_5%
<12,9>
1
TP_DATA TP_CLK 1
@
2
@
1
2
EMI depop location(EMC)
10P_0402_50V8J C380
10P_0402_50V8J C379
2
@
C378 10P_0402_50V8J
1
C377 10P_0402_50V8J
1 @ R450 1 @ R449 1 @ R441 1 @ R444
CONN@ JKBTP1
KB_DET#
18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
KB_DET#
2
I2C1_SDA_TCH_PAD
2
<12>
Touch Pad
R405 4.7K_0402_5%
D
R404 4.7K_0402_5%
1
+3.3V_TP
@
+5V_RUN +3.3V_ALW <37> BC_INT#_ECE1117 <37> BC_DAT_ECE1117 <37>
1
BC_CLK_ECE1117 +3.3V_TP
2
TP_DATA TP_CLK
GND2 GND1 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
Place close to JKBTP1 +3.3V_TP
+3.3V_ALW
1
2
+5V_RUN
1 @ C374 0.1U_0402_25V6
2
D
1 @ C375 0.1U_0402_25V6
@ C376 0.1U_0402_25V6
2
E-T_6718K-Y16N-01L
EMI depop location(EMC)
ST change to 6718K-Y16N-01L +3.3V_RUN
+3.3V_TP PJP8 1
2
C
C
PAD-OPEN1x1m
@ eDP Cable (30P Normal) Part Number
Description
DC02001PB00
H-CONN SET 0VM MB-EDP-LED-CAM
@ eDP Cable (40P Touch Screen) Part Number
Description
DC02001PA00
H-CONN SET 0VM MB-EDP-LED-CAM-TS
@ Sniffer cable Part Number DC02001P900
Description H-CONN SET 0VM MB-SNIFFER
@ TP_FFC
B
Part Number
Description
NBX0001CV00
FFC 16P F P0.5 PAD=0.3 104.4MM MB-KBTP
B
@ FP FFC Part Number NBX0001CX00
Description FFC 6P G P0.5 PAD=0.3 86.4MM USH/B-FP
@ USH FFC Part Number
RSMRST circuit +5V_ALW
2
RESET#
3
PCH_RSMRST#
5 1 2
RSMRST#
B
O A
GND
Part Number
U42
P
1 2
<37>
GC20323MX00
NBX0001CS00 4
Description BATT CR2032 3V 220MAH MAXELL
FFC 15P F P0.5 PAD=0.3 56.01MM MB-NFC @ Speak
0.1U_0402_25V6 EC SIDE
3
2
VCC
Part Number Description
@ Media Board FFC
G
C387 .01U_0402_16V7K
1
1
NBX0001CU00
@ C386 1 2
1 2
+5V_ALW_U41
@ RTC BATT
@ NFC board _FFC
+3.3V_ALW
R440
10K_0402_5%
U41
Description FFC 20P G P0.5 PAD=0.3 33.5MM MB-USH/B
Part Number
+3.3V_ALW
R411 33_0402_5%
NBX0001CT00
@ R414 @R414 0_0402_5% 1 2
1 @ R413
2 0_0402_5%
PCH_RSMRST#_Q
<9>
Description SPK PACK ZJX 2.0W 4 OHM FG
@ Battery bridge cable
NBX0001CR00
RT9818A-44GU3_SC70-3~D
PK230003Q0L
FFC 8P G P0.5 PAD=0.3 51.8MM MB-MEDIA/B
@ SIM Board FFC + Hall Sensor FFC Part Number
TC7SH08FU_SSOP5~D
Part Number Description
Part Number
Description
DC020014Z10
Description H-CONN SET 0FD M/B-BATTERY 9PIN
FFC 12P G P0.5 PAD=0.3 73.3MM MB-SIM+HALL/B @ UMA DC_IN wire cable
change to E4 solution
Part Number
A
DC30100BN0
Description A
CONN SET 0FD DCJACK-MB WDMD-DCE30004-DF
DELL CONFIDENTIAL/PROPRIETARY Compal Electronics, Inc. PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
KB/TP/RSMRST Size
Document Number
Date:
Friday, May 17, 2013
Rev 0.3
LA-9431P Sheet 1
38
of
59
5
4
3
2
1
DC/DC Interface
+3.3V_ALW_PCH/+1.05V_RUN source 1
+3.3V_ALW_PCH
PJP14 PAD-OPEN1x1m U43 1 2
+3.3V_ALW
<37>
+1.05V_MODPHY
5 6 7
+1.05V_M
GND
ON2
CT2
VIN2 VIN2
VOUT2 VOUT2
S
1 C390
1 C389
11 10
1
9 8
+1.05V_RUN_U43
C391
2 470P_0402_50V7K
15
2
2
1
PJP15
1
+1.05V_RUN
PAD-OPEN1x1m
C393 0.1U_0402_10V7K
2 1
2 0.1U_0402_10V7K
2 470P_0402_50V7K
TPS22966DPUR_SON14_2X3~D @R447 20K_0402_5% 2 1
C413 10U_0603_6.3V6M
+3.3V_ALW_PCH_U43
12
D
+3.3V_SUS/+3.3V_M source +3.3V_SUS 1
2
14 13
<36>
USH_PWR_ON
2 0_0402_5%
SIO_SLP_S4#
1 @ R421
2 0_0402_5%
1 2
1 @ R422
2 0_0402_5%
3
U45 <36,43,9>
<36,43>
SUS_ON
SIO_SLP_A#
G S
<37,44>
A_ON
1 @ R423
2 0_0402_5%
1 @ R424
2 0_0402_5%
VIN1 VIN1 ON1
4
+5V_ALW <36,44,9>
C
PJP16 PAD-OPEN1x1m
1 @ R439
VBIAS
5 6 7
+3.3V_ALW
VOUT1 VOUT1 CT1
CT2
VIN2 VIN2
VOUT2 VOUT2
14 13
+3.3V_SUS_U45
12
C397 1
2 470P_0402_50V7K
1 C396
C398 1
2 470P_0402_50V7K
2 0.1U_0402_10V7K
11
GND
ON2
2
3 4
RUN_ON
CT1
VBIAS
D 3
G
R445 10K_0402_5% 2 1
R442 100K_0402_5% 2 1 6 D
1
G
2 0_0402_5%
S
1 @ R420
D
MPHYP_PWR_EN
RUN_ON
ON1
4
+5V_ALW
VOUT1 VOUT1
GPAD
C412 2200P_0402_50V7K
<12>
<26,36,37>
SIO_SLP_S3#
VIN1 VIN1
3
4
1
DMN66D0LDW-7_SOT363-6 Q124A
MPHYP_PWR_EN# 5 DMN66D0LDW-7_SOT363-6 Q124B
2
6 5 2 1
1.05V_MODPHY_EN
C
SIO_SLP_S3#
2 0_0402_5% 2 0_0402_5% 2 0_0402_5%
Q125 +1.05V_M +1.05V_MODPHY SI3456DDV-T1-GE3_TSOP6
+5V_ALW
+3.3V_ALW2
PCH_ALW_ON
<36,43,9>
1 @ R416 1 @ R417 1 @ R418
2
D
10 9 8
2
+3.3V_M_U45
15
GPAD
1
PJP17
1
TPS22966DPUR_SON14_2X3~D
+3.3V_M
PAD-OPEN1x1m
C399 0.1U_0402_10V7K
2
+3.3V_RUN/+5V_RUN source +5V_RUN B
1
B
U46 1 SIO_SLP_S3# @ R425
2 0_0402_5%
1 @ R426
2 0_0402_5%
RUN_ON
1 2
+5V_ALW
3 4 5 6 7
+3.3V_ALW
VIN1 VIN1 ON1 VBIAS
VOUT1 VOUT1 CT1 GND
ON2
CT2
VIN2 VIN2
VOUT2 VOUT2 GPAD
2
PJP18 PAD-OPEN1x1m
14 13
+5V_RUN_U46
1 C400
12
C401 1
2 470P_0402_50V7K
C402 1
2 1000P_0402_50V7K
2 0.1U_0402_10V7K
11 10 9 8
2
+3.3V_RUN_U46
15
1
TPS22966DPUR_SON14_2X3~D 2
1
PJP19
+3.3V_RUN
PAD-OPEN1x1m
C403 0.1U_0402_10V7K
A
A
DELL CONFIDENTIAL/PROPRIETARY Compal Electronics, Inc. PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
POWER CONTROL Size
Document Number
Date:
Friday, May 17, 2013
Rev 0.3
LA-9431P Sheet 1
39
of
59
5
4
3
2
1
Q23A
D
2 W
3
4 Y
MASK_BASE_LEDS#
2
1 1
2 R429 330_0402_5%
D
BATT_WHITE_LED#
<22>
LED6 1 R430
2 SATA_LED 2 150_0402_5%
1
Q23B
LTW-193ZDS5_WHITE <36>
DMN66D0LDW-7_SOT363-6 1 6
R431 150_0402_5% 1 2
BAT1_LED#_Q
BATT_YELLOW_LED#
<22>
G
<22>
3
2
PANEL_HDD_LED#
BAT1_LED#
D
2 MASK_BASE_LEDS# RB751S40T1G_SOD523-2
S
1
1
BATT_WHITE# BATT_YELLOW#
MASK_SATA_LED# LED_SATA_DIAG_OUT#
2 150_0402_5%
G
S
3
1 R427
BAT2_LED#_Q
LTW-295DSKS-5A_YEL-WHITE
D24 <36>
DMN66D0LDW-7_SOT363-6 4 3
D
S
RB751S40T1G_SOD523-2
5 <36>
Q15 PDTA114EU_SC70-3
DMN66D0LDW-7_SOT363-6 1 6 2
2
BAT2_LED#
5
2
1
<36>
G
D
3
G
S
4
SATA_ACT#
LED7 Q24B
D23 <6>
+5V_ALW
+5V_ALW R428 10K_0402_5%
D
+5V_ALW
Battery LED
HDD LED solution for White LED
+3.3V_ALW
Q24A DMN66D0LDW-7_SOT363-6
1
D
MASK_BASE_LEDS#
R433 150_0402_5% 1 2
Q26 PDTA114EU_SC70-3
3
2
G
4
S
Q25A DMN66D0LDW-7_SOT363-6
G
5
BREATH_LED#
2
G
<34,36>
WLAN LED solution for White LED
+3.3V_ALW
1
1
2
BREATH_WHITE_LED_SNIFF
1 R434
2 150_0402_5%
LTW-193ZDS5_WHITE
Place LED1 close to SW1 LED(white) current need to reach 2mA, need to check current limit resistor 1 R436
2 330_0402_5%
BREATH_WHITE_LED#
<22>
D
3
Q16 PDTA114EU_SC70-3
6
2
2
G
S
1
WIRELESS_LED#
LED1
C
Q25B DMN66D0LDW-7_SOT363-6
2 <31,36>
MASK_BASE_LEDS#
+5V_ALW R432 100K_0402_5%
C
Breath LED +5V_ALW
Q28B DMN66D0LDW-7_SOT363-6 1 6 BREATH_LED#_Q D
SYS_LED_MASK#
2 220_0402_5%
S
1 R438
D
S
1
5
Q28A DMN66D0LDW-7_SOT363-6 4 3
1
MASK_BASE_LEDS#
LED5 1 R435
2 WLAN_LED 150_0402_5%
2
1 LTW-193ZDS5_WHITE
+3.3V_ALW
5
@ C404 1
SYS_LED_MASK#
1 2
U47
B A
O
4
MASK_BASE_LEDS#
MASK_BASE_LEDS#
<28>
TC7SH08FU_SSOP5~D
3
LID_CL#
P
SYS_LED_MASK# <31,36>
G
<36>
0.1U_0402_25V6 2
B
B
<37,9>
2
POWER_SW#_MB
SW1
1 <31,41>
@ JRTC1 1 2 1 G 2 G
+COINCELL
3 4
TYCO_2-1775293-2~D 4
3 SKRBAAE010_4P
POWER & INSTANT ON SWITCH
CONN@ JMEDIA
<37> <37> <37>
6 5 4 3 2 1
VOL_UP VOL_DOWN VOL_MUTE
LED Circuit Control Table
Fiducial Mark @ FD1 1
SYS_LED_MASK#
GND2 GND1 6 5 4 3 2 1
8 7
E-T_6718K-Y06N-01L
LID_CL#
FIDUCIAL MARK~D
Mask All LEDs (Sniffer Function) Mask Base MB LEDs (Lid Closed) Do not Mask LEDs (Lid Opened)
A
@ FD2 1 FIDUCIAL MARK~D
0 1 1
X 0 1
@ FD3 1
DELL CONFIDENTIAL/PROPRIETARY
FIDUCIAL MARK~D
5
4
Compal Electronics, Inc.
@ ST2 H_2P8 PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
1
@ ST1 CLIP_C5P1
1
1
1
1
1
1
1
@ H12 @ H13 @ H14 @ H15 @ H16 @ H17 @ H18 H_2P8 H_2P8 H_2P1 H_2P8 H_2P8 H_2P8 H_2P8
1
@ H11 H_3P4
1
@ H10 H_3P4
1
1
@ H8 @ H9 H_3P4 H_3P4
1
@ H5 H_2P3
1
@ H4 H_2P8
1
@ H3 H_2P8
1
@ H2 H_2P8
1
FIDUCIAL MARK~D
@ H1 H_2P8
1
@ FD4 1
A
ST update symbol to 6718K-Y06N-01L
3
2
Title
PAD & ME & LED Size
Document Number
Date:
Friday, May 17, 2013
Rev 0.3
LA-9431P Sheet 1
40
of
59
5
4
3
2
1
+COINCELL
1
COIN RTC Battery PR1 1K_0402_5%~D 2
+3.3V_RTC_LDO Z4012
+COINCELL
+COINCELL
<31,40>
+RTC_CELL
Primary Battery Connector
+3.3V_ALW
8 7 6 5
1
PC1 1U_0603_10V4Z~D
2
+PBATT PR2 2
100K_0402_5%~D
2
PRP2
1
@ PC2 0.1U_0603_25V7K~D
BAS40CW SOT-323
1
PL2 FBMJ4516HS720NT_2P~D 1 2
PBATT+_C LLTOP_ALLTOP C144LS-109A9-L 9P BATT P2 1 1 2 2 3 Z4304 3 4 Z4305 4 5 Z4306 5 6 6 7 7 8 8 9 9 10 GND 11 GND
PD3
PL1 FBMJ4516HS720NT_2P~D 1 2
3
2
PD2 TVNST52302AB0_SOT523-3
1
1
1 3
2
PD1 TVNST52302AB0_SOT523-3
1 2 3 4
PBAT_SMBCLK PBAT_SMBDAT
<37> <37> PBAT_PRES#
<36,48>
PQ1 ME2301D-G 1P SOT-23-3
100_0804_8P4R_5% PD4 2
1
3
3
1
1
PC3 2200P_0402_50V7K~D 2 1
2
D
3
D
DOCK_SMB_ALERT#
<34,36,48>
SDMK0340L-7-F_SOD323-2~D 2 2
@ PBATT1
@ PR6
GND
<34,36,48>
1
SLICE_BAT_PRES#
2 1
0_0402_5% PC4 2
C
C
1500P_0402_7K~D
+5V_ALW
PR7 1 2 0_0402_5%~D
S 2 G
2 PR10
PQ2 FDV301N_G_NL_SOT23-3~D
2
2
2.2K_0402_5%~D
PR9 33_0402_5%~D 1 2
3
D
1
1
DOCK_PSID
NO
IN
6
GPIO_PSID_SELECT
GND
V+
5
<36>
+5V_ALW
1
PL3 BLM15AG102SN1D_2P 2 1
NB_PSID
PU111 <34> PR8
1
PN: SM010028600
GND 2
@
change from 0603 to 0402 size
3
+3.3V_ALW @ PD5 DA204U_SOT323~D
3
NB_PSID_TS5A63157
NC
COM
4
PS_ID
<37>
TS5A63157DCKR_SC70-6~D
+5V_ALW 1
1
1
100K_0402_1%~D B
C
2 B
PQ3 MMST3904-7-F_SOT323~D
B
PR11 10K_0402_1%~D 2
2
3
E
PR12
@ PR13
15K_0402_1%~D 1
1
2
PSID_DISABLE#
<36>
10K_0402_5%~D
DC_IN+ Source +DC_IN_SS
1
PC10 2 1
10U_0805_25V6K
2 1 100K_0402_5%~D
1 @
PR15
PC8 2
1 2
PC7 @
0.1U_0603_25V7K~D
@ <48>
0.1U_0603_25V7K~D
SOFT_START_GC
2
1
4
<36,48>
A
PR18 2
PQ6A DCX124EK-7-F PNP/NPN_SC74-6~D
PC6
PR14 2
1M_0402_5%~D
1 AC_DIS
2
10K_0402_5%~D
0.1U_0603_25V7K~D
5
5
PR17 1 1
4
1
1 PR16 2 @
4.7K_0805_5%~D
1 @
6
PJP1
@ PJPDC1
PC11
2
2
+DCIN_JACK
@
0.1U_0603_25V7K~D
-DCIN_JACK
PD6
PC9 1000P_0603_50V7K~D 2 1
5 4 3 2 1
2
1 2 3
1M_0402_5%~D
2
DELL CONFIDENTIAL/PROPRIETARY
1
PAD-OPEN 1x3m
Compal Electronics, Inc.
PC12 @ 2
A
5 4 3 2 1
VZ0603M260APT_0603
PQ6B 1
ACES_50299-00501-003 7 GND 6 GND
PQ4 FDMC6679AZ_MLP8-5
+DC_IN PC5 0.022U_0805_50V7K~D 1 2
3
PL4 FBMJ4516HS720NT_2P~D 1 2
DCX124EK-7-F PNP/NPN_SC74-6~D
+DC_IN
Title
0.1U_0603_25V7K~D
5
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4
3
2
+DCIN Size
Document Number
Date:
Friday, May 17, 2013
Rev 0.3
LA-9591P Sheet 1
41
of
58
A
B
C
D
E
+3.3V_RTC_LDO 1
1
+3.3V_ALW2
PR102 10K_0402_5%~D 1 2
PR104 10K_0402_5%~D 2 1
<37>
2
1
@ ALW_PWRGD_3V_5V PR105
PAD-OPEN 1x3m
1
0_0402_5%
VCLK 10
TPS51285BRUKR QFN 20P DRVH2 DRVH1
9
VBST2
1 2 3
BST_3V
UG_5V
17
BST_5V
18
SW1
PC110 0.1U_0603_25V7K 1 2
DRVL1
EN1
PL102 3.3UH_ETQP3W3R3WFN_7A_20% 1 2
1 2
4
3
+DC1_PWR_SRC
FDMC7692S_POWER33-8-5
1
PC114 @ 680P_0603_50V7K
1 + 2
@
PR112 @ 2
1 2 3 2
@ PR111 4.7_1206_5%
PQ103 3 2 1
FDMC7692S_POWER33-8-5
PC118 4.7U_0603_10V6K 2 1
PQ102
3VALWP TDC 6.7 A Peak Current 8.1 A OCP Current 9.72 A Rds(on): 13.6m ohm (max)
PC115 330U_D_6.3VM_R25M
5 EN
LG_5V
4
2
+5V_ALWP
15
20
VREG5
VIN
13
LG_3V
2
FDMC8884_POWER33-8-5
1
@ PC111 680P_0603_50V7K
PC117 0.1U_0603_25V7K 2 1
+
@
PQ101
5
12
SW1
@
4 PR109 2.2_0603_5% 1 2
2
1
1
1
PC113 330U_D_6.3VM_R25M
2
PC112 @
0.1U_0603_25V7K
11
SW2
DRVL2
PL101 2.2UH_ETQP3W2R2WFN_8.5A_20% 2 1
+3.3V_ALWP
8
16
@
3 2 1
VBST1 SW2
PR114 200_0402_1% 1
1
PR110 2.2_0603_5% 1 2
2
PC116 0.1U_0603_25V7K
UG_3V PC109 0.1U_0603_25V7K 1 2
19
2
4
PQ100 FDMC8884_POWER33-8-5
14
5
CS1
PGOOD
PC103 10U_0805_25V6K 2 1
7
PGOOD_3V_5V
21
PC102 10U_0805_25V6K 2 1
1
2 VFB1
3
VO1
PC106 2200P_0402_50V7K 2 1
2
PAD
PC101 0.1U_0402_25V6 2 1
1
4
1
@ PR108
@
EN2
VREG3
6
EN
VFB2
5
1 2
PU100
PR107 100K_0402_1%~D 5
PC104 10U_0805_25V6K 2 1
@
PC107 10U_0805_25V6K 2 1
+PWR_SRC
PC105 2200P_0402_50V7K 2 1
PC108 0.1U_0402_25V6 2 1
@
16.9K_0402_1%
+3.3V_ALW
PL100 1UH_PCMB053T-1R0MS_7A_20% 2 1
2
+DC1_PWR_SRC
PR106
20K_0402_1%~D
+DC1_PWR_SRC
CS2
1
2
PJP100
PC100 4.7U_0603_10V6K 2 1
PR103 0_0402_5% 2
PR101 15K_0402_1% 2 1
2
@
PR100 6.49K_0402_1%~D 1 2
4.7_1206_5%
3
+5V_ALW2
EN
<37>
ALWON
2
@ PR113
PJP101
1
+5V_ALWP
0_0402_5%
1
2
+5V_ALW
5VALWP TDC 4.88 A Peak Current 6.89 A OCP Current 8.268 A Rds(on):13.6m ohm (max)
PAD-OPEN 1x3m PJP102
+3.3V_ALWP
1
2
+3.3V_ALW
PC119 1U_0603_10V6K 2 1
PAD-OPEN 1x3m
@
4
4
Compal Electronics, Inc. Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: A
B
C
D
+5V_ALW/3.3V_ALW Document Number
Rev 0.3
LA-9591P Friday, May 17, 2013
Sheet E
42
of
58
5
4
3
2
1
1.35Volt +/- 5% TDC: 7.2 A Peak Current: 10 A OCP current: 12 A Rds(on): 13.6m ohm(max) +PWR_SRC
0.75Volt +/- 5% TDC 0.525A Peak Current 0.75A OCP Current 0.9A
PJP200
2
D
1
1.35V_B+
D
PJP201 PR200 1 2 2.2_0603_5%~D
PAD-OPEN 1x2m~D
BOOT_1.35V
+VLDOIN_1.35V
2
+1.35V_MEN_P
1
PQ200
1 2 3
PR201 23.7K_0402_1% 1 2
13 PC209 1U_0603_10V6K~D
5
1
VTTSNS
2
21
12
1 2
CS
GND
+V_DDR_REF
RT8207MZQW _W QFN20_3X3
VDDP
VTTREF
3 4
+V_DDR_REF
PR202
1 2 3
1U_0603_10V6K~D
+5V_ALW
FB 1.35V_FB
2
PR204 100K_0402_1%~D
PC213 100P_0402_50V8J~D 2 1
2 <37>
1.35V_SUS_PW RGD
PC212 0.033U_0402_16V7~D
PR205 8.06K_0402_1%~D 2 1
1 @ PR203 4.7_1206_5%
C
FB sense trace when FB pull down to GND
1
+3.3V_ALW
+1.35V_MEN_P
5
6
PC211
FDMC7692S_POW ER33-8-5
VDDQ S3
VDD
S5
11
7
VDD_1.35V
8
2
5.1_0603_5%~D
TON
+5V_ALW
9
1 4 PQ201
PGOOD
680P_0603_50V7K
PC205 22U_0805_6.3V6M
19
18
20 VTT
PAD
VTTGND
PGND
10
1
PU11
CS_1.35V
@ PC208
SNUB_1.35V 2
2
PC207 330U_D2_2VM_R15M
+
C
14
LGATE
VLDOIN
15
BOOT
4
FDMC8884_POW ER33-8-5 PL200 1UH_PCMB063T-1R0MS_12A_20% 1 2
16
DL_1.35V
17
SW _1.35V
UGATE
+1.35V_MEN_P
1
+0.675V_P
PHASE
2 1
PC204
5
1 2
@
0.22U_0603_16V7K~D
@
PC203 2200P_0402_50V7K~D
1 2
PC202 0.1U_0402_25V6
1 2
PC201 4.7U_0805_25V6K~D
2
1
PC200 4.7U_0805_25V6K~D
PAD-OPEN1x1m DH_1.35V
1.35V_SUS_PW RGD PR206
SIO_SLP_S4#
1
1.35V_B+
2
1M_0402_1%~D
S5_1.35V
PR209 10K_0402_1%
@ PR208
1
2 0_0402_5%
1
<18>
1
0.675V_DDR_VTT_ON
2
0.1U_0402_16V7K~D <36,39,9>
Mode S5 S3 S0
S3 L L H
S5 L H H
+1.5V_MEN off on on
+V_DDR_REF off on on
@ PC214 0.1U_0402_16V7K~D
2
0_0402_5%
@ PC215
B
@ PR210
2
SUS_ON
1
<36,39>
1
2
<36,39,9>
@ PR207 0_0402_5%~D 1 2
B
@ PR211 1 2 0_0402_5%~D
SIO_SLP_S3#
+0.75V_P off off(Hi-Z) on
+1.35V_MEN_P
FB sense trace PJP203
2
2
1
1
JUMP_1x3m
+1.35V_MEN_P
PJP204
2
2
1
1
PJP202
+1.35V_MEM
+0.675V_P
JUMP_1x3m
2
+0.675V_DDR_VTT
1 PAD-OPEN1x1m
A
A
DELL CONFIDENTIAL/PROPRIETARY Compal Electronics, Inc. Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5
4
3
2
+1.35V_MEN/+0.675V_DDR_VTT Size
Document Number
Date:
Friday, May 17, 2013
Rev 0.3
LA-9591P Sheet 1
43
of
58
5
4
3
2
1
PJP300 2
+V1.05SP_B+
1
+PWR_SRC
PR301 2.2_0603_5% 1 2
PU300
0_0402_5%~D
3
FB_+V1.05SP
4
RF_+V1.05SP
5
VBST
TRIP
DRVH
EN
SW
VFB
V5IN
RF
DRVL TP
C
@ PR304 <37,39>
1
A_ON
10
UG_+V1.05SP
8
SW_+V1.05SP
6 11
4 PQ301 FDMC7692S_POWER33-8-5
1
10U_0805_25V
PC307 C
220U_B2_2.5VM_R15M
@ PR306
3 2 1 1
+
680P_0603_50V7K 2
4.7_1206_5%
2
2
2
470K_0402_1%
@ PC308
1 @ PC306
PC305 1U_0402_6.3V6K~D
PR305
0.1U_0402_16V7K
+1.05V_MP
+5V_ALW LG_+V1.05SP
1
0_0402_5%
PL300 2.2UH_ETQP3W2R2WFN_8.5A_20% 1 2
7
TPS51212DSCR_SON10_3X3 2
4.7U_0805_25V6K~D PC303 2 1
BST_+V1.05SP
9
1
SIO_SLP_A#
S0 mode be high level
EN_+V1.05SP
PGOOD
2
<36,39,9>
@ PR303 1 2
2
5
95.3K_0402_1%
TRIP_+V1.05SP
PQ300 FDMC8884_POWER33-8-5
1
PR302 2
2
1 1
@
D
1
1.05V_A_PWRGD
PC304 0.1U_0603_25V7K 1 2 3 2 1
2
100K_0402_1%~D
<37>
@
@ 4
PR300
PC302 2
1
PC300 2
5
+3.3V_ALW
2200P_0402_50V7K
1
D
0.1U_0402_25V6 PC301 2 1
PAD-OPEN 1x2m~D
PR307 2
1
4.99K_0402_1%
2
+1.05Volt +/- 5% TDC 3.67 A Peak Current 5.25 A OCP current 6.3 A Rds(on): 13.6m ohm (max)
B
PR308 10K_0402_1% 1
PJP301
+1.05V_MP
2
+1.05V_M
1
B
PAD-OPEN 1x2m~D
DELL CONFIDENTIAL/PROPRIETARY
A
A
Compal Electronics, Inc. Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
+1.05V_M Size
4
3
2
Rev 0.3
LA-9591P Date:
5
Document Number Friday, May 17, 2013
Sheet 1
44
of
58
5
4
3
2
1
+3.3V_RUN +3.3V_ALW D
1
+5V_ALW
1
D
PJP400
@ PJP402
2
2
PC400 1U_0402_6.3V6K
PAD-OPEN1x1m
PU400
1
1
1 PR402 1.54K_0402_1%
APL5930KAI-TRG_SO8
+1.5V_THERMAL
PC403 0.01U_0402_25V7K
1
VIN
9
1 PAD-OPEN1x1m
PC404 22U_0805_6.3V6M
2
47K_0402_5%
0.1U_0402_16V7K
2
PJP401
2
1.5VSP
2
@ PC402
2
@ PR401
FB
PC401 4.7U_0805_6.3V6K
3
2
1
1
100K_0402_5%~D
EN
4
2
8
GND
2
5
1
VIN VOUT VOUT
1
1
PR400
POK
2
7
+3.3V_RUN
VCNTL
6
2
1
PAD-OPEN1x1m
PR403 1.74K_0402_1%
C
2
C
B
B
A
A
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
Deciphered Date
Title
+1.05VS_VTTP/+1.0VSP
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
5
4
3
2
Rev 0.3
Chief River VC
Friday, May 17, 2013
Sheet 1
45
of
58
5
4
3
2
1
20120911 TI-Alex Note: Although there is no pulse-overlap in 1-phase mode, during USR, the pulse comes in immediately. So, the problem with PR504 = DNP is that if there is a high ripple, and USR is faultily detected, you will get a double-pulse. So, we want to make sure USR is not active if it is not necessary. So, I moved it all the way to highest level so PR504 works to 8.87k.
VREF
2 1 PR504
+PWR_SRC
PWM1
8 7 6 5 4 3 2 1
@ PR539 2 0_0402_5% 1
@ PR513 1 2 75_0402_1%
2 1
@ PR516
2
1.91K_0402_1%~D
H_VR_READY
<15>
IMVP_PWRGD
<36>
@ PR540
1 0_0402_5%
+3.3V_RUN PU501
1
+5V_RUN
PR512 2.1K_0402_1%~D 2 1
1
PC511 0.1U_0402_25V6
VIDSCLK
<15>
VIDALERT_N
<15>
VIDSOUT
PR514 43.2K_0402_1% 2 1
1 2
PR529 110_0402_1%
1 2
PR528 75_0402_1%
1 2
1 2 <15>
PR527 54.9_0402_1%
B
@
CSP1
<15>
VCCSENSE
2
@ PR531 0_0402_5% 1
VFB
2
@ PR532 0_0402_5% 1
GFB
from processor <17>
VSSSENSE
1 2 PC502 0.068U_0402_16V7K
+1.05V_VCCST
C
2
PH501 10K_0402_1%_TSM0A103F34D1RZ
H_PROCHOT#
PC509 1U_0603_10V7K~D
3
PR515 3.01K_0402_1% 2 1 2
2 1 PC514
<37,47,48,9>
2
PC510 1U_0603_10V7K~D
1
PR526 10_0603_1%
2
+5V_ALW
@
TI recommend 1nF
CSD97374CQ4M_SON8_3P5X4P5
VIDALERT_N
1
2
PR534 0_0402_5%
PC507 1 2 0.33U_0603_10V7K~D PC512 1500P_0402_50V7K 2 1
1 PR535 4.87K_0402_1%
VIDSCLK
2
VREF
+VCC_CORE PL500 0.22UH_FDUE0640J-H-R22M=P3_25A_20% 4 1
4 3 @PR520 @ PR520 2 0_0402_5% 1SKIP#1 1 2 SKIP#
47P_0402_50V8J~D
1 PR523 2 10K_0402_5%~D
1VR_HOT#
2.32K_0402_1%
100P_0402_50V8~D
6 5
PGND2 PWM BOOT VSW PGND1 BOOT_R VDD VIN SKIP#
PC508 2
1
2
9 8 7
2
2
PC503 1000P_0402_50V7K~D 1 2
PC505 1U_0603_10V6K
1
PR521
1 2 0.1U_0402_25V6 2 1 PR517 0_0603_5%~D
1
1_0603_5%
TPS51622RSM
PC504
PWM1
+3.3V_RUN
PC513 0.068U_0402_16V7K
1
1
PR519
4.7_1206_5%~D
2
1 2 PR522
DROP COMP VREF V5A GND VR_HOT# VCLK ALERT# GND 25 26 27 28 29 30 31 32 33 @ PC506 1 2
PC738
SKIP#
VR_ON SKIP# PWM1 PWM2 N/C PGOOD VDD VDIO
C
<36>
+
2
820P_0603_50V7K~D
CSP1 CSN1 CSN2 CSP2 PU3 N/C GFB VFB
2
<15>
IMVP_VR_ON
VIDSOUT
17 18 19 20 21 22 23 24 VFB
GFB
VBAT SLEWA THERM IMON OCP-I B-RAMP F-IMAX O-USR
CSN1
@
1
2
PU500
H_VR_EN
2 1 @ PR537 0_0402_5%
16 15 14 13 12 11 10 9
CSP1
+
100U_D3L_20VM_R55M
10K_0402_5%~D
+3.3V_RUN +3.3V_RUN
1 2 FBMA-L11-453215-121LMA90T
@ PR536 2 0_0402_5%1
PC735
2
1
33U_D_25VM_R60M
PR511
PL501
PC734 10U_0805_25V6K 2 1
1
+VCC_PWR_SRC
PC732 22U_0805_25V6K 2 1
+VCC_PWR_SRC
2
PAD-OPEN 4x4m
PC731 10U_0805_25V6K 2 1
@ PJP500
1
PC736 22U_0805_25V6K 2 1
PR509
2
D
1
1
PR508
2
O-USR 150K_0402_1%
2 PR507
1
150K_0402_1%
8.87K_0402_1%
PR503 1 2 1M_0402_1%
2 PR502
1
75_0402_1%
2 PR501
1
365K_0402_1%
PC500 1 2
2
F-IMAX
1
PR510 39K_0402_5%~D
B-RAMP
1 PR506
2
SLEWA
@
OCP-I 75K_0402_1%
D
PC501 0.1U_0402_16V7K~D 2 1
PR505 10K_0402_5%~D 1 2
1
2
@ PR500 75_0402_1%
4700P_0603_50V7K
2
PH500
IMON
150K_0402_1%
1
100K_0402_1%_NCP15WF104F03RC
B
CSN1
CPU TDC 10 A Peak Current 32 A OCP Current 38.4 A DCR: 0.82m +-5% ohm PH500 B value: 4250k 1% PH501 B value: 3435k 1%
A
A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc. Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5
4
3
2
+VCC_CORE Size
Document Number
Date:
Friday, May 17, 2013
Rev 0.3
LA-9591P Sheet 1
46
of
58
4
+SDC_IN
PR745 10_1206_5%~D 2 1
1 16
REGN
BQ24715_REGN
ACDET
PHASE
18
SDA
LODRV
SCL
GND
2 4
CHG_UGATE
19
15
CHG_LGATE
14
CELL
/BATDRV
4
BQ24715RGRR_QFN 2
PQ706
10K_0402_1%~D SIRA06DP-T1-GE3_POWERPAKSO-8
@ PR751
GNDA_CHG GNDA_CHG
GNDA_CHG
1
1
TC7SH08FU_SSOP5~D 5
ACAV_IN
PQ712B 4
Adapter Protection Circuit for Turbo Mode
<37,47,48>
DMN66D0LDW-7 2N SOT363-6
PR739 10K_0402_1%~D 2 1
PU2B
P
8 +
7
1 1
G
O -
LM393DR_SO8~D
@ PR741
ACAV_IN_NB
2
<37,48>
0_0402_5% A
2
<36>
3
PROCHOT_GATE
PC730 100P_0402_50V8J~D 2 1
2
A
6
4
PR737 232K_0402_1%~D 2 1
+5V_ALW
5
3
A
PR736 1M_0402_1%~D 1 2
5 P
1
B
O G
1
PR740 100K_0402_5%~D
PR742 22.6K_0402_1%~D 2 1
3
PU3 4
PC728 0.1U_0402_25V4Z~D 1
PC729 100P_0402_50V8J~D 2 1
1
2
2
DYN_TUR_CURRNT_SET#
+DC_IN +3.3V_ALW +3.3V_ALW 1
220P_0402_50V8J
5
2
2 @ PC740
4
LM393DR_SO8~D 1
4
1
6
8 1 2
PC727 220P_0402_50V8J~D
PC726 100P_0402_50V8J~D 2 1
PR735 69.8K_0402_1% 2 1
PR734 210K_0402_1% 1 6 2 <37>
-
BQ24715_REGN
+3.3V_ALW2
PU2A O
2
PQ712A DMN66D0LDW-7 2N SOT363-6
+
P
3
DMN66D0LDW-7 2N SOT363-6 PQ710B
2
PR732 20K_0402_1%~D 1 2
@ PR728 0_0402_5%
PQ710A DMN66D0LDW-7 2N SOT363-6
VCP
B
2
221K_0402_1%~D PR729 1.8M_0402_1% 1 2
G
PR730 150K_0402_1%
<48>
<37,46,48,9>
2
PR727
H_PROCHOT#
@
2
PC724 100P_0402_50V8J~D 2 1
PC725 0.01U_0402_25V7K~D 2 1
Low
2
PAD-OPEN1x1m
10K_0402_1%~D
1
65W
@
+5V_ALW
PC722 1
2
BATDRV#
+3.3V_ALW2
PC721 0.1U_0603_25V7K~D 1 2
0.1U_0603_25V7K~D
PJP701 1
+5V_ALW
High
@
2
B
DYN_TUR_CURRENT_SET#
@
PR744
1
+3.3V_ALW2
2 0_0402_5%
2
10K_0402_1%~D
1
CHARGER_CELL_PIN
3
@
@ PC720 0.1U_0603_25V7K~D 1 2
PR738 48.7K_0402_1% 2 1
<48>
@PR750 @ PR750
PR724 1
GNDA_CHG
PR722 4.02K_0402_1% 1 2
11
3 2 1
PR711
2
SRN
2
IOUT
10K_0402_1%~D BQ24715_REGN 1
12
4.7_1206_5%~D
10
1
5 @ PR726 2
TP
1
1
13
21
2
PC719 100P_0402_50V8J~D
V_SYS
4
PR718 0_0402_5%
SRP
10U_0805_25V6K 1 2
ACOK
PC716 2 1
5
PC737 10U_0805_25V6K 2 1
2
+VCHGR
PR716 0.01_1206_1%~D
PL701
GNDA_CHG
45W
+PWR_SRC
3.3UH_FDVE1040-H-3R3M=P3_11.3A_20%~D 2 1
1
PR746 121K_0402_1%~D 2 1
C
PQ704 SIRA14DP-T1GE3_POWERPAK-SO8-5
PC718 10U_0805_25V6K 2 1
HIDRV
PC717 10U_0805_25V6K 2 1
ACDRV
PR715 2.2_0603_5% 1 2
PC742 22U_0805_25V6M 2 1
BTST
PC741 22U_0805_25V6M 2 1
17
CMSRC
PC715 0.1U_0603_25V7K~D 2 1
9
7
GNDA_CHG
<48>
PR719 0_0402_5% 1 2
8
+3.3V_ALW
CSSP_1
1U_0603_10V6K~D PD702 BAT54HT1G_SOD323-2~D
0_0402_5%
<37>
1
1
PR705 1 2
3
PR704 10_0402_5%~D 1 CSSP_1
3
DK_CSS_GC
PR743 42.2K_0402_1%~D 2 1
@ PR717
1
Discrete current monitor circuit 2
PC712 22U_0805_25V6M 2 1
4
6
1
PR749
59_0402_1%
0.1U_0603_25V7K~D
1
1
2
VCC
BQ24715_REGN
ACAV_IN
4
INA199A1DCKR_SC70-6~D
@ PR709
PC714 820P_0603_50V7K~D
PR747 100K_0402_1%~D 1
PC733
2 <37,47,48>
IN+
2
<34>
PC711 22U_0805_25V6M 2 1
3
1
CHARGER_SMBCLK
IN-
V+
0_0402_5%
0.1U_0402_25V6
<37>
GND
5
2
GNDA_CHG
CHARGER_SMBDAT
DOCK_DCIN_IS-
3
PC709 1 2 2
20
+DCIN
0_0402_5%
<37>
+SDC_IN
4
PR748 44.2_0402_1%~D 2 1
5
3 2 1
2 PC708 C
PU700
@ PR725
1
PC705 1 2
6
GNDA_CHG GNDA_CHG
+SDC_IN 1
1
2
1
PR713 261K_0402_1% PR714 49.9K_0402_1%~D 2
PQ703B SI3993CDV-T1-GE3_TSOP6~D
0.1U_0603_25V7K~D
ACN
2
PC706 10U_0805_25V6K 2 1
PC704 0.1U_0603_25V7K~D 1 2
ACP
+SDC_IN
2
PC703 1U_0603_25V6K 1 2
Out
<34> 2
D
2
1_0805_1%~D
DOCK_DCIN_IS+
G
1
+CHGR_DC_IN
REF
CSSN_1
6
S
<48>
@ PR708
5
D
BAT54CW_SOT323~D
S
PR703 10K_0402_5%~D 2 1
1
PQ703A SI3993CDV-T1-GE3_TSOP6~D
G
1 3
D
PU703
S
S
PQ702 NTR4502PT1G_SOT23-3~D
2
+DC_IN_SS
1
PQ701 NTR4502PT1G_SOT23-3~D
2 G PD701
@ PR710 0_0402_5% 2
VCP
D 2 G D
PR707 100K_0402_1%~D 2 1
2
0_0402_5%
+DOCK_PWR_BAR
sense adapter
PC713 0.047U_0603_25V7M 2 1
CSS_GC
2
<37>
PR706 100K_0402_1%~D 1
<48>
PAD-OPEN 4x4m
2
0_0402_5% D
1
2
3
<48> @ PR702 1
1
3
CSSN_1
DC_BLOCK_GC
CHAGER_SRC
PJP700
4
10_0402_5%~D
2
2
@ PR701 1
@
1
@
1
4
PR700 0.01_1206_1%~D
1
1 2 3
5
+DC_IN_SS
2
PL700 1UH_PCMB042T-1R0MS_4.5A_20% 2 1
+PWR_SRC_AC
V30415-T1-GE3 1P POWERPAK1212-8
PC700 0.1U_0603_25V7K~D
PQ700
3
PC707 2200P_0402_50V7K~D 2 1
5
DELL CONFIDENTIAL/PROPRIETARY Compal Electronics, Inc. Title
+GPU_CORE THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5
4
3
2
Size
Document Number
Date:
Friday, May 17, 2013
Rev 0.3
LA-9591P Sheet 1
47
of
58
O
+3.3V_ALW
1
A
PQ802A DMN66D0LDW-7 2N_SOT363-6~D
2
+PWR_SRC_AC
6 2
1
2 1
8 7 6 5
3301_DSCHRG_FET_GC 3
<36,48>
4 B A
6 1
6
PU804
TC7SH08FU_SSOP5~D
1 @ PR812 2
DIS_BAT_PROCHOT#
4
O
2
PQ805A DMN66D0LDW-7 2N_SOT363-6~D
2
@ PD818 SDMK0340L-7-F_SOD323-2~D 1
2
CHARGER_CELL_PIN
<47>
0_0402_5%
+DOCK_PWR_BAR 5
2
PC811 0.01U_0603_25V7K~D
<36>
2
PR814 330K_0402_5%~D 2 1
1
SLICE_BAT_ON
PQ810 FDS6679AZ-G_SO8~D
2
5
PR821 820_0603_5%~D 1 2
4
STSTART_DCBLOCK_GC
1 2 3 1 PD808 PDS5100H-13_POWERDI5-3~D
PQ812B DMN66D0LDW-7 2N_SOT363-6~D 4 3
PBAT_PRES#
4
1
PBAT_PRES#
DMN66D0LDW-7 2N_SOT363-6~D
5
SLICE_BAT_ON
PQ806A
4
FDS6679AZ-G_SO8~D
+3.3V_ALW PC805 0.1U_0402_10V7K 1 2
1
2200P_0402_50V7K~D PC807 @ PR811 1 2 2 1 0_0402_5% 0.47U_0805_25V7K~D
<34,36,41,48>
5
SLICE_BAT_PRES#
P
5
2
3
2 DMN66D0LDW-7 2N_SOT363-6~D PQ807B
G
PR817
3
4
1
330K_0402_5%~D
3
8 7 6 5
1
1 2 3
D
0.1U_0603_25V7K~D PC806 1 2
PQ811
+PBATT
PR816 100K_0402_5%~D
PQ805B DMN66D0LDW-7 2N_SOT363-6~D
5
PR810 100K_0402_5%~D
PQ806B
2
1
2
DMN66D0LDW-7 2N_SOT363-6~D
DMN66D0LDW-7 2N_SOT363-6~D PQ807A
2
+3.3V_ALW2
<37,46,47,9>
1 PR807 100K_0402_5%~D
+3.3V_ALW PC803 1 2
H_PROCHOT#
3
TC7SH08FU_SSOP5~D
PR808
+3.3V_ALW
6 4
3
2
1
B
2
SLICE_BAT_ON
1
4
PR804 100K_0402_5%~D
2 1
<36,41>
1
SLICE_BAT_PRES#
PU801
+3.3V_ALW2
PQ812A DMN66D0LDW-7 2N_SOT363-6~D
PR801 100K_0402_5%~D 2 1 5
2
+NBDOCK_DC_IN_SS
PR802 100K_0402_5%~D
PC801 0.1U_0402_10V7K 1 2
100K_0402_5%~D PR815 10K_0402_5%~D
2 2
1
PR813 100K_0402_5%~D 1 2 PD811
1
6
BATDRV#
3
1
4 <47>
SDMK0340L-7-F_SOD323-2~D
PQ800 SI4835DDY-T1-GE3_SO8~D 1 8 2 7 3 6 5
1
PQ809 SI4835DDY-T1-GE3_SO8~D 1 8 2 7 3 6 5
1
+3.3V_ALW
Purpose: Trigger PROCHOT# when active battery is removed from system. Allows EC to re-establish system performance for battery next in line.
2
+VCHGR
2
1
D
PD800 PDS5100H-13_POWERDI5-3~D 3 1 2
+PBATT_IN_SS
2
PQ801 NTR4502PT1G 1P SOT23-3 3
+BATT_SUM
3
PD807 SDMK0340L-7-F_SOD323-2~D
P
4
PD806 PDS5100H-13_POWERDI5-3~D 3 1 2
G
5
PQ826 FDMC6679AZ_MLP8-5
+3.3V_ALW2
5 P
1 3
3
A
TP
ERC3
ERC2
CSS_GC DK_CSS_GC
@ PR868 1
2
0_0402_5%
@
STSTART_DCBLOCK_GC @ PR877 1 2 0_0402_5%
2
1
6
3
PQ818
1 1
1 3
1
+3.3V_ALW2
3
S
1
D
1
PR837 100K_0402_5%~D
3
PC814 0.1U_0402_10V7K 2 1
2 G
+3.3V_ALW2
1 5
1 4
+PBATT
B A
O 3
DOCK_DET#
1 2
SLICE_BAT_PRES# DOCK_DET#
<34,36,41,48> <34,36,48>
PR864 100K_0402_5%~D
PU808 TC7SH08FU_SSOP5~D
2
2
P
1 3
2
G
2
<36>
@ PR869 1
ACAV_IN#
<37,47,48> 1
2
240K_0402_5%~D @ PR856
D
2 G S
3301_PWRSRC
2
3 1
2
EN_DOCK_PWR_BAR
0_0402_5%~D 2 1
PQ827 @ DMN65D8LW-7_SOT323-3~D
DOCK_DET#
<34,36,48>
<37,48>
+3.3V_ALW2
B
<34,36,41,48>
PQ831
2 2
@ PQ823 ME2301D-G 1P SOT-23-3
+3.3V_ALW
PR874 1 2 1M_0402_5%~D
3
5 <34,36,41,48>
3 @ PR866 0_0402_5% 1
2 P33ALW
SLICE_PERF_EN <34,36,48>
SLICE_BAT_PRES#
DMN65D8LW-7_SOT323-3~D
1
<36> <37,48>
2
@ PR834 2
1M_0402_5%~D SLICE_BAT_PRES#
@ PR863 1 2 0_0402_5%
CD3301BRHHR_QFN36_6X6~D
2
PR853 0_0402_5% 1 2
2 1
0_0402_5%~D
PR848 1 1 @ PR860 0_0402_5% 2
PQ822 NTR4502PT1G 1P SOT23-3
+DC_IN_SS
<37,47>
DOCK_AC_OFF_EC PR858
1
ACAV_IN
@ PR870 1
2
D
S
2 G
@ PQ824A DMN66D0LDW-7 2N_SOT363-6~D 1 6
2
47K_0402_5%~D 1
@ PR872
0_0402_5% PQ825 DMN65D8LW-7_SOT323-3~D
+NBDOCK_DC_IN_SS
EN_DK_PWRBAR PC817 0.1U_0402_25V4Z~D 2 1
PC816 0.047U_0603_25V7M 2 1
PC815 0.1U_0603_25V7K~D 2 1
<47> <47>
ACAV_IN_NB
1 2 @ PR857 0_0402_5%
<37,48>
PD821 SDMK0340L-7-F_SOD323-2~D
PR836 100K_0402_5%~D
@ PR852 0_0402_5%
2
A
@ PR851 0_0402_5%~D
@ PR855 0_0402_5% 1 2
1
10 11 12 13 14 15 16 17 18
37
3301_ACAV_IN_NB DK_AC_OFF_EN SL_BAT_PRES#
1
2 2
1 PR840 2 100K_0402_5%~D
1
@ PR862 1 2 0_0402_5%
DK_AC_OFF
3
+3.3V_ALW2
@ PR859 1 2 0_0402_5%
27 26 25 24 23 22 21 20 19
SLICE_PERF_EN
@ PQ819A DMN66D0LDW-7 2N_SOT363-6~D
1
ACAV_IN
P50ALW PBATT_OFF DK_AC_OFF_EN ACAV_IN_NB GND DK_AC_OFF_EN SL_BAT_PRES# BLKNG_MOSFET_GC NBDK_DCINSS
<36,48>
SDMK0340L-7-F_SOD323-2~D
DMN65D8LW-7_SOT323-3~D
+3.3V_ALW2
SLICE_BAT_ON
ACAV_IN#
3
<37,47,48>
DC_BLOCK_GC
DC_IN SS_GC ERC1 ACAVDK_SRC GND SDC_IN DC_BLK_GC ACAV_IN P33ALW2
@PR850 @ PR850 2 0_0402_5%
2
5
2
@ PQ824B
@ PR875 100K_0402_5%~D
4
A
DMN66D0LDW-7 2N_SOT363-6~D 3
5
0_0402_5% CD3301_SDC_IN
<47>
1 2 3 4 5 6 7 8 ACAVIN P33ALW2 9
+5V_ALW
PD816
PQ828
2
ERC1
1 CD_PBATT_OFF
BAT54CW_SOT323~D
@
0_0402_5%
1
@ PR854 1 2
3
@ PR843 0_0402_5% 2
1
2 G S
1
PQ821A DMN66D0LDW-7 2N_SOT363-6~D PR839 1 6 2 1 100K_0402_5%~D DOCK_AC_OFF <34> PQ821B DMN66D0LDW-7 2N_SOT363-6~D 4 3 PR849 @ PR844 2 1 10K_0402_5%~D 100K_0402_5%~D
2
+SDC_IN
@ PR847 1 2ACAVDK_SRC 0_0402_5%
1
+PBATT P50ALW
2
@ PR861 0_0402_5%
DOCK_DET#
2
ACAV_DOCK_SRC#
SLICE_PERF_EN <34,36,48>
<34,36,41>
D
+NBDOCK_DC_IN_SS
<34,36,41,48>
1
100K_0402_5%~D <34>
PU800
1
0_0402_5%
NC CHARGERVR_DCIN DC_IN_SS DK_PWRBAR GND NC BLK_MOSFET_GC DSCHRG_MOSFET_GC PBatt+
PR846 <41>1 SOFT_START_GC 2
2
@PR838 @ PR838
CSS_GC DK_CSS_GC ERC3 ERC2 GND PWR_SRC SS_DCBLK_GC EN_DK_PWRBAR P33ALW
+3.3V_ALW2
<37,48> PD815 2
36 35 34 33 32 31 30 29 28
2
PC813 0.1U_0603_50V4Z~D
SLICE_BAT_PRES# 1 2
@
0_0402_5%
1
1
47_0805_5%~D
@
3
2 @ PR833 0_0402_5%
CD3301_DCIN
+DOCK_PWR_BAR
1 3301_DSCHRG_FET_GC
2
1
+CHGR_DC_IN
DSCHRG_MOSFET_GC
2
CHGVR_DCIN DC_IN_SS DK_PWRBAR
PR835
1
100K_0402_5%~D
<36,48>
DMN65D8LW-7_SOT323-3~D
3
PR827 1 2 100K_0402_5%~D
G
<47>
+DC_IN
@ 2 PR841
100K_0402_5%~D
PQ819B DMN66D0LDW-7 2N_SOT363-6~D
G
SLICE_BAT_ON 1 @ PR825 2
2
3 1
2 2
5
+3.3V_ALW2
1
1
DOCK_SMB_ALERT#
3
PR829
D
+DC_IN_SS
PR824 @
1
1
B
O
for Slice battery discharge without AC exist
PR823
S
@ PR831 0_0402_5% 1 2
B
+3.3V_ALW2 Purpose: Turn on the PQ817
+3.3V_ALW2 2
3
4
PD819 SDMK0340L-7-F_SOD323-2~D 1 2
NTR4502PT1G_SOT23-3~D PQ830
2
1
PQ813B DMN66D0LDW-7 2N_SOT363-6~D 4 3
3
S
1
<34,36,48>
1
PR822
PU807 TC7SH08FU_SSOP5~D
C
+3.3V_ALW2
2 DOCK_DET# G PQ817 DMN65D8LW-7_SOT323-3~D
S
PC812 0.1U_0402_10V7K 2 1 PD814 SDMK0340L-7-F_SOD323-2~D 1 2
100K_0402_5%~D
100K_0402_5%~D @ PR832 0_0402_5% 2 1
PR819 2
D
1 @ PR820 2 ACAV_IN#
2
+3.3V_ALW2
PQ814 NTR4502PT1G 1P SOT23-3
2 D PQ832 DMN65D8LW-7_SOT323-3~D
2 G
6 2
PR826
2
PR828 1 2 10K_0402_5%~D
AC_DIS
1
<36,41>
1
0_0402_5% PQ813A DMN66D0LDW-7 2N_SOT363-6~D 1
3
<34,36,41,48>
PD820 SDMK0340L-7-F_SOD323-2~D 1 2 SLICE_BAT_PRES#
SLICE_BAT_PRES#
2
3
5
1
0_0402_5%
2 G
2
2
PR830 100K_0402_5%~D
A
100K_0402_5%~D
1
S
SDMK0340L-7-F_SOD323-2~D 1
A
B
O
D
PD813
1
B
O
Purpose: Turn on the PQ817 for primary or module bay battery to provide power to dock side without AC exist. <34,36,41,48>
5
3
@ PR895 0_0402_5%
4
SDMK0340L-7-F_SOD323-2~D
P
2
1
3
1
+3.3V_ALW
1
PQ829 SI2301CDS-T1-GE3 1P_SOT23-3
0_0402_5%~D
2
P
1 2
4
0.1U_0402_10V7K
2
1
+3.3V_ALW2
PQ816 AO3418_SOT23-3
8 7 6 5
FDS6679AZ-G_SO8~D
@ PR894
1 PD810
2 1 10K_0402_5%~D
1 2 3
4
PQ815
PC810 2 1 PU806 TC7SH08FU_SSOP5~D
G
2 1
PR818
2
@ PC809 1500P_0402_7K~D
100K_0402_5%~D
C
G
1 2 3
PC808 0.1U_0402_10V7K 2 1 PU805 TC7SH08FU_SSOP5~D
+3.3V_ALW2
4
4
SLICE_PERF_EN
+PWR_SRC_AC
DELL CONFIDENTIAL/PROPRIETARY Compal Electronics, Inc. PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
5
4
3
2
Title
Selector Size
Document Number
Date:
Friday, May 17, 2013
Rev 0.3
LA-9591P 1
Sheet
48
of
58
5
4
3
2
1
Based on PDDG rev 0.7 Table 5-1.
+VCC_CORE
D
D
1
2
1 PC900 22U_0805_6.3V6M
1
2
1 PC905 22U_0805_6.3V6M
1
2
2
1 PC901 @ 22U_0805_6.3V6M
2
1 PC906 22U_0805_6.3V6M
1 PC910 @ 22U_0805_6.3V6M
2
2
1 PC902 @ 22U_0805_6.3V6M
2
1 PC907 @ 22U_0805_6.3V6M
1 PC911 @ 22U_0805_6.3V6M
2
2
1 PC903 22U_0805_6.3V6M
2
1 PC908 22U_0805_6.3V6M
1 PC912 22U_0805_6.3V6M
2
2
PC904 22U_0805_6.3V6M
2
PC909 22U_0805_6.3V6M
1 PC913 22U_0805_6.3V6M
2
PC914 22U_0805_6.3V6M
C
C
1
2
1 PC915 22U_0805_6.3V6M
1
2
1 PC920 22U_0805_6.3V6M
1
2
2
1 PC916 22U_0805_6.3V6M
2
1 PC921 22U_0805_6.3V6M
1 PC925 22U_0805_6.3V6M
2
2
1 PC917 22U_0805_6.3V6M
2
1 PC922 22U_0805_6.3V6M
1 PC926 22U_0805_6.3V6M
2
2
1 PC918 @ 22U_0805_6.3V6M
2
2
PC919 @ 22U_0805_6.3V6M
1 PC923 @ 22U_0805_6.3V6M
1 PC927 22U_0805_6.3V6M
2
2
PC924 @ 22U_0805_6.3V6M
1 PC928 22U_0805_6.3V6M
2
PC929 22U_0805_6.3V6M
B
B
A
A
DELL CONFIDENTIAL/PROPRIETARY Compal Electronics, Inc. Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5
4
3
2
PROCESSOR DECOUPLING Size
Document Number
Date:
Friday, May 17, 2013
Rev 0.3
LA-9591P Sheet 1
49
of
58
5
4
3
V ersion Change L ist ( P. I. R . L ist ) Item Page# 1
Title
P45
1.5VSP
D ate 8/17
R equest O w ner Compal
2
1
Page 1
Issue D escription Base power budget request, add 1.5V powre rail
Solution D escription
R ev.
Add PU400
D
D
2
P42
+5V/+3.3V
8/17
Compal
reserver PR114 for TPS51282 application
ADD @PR114
3
P47
Charger
8/17
Compal
EC can't detect charger IC cause can't charger
modify SMBus net for correct connect
4
P46
Vcore
8/17
Compal
schematic control error cause can't set OCP
add Vref net for correct connect
5
P48
Selector
8/17
Compal
in order to meet latest multi-battery request
change control signal for meet E5 request
6
P43
1.35V/0.675V
8/17
Compal
chagne OCP setting
change PR201 from 20k to 24.9k.
7
P42
+5V/+3.3V
10/22
Compal
Reserve 0ohm for 3v5v enable debug
Change PR113 from SD03420018L (S RES 1/16W 2K +-1% 0402) to SD028000080 (S RES 1/16W 0 +-5% 0402)
8
P44
+1.05V_MP
10/22
Compal
+1.05V_MP EA for ripple portion can't meet spec. 31.5mv, after change from 1u to 2.2u test is pass
9
P42
+5V/+3.3V
10/22
Compal
Original 3v5v IC -TPS51225 can't support 2cell battery follow TI suggestion, When TPS51285A/B is used, please update the below four components. 1)VREG5 cap to 4.7uF 2)VREG3 cap to 4.7uF 3)CS1 resistor to 1/5 of the Tps51275’s value 4)CS2 resistor to 1/5 of the Tps51275’s value 5)VCLK connection (when not be used): add 200-ohm to GND
C
X01 C
Change PL300 from SH00000PJ00 (S COIL 1UH +-20% PCMB063T-1R0MS 12A) X01 to SH00000MR00 (S COIL 2.2UH +-20% ETQP3W2R2WFN 8.5A) Change PU100 from SA00005LS00 (S IC TPS51225CRUKR QFN 20P PWM) to SA000064T00 (S IC TPS51285BRUKR QFN 20P PWM)
X01
1)2)Change PC118(VREG5 Cap) and PC100(VREG3 Cap) from SE080105K80(S CER CAP 1U 10V K X5R 0603) to SE00000MA00(S CER CAP 4.7U 10V K X5R 0603) 3) Change PR106(for CS1) from SD03484528L (S RES 1/16W 84.5K +-1% 0402) to SD034169280 (S RES 1/16W 16.9K +-1% 0402) 4) Change PR105(for CS2) from SD03410038L (S RES 1/16W 100K +-1% 0402) to SD034200280 (S RES 1/16W 20K +-1% 0402) 5) Add
B
10
P47 P48
Charger Selector
10/22
Compal
To avoid HW and Power SMT materials can't entirely replace
11
P47
Charger
10/22
Compal
follow E5- Salado 14"15" schematic
12
P46
Vcore
11/02
Compal
follow TI suggestion modify setting value to meet Intel VR12.6(ULV) validation EA 1) Imon 2) Loadline 3) transient
PR114 SD034200080(S RES 1/16W 200 +-1% 0402)
Change PU3,PU801,PU804,PU805,PU806,PU807 from SA74108040L(S IC 74AHC1G08GW SOT353 AND) to SA00708012L(S IC TC7SH08FU SSOP 5P AND)
X01
1) @PQ819, @PQ824 2) EMI request for add PL700 SH00000IW00(S COIL 1UH +-20% PCMB042T-1R0MS 4.5A) 1) Change PR501 from SD034422380 (S RES 1/16W 422K +-1% 0402) to SD034365380 (S RES 1/16W 365K +-1% 0402)
X01
B
X01
2) Change PR521 from SD000009M80 (S RES 1/16W 2.61K +-1% 0402) to SD00000WS8L(S RES 1/16W 2.32K +-1% 0402) 3) @PC506 100p_0402 and change PR535 from SD02810028L(S RES 1/16W 10K +-5% 0402) to SD034487100 (S RES 1/16W 4.87K +-1% 0402 (LF))
A
A
DELL CONFIDENTIAL/PROPRIETARY Compal Electronics, Inc. Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PWR_PIR 1 Size
4
3
2
Rev 0.3
LA-9591P Date:
5
Document Number Friday, May 17, 2013
Sheet 1
50
of
58
5
4
3
V ersion Change L ist ( P. I. R . L ist ) Item Page# 13
Title
P47
Charger
D ate
R equest O w ner
11/05 Compal
D
2
Page 1
Issue D escription 1) TI suggestion BQ24715 cell pin pull high 3.3V change to V_regn(6v) for sequence issue 2) Reserve 0 ohm for debug
14
+5V/+3.3V
P42
11/05
Compal
1
Solution D escription
R ev.
1) Change PR711 from SD02800008L (S RES 1/16W 0 +-5% 0402) to SD034100280 (S RES 1/16W 10K +-1% 0402) ,add PR750 SD028000080(S RES 1/16W 0 +-5% 0402)
X01 D
2) Add @PR751
follow E5- Salado 14"15" schematic
1) @PR863, @PR870, @PR869, @PR824, @PR875, @PQ823
X01
2) Add @PR848, @PR851 and add PR834, PR852, PR853, all is SD028000080(S RES 1/16W 0 +-5% 0402) 3) Add PR874 SD028100480(S RES 1/16W 1M +-5% 0402) 4) Add PD819 SCS0340L01L(S SCH DIO SDMK0340L-7-F SOD-323)
15
P47
Charger
11/05
Compal
16
P47
Charger
11/05
Compal
17
P44
+1.05VTTP
11/05
18
P48
+5V/+3.3V
11/05
Improve charger efficiency
Change PR715 from SD028200A80 (S RES 1/16W 20 +-5% 0402) to SD013220B80 (S RES 1/10W 2.2 +-5% 0603)
follow E5- Salado 14"15" schematic
Delete @PR731, @PR733, @PU702
X01
C
C
1.35V/0.675V +1.05V_MP B
19
P48
Selector
11/15
Compal Support QAD WCEPTA analysis, to modify 1.05 OCP Rtrip -QAD team resistance to 95K, Cpk value will pass specification. -Huang.Hanks (PCP)
Compal - EMC team Wen. Andy
Compal
EMC team suggestion
follow E5- Salado 14"15" schematic for undock shutdown issue
X01
Change PR302 from SD00000H880 (S RES 1/16W 54.9K +-1% 0402) to SD034953280 (S RES 1/16W 95.3K +-1% 0402 )
X01
@PC105, @PC203, @PC301
X01
Add PQ827 SB00000UO00 (S TR DMN65D8LW-7 1N SOT323-3), @PR856 SD028000080 (S RES 1/16W 0 +-5% 0402), PQ816 SB534020000 (S TR AO3402 1N SOT-23), PQ828 SB00000UO00 (S TR DMN65D8LW-7 1N SOT323-3), PR861 SD028000080 (S RES 1/16W 0 +-5% 0402)
X01
B
PR802, PR827, PR840 change from SD028240380 (S RES 1/16W 240K +-5% 0402) to SD028470280 (S RES 1/16W 47K +-5% 0402), PR804, PR826, PR839 change from SD028470280 (S RES 1/16W 47K +-5% 0402), to SD028240380 (S RES 1/16W 240K +-5% 0402)
20
P47
Charger
P48
Selector
P41
+DCIN
Change PR713 from SD034294380 (S RES 1/16W 294K +-1% 0402) to SD034261380 (S RES 1/16W 261K +-1% 0402)
12/12 Compal
A
21
2013 Compal/01/11 ESD team
ESD team's PD1 vendor(NXP) proposal PD1 pin 5 connected to the VCC (5V or 3.3V).
X01
@PR844 PD1 pin5 connect to +3.3V_ALW
A
X01_2
DELL CONFIDENTIAL/PROPRIETARY Compal Electronics, Inc. Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PWR_PIR 2 Size
4
3
2
Rev 0.3
LA-9591P Date:
5
Document Number Friday, May 17, 2013
Sheet 1
51
of
58
5
4
3
V ersion Change L ist ( P. I. R . L ist ) Title
D ate
R equest O w ner
Selector
2013/ 01/23
Compal
Item Page# 22
P48
D
2
1
Page 1
Issue D escription To avoid +DOCK_PWR_BAR leakage voltage when system only with main battery
Solution D escription
R ev.
1). Add PU808 P/N: SA007080120 (S IC TC7SH08FU SSOP 5P AND)
X01_2 D
2). Add PQ830 P/N: SB000007900 (S TR NTR4502PT1G 1P SOT23-3) 3). Add PQ831 P/N: SB00000UO00 (S TR DMN65D8LW-7 1N SOT323-3) 4). Add PD821 P/N: SCS0340L010 (S SCH DIO SDMK0340L-7-F SOD-323) 5). Add PR836, PR837 P/N: SD028100380 (S RES 1/16W 100K +-5% 0402) 6). Add PC814 P/N: SE102104K00 (S CER CAP 0.1U 10V +-10% X7R 0402)
23
P41
+DCIN
C
24
P48
Selector
2013 Compal /02/07
PPM-Jovins_Chang and Sourcer-Willie_Zeng highlight SB000009N8L will shortage after 2013/05
2013/ Compal 02/18
Change PQ6 From : SB000009N8L (S TR IMD2AT-108 PNP/NPN SC74-62) To : SB000009P80 (TR DCX124EK-7-F PNP/NPN SC74R-6)
X02
GPIO net - AC_DIS# is high active. Corrent net name.
1). Change PQ6A.5 and PR828.1 net name from AC_DIS# to AC_DIS
X02
AC_DIS circuit modify to improve output voltage level.
2). Add PQ829 P/N: SB00000H500 , PQ832 P/N: SB00000UO00 , PD820 P/N: SCS0340L010 , @PR894 , PR895 P/N: SD028000080
C
(S TR SI2301CDS-T1-GE3 1P SOT23-3) (S TR DMN65D8LW-7 1N SOT323-3) (S SCH DIO SDMK0340L-7-F SOD-323) (S RES 1/16W 0 +-5% 0402)
3). modify PR828,PR830 4). Delete PQ820 5). Delete PL5, add PJP1
B
25
P41
+DCIN
2013/ Compal-ME 02/18
26
P48
Selector
2013/ Compal 02/18
layout spec limit
P46 P48
Vcore Selector
2013/ Compal02/18 ESD team Hsu. Matt
Add snubber component by ESD team request
27
DFX highlight Battery connetor(locattion:PBATT1) hard to insert.
B
Battery connetor(locattion:PBATT1) footprint follow ME team Iris requesti to change from SUYIN_200277GR009M262ZR_9P-T to ALLTO_C144LS-109A9-L_9P-T
X02
Delete PD817, modify PD815 footprint same as PD701, from SDMK0340L-7-F_SOD323-2 to RB717F_SOT323-3 Add PC508, PC714 P/N:SE025821K80 (S CER CAP 820P 50V K X7R 0603) PR522, PR724 P/N:SD001470B80 (S RES 1/4W 4.7 +-5% 1206 )
X02 X02
A
A
DELL CONFIDENTIAL/PROPRIETARY Compal Electronics, Inc. Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PWR_PIR 3 Size
4
3
2
Rev 0.3
LA-9431P Date:
5
Document Number Friday, May 17, 2013
Sheet 1
52
of
58
5
4
3
V ersion Change L ist ( P. I. R . L ist ) Title
D ate
R equest O w ner
Selector
2013/ 02/21
Compal
Item Page# 28
P48
D
2
1
Page 1
Issue D escription
Solution D escription
follow E5- Salado 14"15" schematic
1). Change PC703 from 0.1U to 1U P/N: SE000006900 (S CER CAP 1UF 25V K X5R 0603)
1) For Input current sense stablilze
2). Change PC706 from 1U to 0.1U P/N: SE00000QK00 (S CER CAP 10U 25V K X5R 0805 H1.25)
2) To provent charger into sleep mode dual AC transient.
3). Change PC708 from 0.01U to 10U P/N: SE00000G880 (S CER CAP 0.1U 25V K X5R 0402)
4) Adapter protect rating setting 5) Fine tune H_PROCHOT# response time. 6) Improve ACAV_IN_NB ref voltage accuracy. 7) Improve current sense accuracy.
C
4). Change PR734 P/N: SD034210380 Change PR735 P/N: SD034698280
Vcore
2013/ Compal02/26 ESD team Hsu. Matt
Add 22U_0805 by ESD team request
from 100K ohm to 210K ohm (S RES 1/16W 210K +-1% 0402) from 46.4K ohm to 69.8K ohm (S RES 1/16W 69.8K +-1% 0402)
5). Add @PC740 6). Change PR738.pin1 from BQ24715_REGN connect to +3.3V_ALW2. Change PR738 from 118K ohm to 48.7K ohm P/N: SD034487280 (S RES 1/16W 48.7K +1% 0402) Change PR744 from 12K ohm to 10K ohm P/N: SD034100280 (S RES 1/16W 10K +-1% 7). Change PR748 P/N: SD034442A80 Change PR749 P/N: SD00000W200
P46
X02 D
3) Fine tune ACOK response time.
29
R ev.
C
from 6.8 ohm to 210K ohm (S RES 1/16W 44.2 +-1% 0402) from 10 ohm to 69.8K ohm (S RES 1/16W 59 +-1% 0402)
X02
Change PC732, PC736 from 10U to 22U from P/N: SE00000QK00 (S CER CAP 10U 25V K X5R 0805 H1.25) to P/N: SE00000XH80 (S CER CAP 22U 25V M X5R 0805 H1.25)
B
B
30
Selector
P48
2013/ Compal 02/27
Modify resistor value to meet voltage tolerence
X02
1). Change PR802,PR827,PR840 from 47K ohm to 100K P/N: SD028100380 (S RES 1/16W 100K +-5% 0402) 2). Change PR804,PR826,PR839 from 240K to 100K P/N: SD028100380 (S RES 1/16W 100K +-5% 0402)
31
P47
Charger
2013/ Compal 03/18
follow E5- Salado 14"15" schematic to add charger input MLCC to 88u
1). Add PC741, PC742 P/N: SE00000XH80 (S CER CAP 22U 25V M X5R 0805 H1.25)
X02_1
2). Due to space limit, so delete @PC701, @PC702, @PC710
A
32
P42 P43 P44
+5V/+3.3V 1.35V/0.675V +1.05V_MP
2013/ Compal 03/20
support DFX team change choke layout pad to avoid soldering issue
1). Change PL101, PL102, PL200, PL300 change from CYNTE_PCMC063T-2R2MN_2P to CYNTE_PCMB064T-3R3MS_2P
33
P46
Vcore
2013/ Compal 03/21
Support acoustic team to reduce noise
3). Change PC738 X02_1 from 33U(SGA00005M00) to 100U P/N: SGA00008R00 (S POLY C 100U 20V M D ESR55M (D3L_H=2.8mm) DELL CONFIDENTIAL/PROPRIETARY
PCB FootPrint
X02_1
Compal Electronics, Inc. Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PWR_PIR 4 Size
4
3
2
Rev 0.3
LA-9431P Date:
5
Document Number Friday, May 17, 2013
Sheet 1
53
of
58
A
5
4
3
2
1
V ersion Change L ist ( P. I. R . L ist ) Item Page# D
1
22,40,38 26,34
2 3 4
Title
D ate
ESD
11/05/2012
27
Safty
37
HW
22,40,38 26
HW
R equest O w ner
A
Solution D escription
R ev.
COMPAL
ESD team request
Remove D3,D27,D22,DE1,DE2 Reserve D20
0.2(X01)
11/05/2012
COMPAL
Safty team request
Pop F2 and reserve R160
0.2(X01)
11/05/2012
COMPAL
Based on align E5,P5 Fan module pin define
Swap JFAN1 pin define
0.2(X01)
11/06/2012
COMPAL
To avoid PT phase occurs ESD issue and change back ESD request
Reserve D3,D27,D22,DE1,DE2
0.2(X01)
5
40 36
HW
11/08/2012
DELL
DELL drop Media LED function
Remove backlight LED function and change connector to 6pin
0.2(X01)
6
26
HW
11/09/2012
COMPAL
Remove EMI solution at Speaker side
Remove R132, R133, R134 and R135
0.2(X01)
7
12,22,37
HW
11/09/2012
DELL
DELL drop ALS function
Remove ALS interface from EC and CPU side than move touch screen signal to eDP side
0.2(X01)
8
22
HW
11/09/2012
COMPAL
change Webcam power enable from PCH
pop R106 and de-pop R102
0.2(X01)
9
10
HW
11/09/2012
COMPAL
Schmatic error and remove eDP backlight control pull up resistor
Remove RC150
0.2(X01)
C
B
Issue D escription
C
10
39
HW
11/12/2012
COMPAL
+1.05V_MODPHY can't meet INTEL timing spec
change +1.05V_MODPHY to MOS solution
0.2(X01)
11
18 19
HW
11/12/2012
COMPAL
Remove DIMM VERF power rail from power side
Remove RD2, RD4, RD8 and RD9
0.2(X01)
12
27
HW
11/12/2012
COMPAL
change miniDP OCP solution
remove D10 R160 F2 and add U50 de-pop C383
0.2(X01)
13
26
HW
11/12/2012
COMPAL
refer salado 14" to change PCBEEP circuit
remove C132,C146,R146,R138,C133 and C143 than add C145,C146,R147,R151 and de-pop R194 R153
0.2(X01)
14
26
HW
11/12/2012
COMPAL
If doesn't has external power, Sleeve will be floating mode and no reference GND.
Add AUD_NB_MUTE# to control Sleeve pin.
0.2(X01)
15
37
HW
11/12/2012
COMPAL
Change board ID to X01
change R392 form 240K to 130Kohm
0.2(X01) 0.2(X01)
COMPAL
Vendor update schematic for power saving
change +1.05V_RUN_VMM power enable signal from LP_EN to DOCKED and add +3.3V_RUN_VMM for DP2320 series 3.3V power rail remove L3 and move U6.E5 to +1.05V_VMM_VDD power rail change U6.J4 to +3.3V_RUN_VDDA R85 change to 3.74K_1% remove LP_EN, R232 and U6A.A5 to NC remove R55 and pop-option R207 when use VMM2310
16
21
HW
11/12/2012
B
17
21
HW
11/12/2012
COMPAL
change VMM2320 config
remove DP to VGA PTN3392 circuit and add 0ohm pop option for 2320 config 0.2(X01)
18
22
HW
11/13/2012
COMPAL
Add Mic power and remove DBC function
Add 3.3V_RUN for Mic power and remove DBC function at JeDP.2
0.2(X01)
19
19
HW
11/13/2012
COMPAL
refer PDG1.0 to change SODIMM control circuit resistor
change RC68, RC126 and RC173 from 2.2 to 2ohm 1% change RC67,RC69,RC130,RC132,RC217 and RC221 from 1.82K to 1.8Kohm 1%
0.2(X01)
20
37,36,12
HW
11/13/2012
COMPAL
GPIO map update to 2.7 version
Move EC_WAKE# from ECE5048[L]5 to MEC5075 GPIO52. Change name: 1.5V_SUS_PWRGD to 1.35V_SUS_PWRGD for DDR3L. Add NFC_DET# ECE5048 GPIOL[5] to NFC moudle & add R38 PU
0.2(X01)
21
20,27,29 ,38,40
ME
11/13/2012
COMPAL
ME change connector
change JmDP1,JNFC1,JMEDIA,JKBTP1,JUSH1
0.2(X01)
22
24
HW
11/14/2012
COMPAL
Vendor update schematic for power saving
align AUX/DDC SW voltage with DP Hub to +3.3V_RUN_VMM
0.2(X01)
DELL CONFIDENTIAL/PROPRIETARY Compal Electronics, Inc. Title PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 5
4
3
D
2
EE P.I.R (1/6) Size
Document Number
Date:
Friday, May 17, 2013
Rev 0.3
LA-9431P Sheet 1
54
of
59
A
5
4
3
2
1
V ersion Change L ist ( P. I. R . L ist ) Item Page# D
23
Title
2,3,6,34
HW
D ate 11/15/2012
R equest O w ner
Issue D escription
COMPAL
update SATA topology fro Mainstream CPU
Solution D escription
R ev.
exchange SATA1&SATA2 topology
0.2(X01)
24
12
HW
11/15/2012
COMPAL
Add LAN_WAKE# T-topology
Pop RC301 to link LAN_WAKE# and EC_WAKE#
0.2(X01)
25
15
HW
11/15/2012
COMPAL
remove RC252 for cost saving
change RC252 to PJP11(1mm jumper-short)
0.2(X01)
26
16
HW
11/15/2012
INTEL
MOW_WW46 request change for VCCUSB3PLL and VCCSATA3PLL
change CC42 and CC49 from 1u_0402 to 22u_0603 change CC76 and CC77 from 100u_1206 to 22u_0603
0.2(X01)
HW
11/15/2012
COMPAL
change AND gate to same source
Change U20, U26, U29 and U30 from SA74108040L to SA00708012L
0.2(X01)
27
20,28,30,31
28
34
ME
11/15/2012
COMPAL
ME change Docking connector
change JDOCK1 that Pin145 from PWR1 to GND1 & Pin148 from PWR2 to GND2
0.2(X01)
29
38,12
HW
11/15/2012
COMPAL
remove +3.3V_TP power load switch solution
remove U40, R458,C424 and C423
0.2(X01) 0.2(X01)
30
22
HW
11/15/2012
COMPAL
change LCDVDD power control circuit
change U9 from TPS22966 to APL3512 solution
31
31,32
HW
11/15/2012
COMPAL
remove TPS22965 solution
remove U51(TPS22965) and U34(TPS22965) than add U3(TPS22966)
0.2(X01)
32
10,27
HW
11/15/2012
COMPAL
ESD solution for black screen issue
Add CC450 on EDP_CPU_HPD to GND and C451 on DPC_HPD to GND
0.2(X01)
33
40
ME
11/16/2012
COMPAL
ME change drawing
Add H18 and H10,H11 change size from 2.3 to 3.4 , H5 change size from 2.8 to 2.3
0.2(X01)
34
22
HW
11/16/2012
COMPAL
change diode to daul-diode fro cost saving
remove D4,D5,D6,D7 and add D10,D21
0.2(X01)
35
40
ME
11/16/2012
COMPAL
ME request
change SW1 to SKRBAAE010
0.2(X01)
36
30
ME
11/16/2012
COMPAL
ME change connector
change SD1
0.2(X01)
37
21,26,28, 31,39
HW
11/16/2012
COMPAL
For EA rework request
Add PJP12~25 for +1.05V_RUN_VMM,+3.3V_RUN_VMM,+3.3V_ALW_PCH,+1.05V_RUN, 0.2(X01) +3.3V_SUS,+3.3V_M,+5V_RUN,+3.3V_RUN,+3.3V_LAN,+3.3V_mSATA_WWAN,+3.3V_HDD ,+3.3V_WLAN,+5V_RUN_AUDIO,+3.3V_RUN_AUDIO
38
37
HW
11/19/2012
COMPAL
change thermal diode for cost saving
change Q11,Q13 and Q14 form SB000008P0L to SB33904510L
0.2(X01) 0.2(X01)
change Bead for cost reduce
change change change change
C
D
C
39
38,26,30,22
HW
11/19/2012
COMPAL
B
L44 L35 LE1 L21
and L45 from SM01000558L to SM01000C500 and L36 from SM01000AM0L to SM01000C500 from SM01000DH0L to SM01000BV00 from SM01001788L to SM010005N00
B
40
9
HW
11/19/2012
COMPAL
change APS pin 11 net_name for DELL APS debug Change JAPS1.11 net name from SIO_PWRBTN# to POWER_SW#_MB change net name from HOST_ALERT1_R_N to PCH_GPIO15, and pop RC190 support TLS confidentility remove R188
0.2(X01)
41
12,28
HW
11/19/2012
COMPAL
42
37
HW
11/19/2012
COMPAL
change thermal OTP to 98 degree
change R394 from 1.24K to 1.82K_1%
0.2(X01)
43
31
HW
11/20/2012
COMPAL
Intel notice remove HDD_DEVSLP function on WWAN JMINI port
remove HDD_DEVSLP from JMINI2.44 de pop HDD_DEVSLP pull up resistor R155
0.2(X01)
44
28
HW
11/20/2012
COMPAL
LOM LED issue
reverse Q32,Q33 of C & D gate
0.2(X01)
45
22
HW
11/20/2012
COMPAL
ME change connector
change JLED1
0.2(X01)
46
35
HW
11/21/2012
COMPAL
Align EMI part
change L54 pat to DLW21SN900SQ2L that same with L42, L39
0.2(X01)
47
15
HW
11/22/2012
COMPAL
Per Intel CRB updated
change VCCST_PWRGD pull high value from 10K ohm to 1K ohm
0.2(X01)
48
26
HW
11/22/2012
COMPAL
Universal Jack no longer supported on X5
Remove D9,D11,R209,R210,C195,C196,R198,R199
0.2(X01)
0.2(X01)
A
A
49
6,12,25,31
HW
11/26/2012
DELL
For support DEVSLP on WWAN JMINI2 & mSATA JMINI3
SATA HDD change from port0 to port1, and connect HDD_DEVSLP Dock change from port1 to port2, and connect mSATA_DEVSLP
0.2(X01)
Compal Electronics, Inc. PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
Title
EE P.I.R (2/6) Size
4
3
2
Rev 0.3
LA-9431P Date:
5
Document Number Friday, May 17, 2013
Sheet 1
55
of
59
5
4
3
2
1
V ersion Change L ist ( P. I. R . L ist ) Item Page# D
Title
D ate
R equest O w ner
Issue D escription
Solution D escription
R ev.
50
21,26
HW
11/26/2012
COMPAL
change Bead for cost reduce
L6 and L7 from SM01000GG0L to BLM15PX471SN1D(SM01000M700) L22, L23, L24 and L25 from SM010028800 to BLM15PX121SN1D(SM01000L300)
0.2(X01)
51
31
HW
11/26/2012
COMPAL
change WWAN power control signal
Change U3.5 from 3.3_1.5V_WLAN_E to SIO_SLP_WLAN#
0.2(X01)
52
12,36
HW
11/27/2012
COMPAL
NFC_DET# change to PCH side GPIO59
UC1.AT5 change from PCH_GPIO59 to NFC_DET# U37.B1 change to NC
0.2(X01)
53
22,26,38,40
HW
11/27/2012
COMPAL
Remove ESD reserve location
Per ESD experiment, D3,D27,D22,DE1,DE2 can be remove
0.2(X01)
54
33
HW
11/27/2012
COMPAL
Per USB2.0 EA result
Change U42 from SM01002080L(DLW21SN900SQ2L) to SM070001600(OCE2012120YZF)0.2(X01)
55
6,12,25,31
HW
11/27/2012
DELL
Per Dell requset, only JMINI3(mSATA ) support DEVSLP
SATA HDD use port0 ,Dock use port1
0.2(X01)
56
31
HW
11/28/2012
COMPAL
change +3.3V_WLAN PWR control
change +3.3V_WLAN PWR control from SIO_SLP_WLAN# to AUX_EN_WOWL
0.2(X01)
57
28
HW
11/28/2012
COMPAL
change +3.3V_mSATA_WWAN control
change +3.3V_mSATA_WWAN control from WWAN_mSATA_EN to MCARD_WWAN_PWREN
0.2(X01)
58
34
HW
11/28/2012
COMPAL
For EMI request, change to 33 ohm for docking DVI noise
R252/R253/R254/R255/R256/R257/R258/R259/R260/ R261/R262/R263/R264/R265/R266/R267 change to 33ohm from 0 ohm
0.2(X01)
59
21
HW
11/28/2012
COMPAL
For use IDT2320, need change EEPROM PN
U7 change from SA00003FL10(W25X10BVSNIG) to SA00006HH00(W25X10CLSNIG)
0.2(X01)
60
22
HW
11/28/2012
COMPAL
change Bead for cost reduce
LE1 change from SM01000DH0L(BLM18BB221SN1D)to SM01000BV00(BLM15BB221SN1D)0.2(X01)
C
D
C
61
6,25,31
HW
11/29/2012
DELL
To support mainstream and Premium CPU, change to SATA port assignment.
SATA HDD change from port0 to port1, and connect HDD_DEVSLP Dock change from port1 to port0, and connect mSATA_DEVSLP
62
12,31,34
HW
11/29/2012
DELL
To support the SATA DevSLP function for new SATA port assignment.
Change DEVSLP0/GPIO33 to mSATA_DEVSLP and DEVSLP1 to HDD_DEVSLP
0.2(X01) 0.2(X01)
63
33
HW
01/10/2013
COMPAL
For USB3.0 EA result
L37 & L38 change to SM070000S80(S COM FI_ CHENG HANN WCM2012F2SF-670T04) 0.3(X02)
64
40
HW
01/10/2013
COMPAL
For ME team force test result
SW1 change to SN111005800(S TACK SW BCL31 SKRBAAE010 SPST)
0.3(X02)
65
9
HW
01/17/2013
COMPAL
For U42 2nd source (MC74VHC1G08DFT2G)can't boot issue
PCH_RSMRST#_R add RC136 10K pull dowm
0.3(X02)
66
28
HW
01/17/2013
COMPAL
For meet INTEL LAN SPEC
Y3 change to SJ10000JC00(S CRYSTAL 25MHZ 18PF +-30PPM 7V25000034)
0.3(X02)
67
22
HW
01/17/2013
COMPAL
For trial run U9 2nd source
U9 pin 4 & pin5 connect to +3.3V_ALW
0.3(X02)
1.change R435 from 1.8k to 150(SD028150080) 2.R430/R438/R436 from 2.2k to 150(SD028150080) 3.R434 change from 220 to 150(SD028150080) 4.R427 change from 1K to 150 ohm(SD028150080) 5.R429 change from 620 to 330 ohm(SD028330080) 6.R431/R433 change from 330 to150 ohm(SD028150080)
0.3(X02)
1. modify JEDP1 pin assignment 2. pin 29 (IO_LOOP) add 1k pull down
0.3(X02)
B
B
68
40
HW
01/17/2013
COMPAL
69
22
HW
01/17/2013
COMPAL
A
For LED light test result
For prevent EDP pin shift then cause broken issue
A
Compal Electronics, Inc. PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
Title
EE P.I.R (3/6) Size
4
3
2
Rev 0.3
LA-9431P Date:
5
Document Number Friday, May 17, 2013
Sheet 1
56
of
59
5
4
3
2
1
V ersion Change L ist ( P. I. R . L ist ) Item Page#
Title
D ate
R equest O w ner
Issue D escription
Solution D escription 1.L22/L23/L24/L25 change to SM010019400 from SM01000L300 2.L51/L52 change to SM01000FV00 from SM01000AM0L 3.Delete L50/L53 & add R491/R492 0 ohm-short
D
D
0.3(X02)
70
25,26
HW
12/05/2012
COMPAL
For Audio Presison result
71
37
HW
12/07/2012
COMPAL
Change Board ID for ST
R392 change to 33K ohm from 130k ohm
0.3(X02)
Change connector tyoe
1. JNFC1 change to 6718K-Y15N-01L 2. JKBTP1 change to 6718K-Y16N-01L 3. JUSH1 change to 6718K-Y20N-00L 4. JUSB3 change to PUBAUE-09FLBS1FF4H0 5.JMEDIA change to 6718K-Y06N-01L 6. SH1 change to 6718K-Y12N-01L
0.3(X02)
72
73
37
HW
02/19/2012
COMPAL
HW
02/21/2012
COMPAL
For OTP issue, & change OTP to 96 degree from 98 degree
C
1. Q11/Q13/Q14 change to SB000008P00(S TR MMBT3904WT1G NPN SC70-3) from SB33904510L(S TR PMST3904 NPN SOT323-3) 2. R394 chagne to SD00000SJ80(S RES 1/16W 1.58K +-1% 0402) from SD034182180(S RES 1/16W 1.82K +-1% 0402)
0.3(X02) C
74
7
HW
02/21/2012
COMPAL
change JTAA1 connector type
JTAA1 change to PANAS_AXK820145WG from ACES_50185-02041-001
0.3(X02)
75
38
HW
02/21/2012
COMPAL
Per EMI Test result
Remove L44 & L45
0.3(X02)
76
38
HW
02/21/2012
COMPAL
Per ESD Test result
Pop C141 & C142 & C143
0.3(X02)
77
9
HW
02/21/2012
COMPAL
add XDP@ for XDP component
change XDP circuit to XDP@
0.3(X02)
78
9
HW
02/21/2012
COMPAL
update XDP circuit for INTEL ITE can't boot remove RC121 and pop RC102
0.3(X02)
HW
02/21/2012
COMPAL
HW
02/21/2012
79
B
R ev.
80
9,11,35
9,11,35
COMPAL
Fixed 2 USB Port use the same OC# signal issue
1.change JUSB3 OC# from USB_OC0# to USB_OC1# 2.change USB_OC1#/3# to USB_OC1#, USB_OC3# and add RC166 for OC1# pull up resistor
Add jumper for clock buffer co-layout
add PJP26, PJP27 and PJP28 beween UC5
0.3(X02)
1.L42 change to SM070003N00(CHILISIN CMM0805-20Y-N)from SM070001600( SUPERWORLD OCE2012120YZF) 2.L37/L38 change to SM070001R00(MURATA DLW21SN670HQ2L) from SM070001E0L(MURATA DLW21SN900HQ2L) 3.L8/L39/L54 change to SM070001N00(MURATA DLW21HN900SQ2L)from SM01002080L(MURATA DLW21SN900SQ2L)
0.3(X02)
81
33
HW
02/21/2013
COMPAL
Per EMI test result
82
33
HW
02/22/2013
COMPAL
Per ESD test result
83
9,12
HW
02/25/2013
COMPAL
For LID & AOAC S3 wake up issue
1. 2. 3. 4.
Pop CC71 & CC72 & CC73 Add C452 & C453 & C454(@) 22uF 0603 size R338 & R349 & R352 change to 10k ohm from 1k ohm Add C455 & C456 & C457 0.1UF
0.3(X02)
B
0.3(X02)
Change Net name to SIO_EXT_SMI# from USB_OC3# and change to PCH_GPIO45 from SIO_EXT_SMI#
0.3(X02)
A
A
Compal Electronics, Inc. PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
Title
EE P.I.R (4/6) Size
4
3
2
Rev 0.3
LA-9431P Date:
5
Document Number Friday, May 17, 2013
Sheet 1
57
of
59
5
4
3
2
1
V ersion Change L ist ( P. I. R . L ist ) Item Page#
Title
D ate
R equest O w ner
Issue D escription
Solution D escription 1. 2. 3. 4.
D
C
R ev.
add CC86~CC90 between clock signal add RC62 for UC5 power rail change RC100 from 0ohm short to 10ohm change UC5 from IDT_5V60034DCG8 to CYPRESS_CY2304SXI-1T
D
84
7
HW
02/25/2013
COMPAL
add RF noise solution at clock buffer
85
23
HW
02/25/2013
COMPAL
refer INTEL MOW to upfate HDMI cost reduce level shifter main link
86
33
HW
02/25/2013
COMPAL
change USB charge solution for SAMSUNG phone change U39 from SA00004VH00 to SA00006L600
0.3(X02)
87
26
HW
COMPAL
for Fixed BIOS fliah HOTSOS issue
change R154 from PCH_AUDIO_EN to RUN_ON
0.3(X02)
88
9
HW
02/28/2013
COMPAL
For ESD request
Add CC149(@) on H_PROCHOT# near CPU side
0.3(X02)
89
9
HW
02/28/2013
COMPAL
Follow INTEL CRB XDP schematic
CC68 change to 0.1uF from 0.01uF
0.3(X02)
90
7
HW
02/28/2013
COMPAL
For RF 24MHz issue
1. remove UC5 CC25,CC57,CC80,CC86~CC90,CC22,RC62,RC100,CC23 2. Change RC65 to 0 ohm-short
0.3(X02)
91
9
HW
02/28/2013
COMPAL
For Touch panel issue
92
7,29
HW
03/01/2013
COMPAL
refer GPIO3.0 to add PCH_TPM_LPC_EN
1. add RC56 for pull up enable signal and add R198 for pop option 2. change R193 form 0hm to 10ohm
93
7
HW
03/12/2013
COMPAL
Base on INTEL EDS SPEC Update Rev 1.5.1
1. 2. 3. 4. 5.
LANCLK_REQ# change to UC1.AD1 from UC1.Y5 MINI1CLK_REQ# change to UC1.T2 from UC1.U2 MINI2CLK_REQ# change to UC1.N1 from UC1.T2 MMICLK_REQ# change to UC1.U5 from UC1.AD1 PCH_TPM_LPC_EN change to UC1.Y5 from UC1.U5
0.4(X02)
1. 2. 3. 4.
CLK_PCIE_LAN change CLKOUT_PCIE port2 CLK_PCIE_MINI2 change CLKOUT_PCIE port3 CLK_PCIE_MMI change CLKOUT_PCIE port4 CLK_PCIE_MINI1 change CLKOUT_PCIE port5
0.4(X02)
94
7
HW
02/27/2013
03/14/2013
COMPAL
change
0.3(X02)
R462~R469 resistor from 680(SD034680080) to 470ohm(SD034470080) 0.3(X02)
1.TOUCH_PANEL_INTR# add RC181(@) PU & RC180 PD
For PCIE CLK & PCIE CLK REQ signal mapping
B
0.3(X02) 0.3(X02)
B
95
30
HW
03/14/2013
COMPAL
For O2 enters into test mode unexpectedly with SD card inserted incompletely issue.
1. SD/MMCCD# add C256(0.1uF) & R493(1M) pull-down to GND 2. C222 change to 1uF(SE000000K80) from 0.1u(SE00000G880)
0.4(X02)
96
21
HW
03/15/2013
COMPAL
For Synaptics vender request
1. Delete VMM2310 co-lay related schematic
0.4(X02)
97
21
HW
03/15/2013
COMPAL
For ESD request
1. Add C458(@) &C459(@) &C460(@) &C461(@) 22uF 0603 size
0.4(X02)
98
7
HW
03/18/2013
COMPAL
For INTEL request
PCIECLK_REQ0# add RC57(10k) pull-high to+3.3V_RUN
0.4(X02)
99
21
HW
03/20/2013
COMPAL
For Synaptics vender request
1. Delete R78/R80/R82 2. add C132
0.4(X02)
100
21
HW
03/20/2013
COMPAL
For ME request
ST2 change to H_2P8 from CLIP_C5P1
0.4(X02)
101
9, 12, 15
HW
03/22/2013
COMPAL
For ESD request
1. H_CPUPWRGD add CC90 100pF(@) to GND 2. H_THERMTRIP# add CC91 100pF(@) to GND 3. H_VCCST_PWRGD add CC22 100pF(@) to GND
A
0.4(X02)
Compal Electronics, Inc. PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
Title
EE P.I.R (5/6) Size
4
3
2
Document Number
Rev 0.3
LA-9431P Date:
5
C
Friday, May 17, 2013
Sheet 1
58
of
59
A
5
4
3
2
1
V ersion Change L ist ( P. I. R . L ist ) Item Page# D
Title
D ate
R equest O w ner
102
9
HW
03/27/2013
COMPAL
103
9
HW
03/27/2013
COMPAL
104
32
HW
04/24/2013
COMPAL
105
9
HW
04/24/2013
106
37
HW
107
40
108
Issue D escription
Solution D escription
For Touch panel issue
R ev.
pop RC181 and depop RC180(@)
0.4(X02)
pop RC97 & RC135
0.4(X02)
For USB S3 wake up issue
U33 power rail change from +3.3V_RUN to +3.3V_SUS
1.0(A00)
COMPAL
For XDP signal should be contact to PCH
change RC97 and RC135 to 0ohm short
1.0(A00)
04/25/2013
COMPAL
Change Board ID for A00
R392 change from33K ohm to 1K ohm
1.0(A00)
HW
04/25/2013
COMPAL
For LED EA
R436 change from150 ohm to 330 ohm;R438 change from 150 ohm to 220 ohm
1.0(A00)
28
HW
04/25/2013
COMPAL
for support Vpro reset pin
depop U20 and add R145
1.0(A00)
109
12
HW
04/25/2013
COMPAL
reserve for support non vpro pop option pin reserve RC292 100 ohm pull down
110
6
HW
05/13/2013
COMPAL
For Crystal EA result & RTC time fail issue
1. CC1 & CC2 change from 18pF to 15pF
1.0(A00)
111
16
HW
05/17/2013
COMPAL
For ESD request
Depop CC71/CC72/CC73
1.0(A00)
For XDP SPEC
D
1.0(A00)
C
C
B
B
A
A
Compal Electronics, Inc. PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
Title
EE P.I.R (6/6) Size
4
3
2
Rev 0.3
LA-9431P Date:
5
Document Number Friday, May 17, 2013
Sheet 1
59
of
59
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