Xilinx 4000-series Fpgas

Xilinx 4000-series FPGAs

Xilinx 4000-series FPGAs

XC4000 CLB

Two 4-input functions, registered output

5-input function, combinational output

CLB Used as RAM

CLB function generators (F, G, H) • Use RAM to store a truth table – F, G: 4 inputs, 16 bits of RAM each – H: 3 inputs, 8 bits of RAM – RAM is loaded from an external PROM at system initialization.

• Broad capability using F, G, and H: – – – –

Any 2 funcs of 4 vars, plus a func of 3 vars Any func of 5 vars Any func of 4 vars, plus some funcs of 6 vars Some funcs of 9 vars, including parity and 4-bit cascadable equality checking

Xilinx FPGA Combinational Logic • Examples – N-input majority function: 1 whenever n/2 or more inputs are 1 – N-input parity functions: 5 input/1 CLB; 2 levels yield 25 inputs! 5-input Majority Circuit 9 Input Parity Logic CLB CLB

7-input Majority Circuit CLB CLB CLB

CLB

Xilinx FPGA Adder Example • Example – 2-bit binary adder - inputs: A1, A0, B1, B0, CIN outputs: S0, S1, Cout A3 B3

A2 B2

CLB

Cout

A1 B1

CLB

S3

CLB

S2

C2

A3 B3 A2 B2

CLB

A0 B0 Cin

C1

CLB

S1

C0

S0

A1 B1 A0 B0 Cin

S2

2 x Two-bit Adders (3 CLBs each) yields 2 CLBs to final carry out

CLB

S0

S3 Cout

Full Adder, 4 CLB delays to final carry out

S1 C2

XC4000 Routing

XC4000 Routing

connections controlled by SRAM bits

XC4000 Programmable Switch Matrix programmable switch element

After Programming

XC4000 I/O block

Floorplan control using CAD tools Programmable Interconnect Points, PIPs (White) Switch Matrix

Direct Interconnect (Green) CLB (Red)

Long Lines (Purple)

Routed Wires (Blue)

Xilinx Spartan-II FPGAs • More conventional FPGAs are coarse grain – i.e. Fewer, more complex CLBs • New FPGA have other built-in resources for high performance computing. • Spartan Series FPGAs have BLOCK RAM

Spartan-IIE Memory Hierarchy

Shift Register LUT Distributed RAM •16 registers, 1 LUT •Single-port •Compact & fast •Dual port •Cascadable Q 16x1

 Pipelining  DSP Coefficients  Buffers  Small FIFOs  Scratch Pad

Bytes

4Kx1 2Kx2 1Kx4 512x8 256x16

Port B

CLA 0 A 1 A 2 A 3

SRL1 D CL 6Q KSRL16 A 0 A E 1 A 2 A 3

Port A

D C

Block RAMs •4Kbit blocks •True dual-port

Block RAM  Cache Tag memory  Large FIFOs  Packet buffers  Video line buffers

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Xilinx Spartan-II FPGAs

Xilinx Spartan-III FPGAs

Virtex FPGAs

Virtex-II CLB Slice

Virtex-II FPGAs

Virtex-II Pro FPGAs (2003 End)

Virtex 4 series FPGAs have more logic