Vhdl Basics

VHDL BASICS

Important elements of a VHDL file How do they relate with each other? • • • • • •

A TYPICAL VHDL FILE ------LIBRARY DECLARATION ……ENTITY ----defines external details …….ARCHITECTURE ------defines internal details

1. Entity Declarations • The primary purpose of the entity is to declare the signals in the design’s interface – The interface signals are listed in the PORT clause • In this respect, the entity is similar to the schematic symbol for the component

– Additional entity clauses and statements will be introduced later

Half adder

x y enable

carry Half Adder result

• -- a simple full adder model LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY ha IS PORT( x, y, enable: IN BIT; carry, result: OUT BIT); END[entity] ha ;

Entity declaration ENTITY latch IS PORT (s,r : IN BIT; q,nq : OUT BIT); END latch;

Architecture Bodies • Describe the operation of the component • Consist of two parts : – Declarative part -- includes necessary declarations • e.g. type declarations, signal declarations, component declarations, subprogram declarations

– Statement part -- includes statements that describe organisation and/or functional operation of component • e.g. concurrent signal assignment statements, process statements, component instantiation statements

x y

carry

enable

result

BEHAVIORAL MODEL •

ARCHITECTURE ha2 OF ha IS BEGIN PROCESS (x, y, enable) BEGIN IF enable = ‘1’ THEN result <= x + y; carry <= x AND y; ELSE carry <= ‘0’; result <= ‘0’; END IF; END PROCESS;

• In the data flow approach, we describe how signals (data) flow through the circuit

DATA FLOW MODEL ARCHITECTURE ha1 OF ha IS BEGIN carry <= enable AND (x AND y); result <= enable AND (x XOR y); END [ARCHITECTURE] [ha1];

STRUCTURAL MODEL

ARCHITECTURE ha3 OF ha IS COMPONENT and2 PORT (in0, in1 : IN BIT; out0 : OUT BIT); END COMPONENT; COMPONENT and3 PORT (in0, in1, in2 : IN BIT; out0 : OUT BIT); END COMPONENT; COMPONENT xor2 PORT (in0, in1 : IN BIT;

out0 : OUT BIT); END COMPONENT;

SIGNAL temp : BIT; -- internal signal -- Note that other signals are already -- declared in entity BEGIN A0 : and2 PORT MAP (enable, temp, result); A1 : and3 PORT MAP (x, y, enable, carry); X0 : xor2 PORT MAP (x, y, temp); END [ARCHITECTURE] [ha3];

• The structural description of a design is simply a textual description of a schematic. • A list of components and there connections in any language is sometimes called a netlist. • The structural description of a design in VHDL is one of many means of specifying netlists.

One System – Many VHDL Descriptions

DESIGN UNITS IN VHDL • Only 5 design units in VHDL • • • • •

Entity Declaration Architecture Body Configuration Declaration Package Declaration Package Body

Entity FOR DECODER entity DECODER is port (A, B, enable :in BIT ; Z : out BIT-VECTOR ( 0 to 3); end DECODER ;

Data flow model for decoder architecture D_FLOW of DECODER is signal ABAR ,BBAR :bit begin Z(3) <= not (A and B and ENABLE); Z(0) <=not (ABAR and BBAR and ENABLE); BBAR <= not B; Z(2) <= not (A and BBAR and ENABLE) ; ABAR <= not A; Z(1) <=not (ABAR and B and ENABLE); end D_FLOW;

BEHAVIORAL MODE Architecture SEQ of DECODER is begin process(A,B,ENABLE) variable ABAR,BBAR:bit; begin ABAR :=not A; BBAR:=not B;

if ENABLE =‘1’ then Z(3) <= not (A and B); Z(0) <= not (ABAR and BBAR); Z(2) <= not (A and BBAR); Z(1) <= not (ABAR and B); else Z<=“1111” end if; end process; end SEQ;

STRUCTURAL architecture STRUC of DECODER is component INV; port (PIN:in BIT;POUT:out BIT); end component; component NAND3; port ( D0,D1,D2 : in BIT; DZ :out BIT); end component ;

signal ABAR ,BBAR:BIT; Begin V0:INV port map (A,ABAR)’ V1:INV port map (B,BBAR); N0:NAND3 port map(ENABLE,ABAR,BBAR,Z(0); N1:NAND3 port map (ABAR ,B,ENABLE,Z(2); N2 :NAND3 port map(A,BBAR,ENABLE,Z(2)); N3:NAND3 port map (A ,B,ENABLE ,Z(3)); end STRUC

OR GATE library ieee; use ieee.std_logic_1164.all entity OR_ent is port(x: in std_logic; y: in std_logic; F: out std_logic); end OR_ent;

architecture OR_SEQ of OR_ent is begin process(x, y) begin if ((x='0') and (y='0')) then F <= '0'; else F <= '1'; end if; end process; end OR_SEQ;

OR-data fllow architecture OR_DF of OR_ent is begin F <= x or y; end OR_beh;

AND GATE library ieee; use ieee.std_logic_1164.all; -------------------------------------------------entity AND_ent is port (x: in std_logic; y: in std_logic; F: out std_logic); end AND_ent;

architecture behav1 of AND_ent is begin process(x, y) begin if ((x='1') and (y='1')) then F <= '1'; else F <= '0'; end if; end process; end behav1;

AND GATE -2 architecture behav2 of AND_ent is begin

F <= x and y; end behav2;

DATA FLOW_DEMUX entity DEMUX is port (e: in BIT) s: in bit_vector (1 downto 0); -- select signals d: out bit_vector (3 downto 0)); -- four output signals end DEMUX;

architecture DF of DEMUX is signal t : bit_vector(3 downto 0); internal signal begin t(3)<=s(1) and s(0); t(2)<=s(1) and not s(0); t(1)<=not s(1) and s(0); t(0)<=not s(1) and not s(0); d<=e and t; end DF;

-- an

Latch library ieee ; use ieee.std_logic_1164.all; entity D_latch is port( data_in: in std_logic; enable: in std_logic; data_out: out std_logic); end D_latch;

• -- latch is simply controlled by enable bit • -- but has nothing to do with clock sigal • -- notice this difference from flip-flops architecture behv of D_latch is begin process(data_in, enable) begin if (enable='1') then -- no clock signal here data_out <= data_in; end if; end process; end behv;

XOR library ieee; use ieee.std_logic_1164.all; entity XOR_ent is port( x: in std_logic; y: in std_logic; F: out std_logic); end XOR_ent;

architecture behv1 of XOR_ent is begin process(x, y) begin if (x/=y) then F <= '1'; else F <= '0'; end if; end process; end behv1;

architecture behv2 of XOR_ent is begin F <= x xor y; end behv2;

CONFIGURATIONS • Component declaration and instantiation are independent of VHDL models that are actually available. • It is the task of the VHDL configuration to link the components to entity/architecture pairs in order to build the complete design.

configuration • In summary: A component declaration provides a certain kind of socket that can be placed on the circuit as often as necessary with component instantiations. The actual insertion of a device into the instantiated sockets is done by the configuration.

entity FULLADDER is ... end FULLADDER; architecture STRUCT of FULLADDER is .. end STRUCT;

Example -configuration configuration CFG_FULLADDER of FULLADDER is for STRUCT -- select architecture STRUCT end for; end configuration CFG_FULLADDER ;

• Selects architecture for top-level entity • Selects entity/architecture pairs for instantiated components • Generates the hierarchy • Creates a simulatable object • Default binding rules: • selects entity with same name as component • signals are associated by name • last compiled architecture is used