Xilinx Fpga

XILINX FPGA

Virtex-6 

Configurable Logic Block (CLBs): A CLB element contains a pair of slices  Each slice contains: 

4

(6 input) Look-up tables (LUTs)  8 storage elements (flip-flops)  Wide-function multiplexers  Carry logic  Some slices support two additional functions: storing data using distributed RAM(256 bits/slice) and shifting data with 32-bit registers. 

Virtex-6

Virtex-6 

Additional features:  Powerful

mixed-mode clock managers(MMCM)  MMCM

blocks provide zero-delay buffering, frequency synthesis, clock-phase shifting, input-jitter filtering, and phase-matched clock division

 Advanced  25

DSP48E1 slices

x 18, two's complement multiplier/accumulator  Optional pipelining  New optional pre-adder to assist filtering applications  Optional bitwise logic functionality 

Virtex-6 

 



Integrated interface blocks for PCI Express® designs GTX transceivers: 150 Mb/s to 6.5 Gb/s GTH transceivers: 2.488 Gb/s to beyond 11 Gb/s Integrated 10/100/1000 Mb/s Ethernet MAC block

Virtex-6

Spartan-6 

Configurable Logic Block (CLBs): A

CLB element contains a pair of slices  Each slice contains: 4

(6 input) Look-up tables (LUTs)  8 storage elements (flip-flops)  Three

types of CLB slice

 SLICEM    

LUT can be used as 6 inputs or as dual 5 inputs LUT LUT can be used as 64 bit distributed RAM or as 2 * 32bit RAM LUT can be used as a 32 bit shift register

Spartan-6  SLICEL 

Same as SLICEM except for memory/shift register

 SLICEX 



 

Same as SLICEL except for arithmatic carry and wide MUX

Spartan-6 

Additional features:  Digital

Signal Processing—DSP48A1

 Pipelining

and cascading capability  Pre-adder to assist filter applications  Each slice consists of  

18 × 18 bit two's complement multiplier 48-bit accumulator

 Low-Power

Gigabit Transceivers

 All

Spartan-6 LXT devices have 2–8 gigabit transceiver circuits(622MB/s up to 3.125 GB/s)

 Integrated

Designs

Endpoint Blocks for PCI Express

 Clock

Management Tile (CMT) for enhanced performance  Low

noise, flexible clocking  Digital Clock Managers (DCMs) eliminate clock skew and duty cycle distortion  Phase-Locked Loops (PLLs) for low-jitter clocking  Frequency synthesis with simultaneous multiplication, division, and phase shifting  Sixteen low-skew global clock networks

Spartan-6

Summary Technology Spartan ( XL )

Core V

Core Clock

Max CLBs

Max I / Os

5(3.3) V

80 MHz

784

205

200 MHz

576 ( X2 slices )

512

Virtex

0 . 22 micron

Spartan II

0 . 18 micron

2.5 V

200 MHz

1176

284

Virtex II

0 . 15 micron

1.5 V

420 MHz

11648 ( X4 slices )

1108

8320 ( X4 )

633

Spartan III Virtex II Pro

0 . 13 micron

1.5 V

400 MHz >

11280 ( X4 ) PowerPC

Virtex IV



nm

1.2 V

500 MHz > 450 MHz >

12272 ( X4 ) (+ PowerPC )

960

Virtex V



nm

1.0 V

550 MHz

25920 1200 (+ PowerPC )

1200

Virtex 6



nm

1.0 V

400 MHZ up to 1600 59,280 ( X2 slices ) MHZ

1200

Spartan 6

45 nm

1.0V(low power) 1.2V(High performance)

400 MHz to 1000 11519 MHz ( X2 slices )

570

+

1164

CoolRunner XPLA3 CPLDs 

Architecture consists of function blocks that are interconnected by a Zeropower Interconnect Array (ZIA)  Each

FB has 16 macrocells  Each FB uses a Programmable Logic Array (PLA) architecture  guarantees

 

100% routability within the FB

The ZIA is a virtual crosspoint switch Each function block has 40 inputs from the ZIA

CoolRunner XPLA3 Architecture

CoolRunner XPLA3 Function Block Architectur e 

CoolRunner XPLA3 Variable Function Multiplexer 

(VFM)



CoolRunner XPLA3 CoolRunne r XPLA3 Macrocell 

CoolRunner XPLA3



I/O cell

XC9500XV 



Optimized for high-performance 2.5V systems Excellent quality and reliability  20

year data retention  ESD protection exceeding 2,000V 

Supports in-system programming (ISP) and the full IEEE 1149.1 (JTAG) boundary-scan

XC9500XV 

XC9500XV device is a subsystem consisting of  Function

Blocks (FBs)

 Each

FB provides programmable logic capability with extra wide 54 inputs and 18 outputs  Each Function Block is comprised of18 independent macrocells  I/O

Blocks (IOBs)  Fast CONNECT II switch matrix  connects

all FB outputs and input signals to the FB inputs



XC9500XV XC9500X V Architect ure 

XC9500XV XC9500X V Function Block 

XC9500XV XC9500X V Macrocell Within Function Block 

XC9500XV Fast CONNECT II Switch Matrix 

I/O Block and Output Enable Capability 

CoolRunner XPLA3 



Available in commercial grade and extended voltage (2.7V to 3.6V) industrial grade Advanced 0.35μ five layer metal EEPROM process  1,000

erase/program cycles guaranteed  20 years data retention guaranteed 

3V, In-System Programmable (ISP) using JTAG IEEE 1149.1 interface  Full

Boundary-Scan Test (IEEE 1149.1)  Fast programming times