Substrate Noise Analysis With Compact Digital Noise Injection And Substrate Models

Substrate Noise Analysis with Compact Digital Noise Injection and Substrate Models Makoto Nagata1

Yoshitaka Murasaka2

Youichi Nishimori1

Takashi Morie1

Atsushi Iwata1,2 1

Integrated Systems Laboratory, Hiroshima University 1-3-1 Kagamiyama, Higashi-Hiroshima, 739-8526 Japan 2 A-R-Tec Corp. Email: {nagata, morie, iwa}@dsl.hiroshima-u.ac.jp Abstract This paper presents a substrate noise analysis methodology that employs chip-level substrate modeling based on F-matrix computation and digital substrate-noise injection modeling with a time-series divided parasitic capacitance model for time-domain power-supply current estimation. System-level simulation models generated accordingly to the methodology provide reliable substrate noise waveforms. Simulated waveforms for practical digital circuits on a 0.6-µm CMOS 4.5-mm square chip are well consistent with measurements with a 100-ps 100-µV resolution. Peak-topeak substrate noise amplitudes for reduced-substrate noise as well as conventional designs show roughly the error of 10% compared with the measurements.

1. Introduction Advanced system-on-a-chip (SoC) VLSIs much benefit from mixed-signal integration of analog functional sub-systems for such as ADC/DAC and RF with highspeed/large-scale digital signal processing cores on a single Si die. However, time-to-market designs need reliable ways to estimate mixed-signal circuit performance with the effect of digital-to-analog substrate crosstalk [1, 2] especially in closing physical designs. This paper proposes a suite of substrate noise analysis methodologies that includes chip-level substrate modeling based on fundamental matrix (F-matrix) computation and digital-substrate noise injection modeling based on rapid yet accurate power-supply current waveform estimation. We applied the methodologies to a 0.6-µm CMOS test chip in which conventional and reduced-substrate noise

CMOS digital circuits were embedded with a highly linear substrate noise detector. Simulation results are compared with measurements with a 100-ps 100-µV resolution.

2. Full-chip substrate noise analysis The substrate crosstalk is a phenomenon where noises injected into a common substrate by digital circuits propagate toward embedded analog circuits and leak to analog signal paths, which finally interfere with analog operation and degrade analog circuit performance. Such noise, generally referred to as a substrate noise, has a waveshape closely correlating with a change in logic activity in a digital circuit, and more complicatedly, is considerably attenuated when propagating through a Si substrate. The goal of substrate noise analysis is to estimate the change in substrate voltage quantitatively both in time and space domains in the vicinity of victim analog circuits [3, 4]. However, great difficulties in performing fullchip substrate noise analysis are due mainly to dealing with the hundred thousands of gate elements in digital circuits and the millions of connections between ground wirings and a substrate on the surface, which are non-uniformly distributed within the die area of up to 20-mm square. Therefore, we need macro-modeling techniques for digital circuits as noise injectors and also for a substrate and surface power-supply/ground wiring systems as transmitting media, on the basis of general understandings on substrate noise properties. Our proposed techniques are outlined in following sections. Note that one can predict the response of an analog circuit to substrate noise through conventional time-domain circuit simulation, where the circuit senses the noise mainly through the back-gate effect of MOSFETs and capacitive coupling of parasitic components.

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2.1. Chip-level substrate modeling using F-matrix computation We can deal with a silicon substrate as an equivalent resistive mesh, as long as the frequency of interest is within a few giga-hertz. However, accurate analysis requires a finer mesh, which demands a greater analysis time and memory and is of less practical use. Network reduction methods such as [5] can involve mesh nodes other than some of explicitly designated surface analysis nodes into a transfer matrix and thus remove them from an actual nodal matrix for circuit simulation, without loss of accuracy. We have developed a chip-level substrate modeling technique which uses fundamental matrix (F-matrix) computation in conjunction with such the network reduction principle and provides a general way to compute an admittance matrix of the explicit analysis nodes for a substrate with surface ground-wiring systems [6]. The computed admittance matrix can be easily transformed to netlists compatible with conventional circuit simulators such as SPICE. A multi-terminal F-matrix relates voltage V 2 and current I2 of n output terminals to those of n input terminals V 1 and I1 as follows:

 V V1 =F 2 . (1) I1 I2

I11

V11

I12

V12

V21

F1

V22

F2

V31

Vm1

V32

Vm2

V3n

Vmn

(2)

where F1 , F2 , · ··, Fm denote F-matrices of sub-circuit networks, and Fcas the synthesized matrix. All of these matrices have n input and n output terminals. We can deal with a chip as a resistive network in alternate piles of horizontal and vertical layers, as Fig. 2 shows. Since an F-matrix can be defined for each of the layer, a chip-level F-matrix cascade can be formed as follows:


 
V Vtop = Fh,wire Fv,con Fh Fv Fh Fv · · · btm , Itop Ibtm

(3)

where (Vtop , Itop ) stand for the voltage and current of n nodes on the chip surface, (Vbtm , Ibtm) those on the chip bottom, Fh,wire a horizontal F-matrix for a ground wiring system, Fv,con a vertical F-matrix for ties between the ground wirings and substrate, F h and Fv horizontal and vertical F-matrices within a substrate mesh, respectively. From the Kirchhof’s laws, we can find I1 = I2 in determining vertical and V 1 = V2 in determining horizontal

Fm

V(m+1)2 I(m+1)2

I1n

I(m+1)n V1n

V2n

V(m+1)n

Figure 1. F-matrix computation for m-stage cascaded circuit.

Chip

Fh,wire Fv,con Fh Fv Fh Fv

Cascading F-matrices of sub-circuits gives a synthesized system F-matrix as shown in Fig. 1 where all of the intermediate nodes are included to a single F-matrix, which is the most attractive feature of the F-matrix computation. The F-matrix of the m-stage cascaded circuits is described as follows: Fcas = F1 F2 · · ·Fm ,

V(m+1)1 I(m+1)1

Figure 2. Chip-level F-matrix cascade.

F-matrices, respectively, and obtain general forms of Fmatrices as follows:

 E A E 0 Fv = , Fh = . (4) 0 E B E Here, A, B are sub-matrices representing vertical resistive elements determining vertical voltage differences and horizontal resistive elements determining horizontal currents induced from voltage differences from four neighboring nodes, respectively, and E an identity matrix. Although the synthesized system F-matrix relates (V, I) of all the surface nodes to those of the bottom nodes, we choose a few of the nodes as explicit analysis nodes for connecting the substrate to active circuits and system power-supply/ground terminals and leave the other nodes floated, in macroscopic treatments. Further network reduction can be performed in converting the F-matrix to a

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Y-matrix of the explicit analysis nodes under a condition where Itop−floated = 0 and Ibtm−floated = 0 for the other floated nodes. The final form of the chip-level substrate model is a SPICE compatible sub-circuit netlist, where the ports corresponding to the explicit analysis nodes are fully connected each other with the resistors constituting the Ymatrix. Note that the proposed chip-level substrate modeling technology with the F-matrix computation considerably reduces the size of the nodal matrix of a chip-level resistive mesh network in an error-free way, except for round-off errors in actual computing.

2.2. Digital substrate noise injection modeling The leakage of voltage bounce on power-supply/return rails into a substrate is the most dominant source of substrate noises in large-scale digital circuits [7]. This fact naturally indicates that a precise expression of power-supply current waveforms in digital circuits must be key in simulating the substrate noise injection, since the interaction of the current with power-supply parasitic impedance results in the bounce. We have developed a time-series divided parasitic capacitance (TSDPC) model shown in Fig. 3(c), where a digital circuit is equivalently expressed as a series of capacitors to be charged by an external power source [8]. Groups of capacitances parasitic to gate elements switching in rise and those in fall in the digital circuit are defined as ΣC ↑ , ΣC↓, respectively. Each of the active gate element involves both charging (C ch) and discharging (Cdis) capacitances in both of the switching directions, as shown in Figs. 3(a) and (b). Here, the discharging process is mostly completed through local shorts formed in MOSFETs with channel resistance. On the other hand, sub-nano second logic switching operation is mostly completed through charge redistribution, where stably charged capacitances work as locally distributed charge reservoirs which rapidly feed charges to the charging capacitors. The primal role of external power sources is to feed charges equal to ΣCch ·Vdd to the circuit, 2 required from and it consumes the entire energy of ΣCch ·Vdd completing logic operations in this process. While the loss of charges due to sub-threshold leakage and short-circuit currents shares other parts of power consumption, its effect on the noise injection is minor. Now we introduce a time division to the continuous distribution of logic transitions in a digital circuit. The charging capacitance is integrated in every time interval of nT ∼ nT + T , where T and n stand for the period and the number of the interval, respectively. The resulting timeseries capacitances of {Cch,↑(nT ),Cch,↓ (nT )} is the TSDPC model of the circuit. This model generation is required once per an input vector for the circuit, however, which can be

A AA A AA AA A AA AA AAA A AA AAA A AAAAA A A AAA

(a)

(b)

ΣC (nT) ΣC dis, (nT) ΣCch, (nT) ΣC (nT) ΣCdis, (nT) ΣCch, (nT)

(c)

AAAAAAAAAAAAA AA AAAAAA A AA A AA A A AA AA A AAAA AA

Lp Rp Vdd

Cs

(n-2)T

Vsub

(n-1)T

nT

(n+1)T

Figure 3. Capacitances parasitic to logic elements switch (a) in rise and (b) in fall. (c) Time-series divided parasitic capacitance (TSDPC) model.

(a) CMOS

(b) SGW

VDD&Nwell

z0

Nwell Cj

VDD

Cp

TSDPC GND&Psb

z1

Noise injection

TSDPC

z1

z0

GND

Cj Psb

Nwell Cj

(c) RSB

Cd z0 z1

z0 VDD

z0 z0 Cp z0 z0

z1 z1 Cp z1 z1

z1 Cp

TSDPC

Cd

GND Cj Psb

z0

z1

Figure 4. Substrate noise injection models for (a) conventional, (b) separated guard wiring (SGW), and (c) reduced supply bounce (RSB) CMOS topologies.

achieved in parallel with conventional post P&R gate-level or transistor-level time-domain simulations. A compact time-domain power-supply current estimator is formed by connecting the model with a power-supply parasitic impedance network and a stable parasitic capacitor Cs between the circuit and the external power source, as shown in Fig. 3(c). The size of Cs can be roughly equal to the total sum of parasitic capacitances between power-supply and ground terminals of the circuit and on-chip de-caps. The model greatly reduces the cost of computation since only a few passive components are to be solved in every sim-

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ulation steps while maintains the accuracy comparable to full-transistor level circuit simulation. In addition, once a TSDPC model is generated, it can be re-used for simulating power-supply current with the power-supply networks with various component values or even in different topologies, since the model simply provides the amount of charges required per every time interval from a digital circuit. Figure 4 shows substrate noise injection models, where reduced-substrate noise designs including separate guard wiring (SGW) CMOS and reduced supply bounce (RSB) CMOS [8] employ the same TSPDC model as well as in a conventional design. The voltage bounce induced at parasitic impedances on return wirings appears as the substrate noise through distributed P + substrate contacts on the surface of a P-type substrate. Guard wirings for substrate/well ties are isolated from the bouncing power-supply/return rails in the SGW-CMOS, which is often used in highperformance mixed-signal design. On the other hand, the variation of power-supply current is suppressed by intentionally inserted RC-time constants between local and main power-supply/return rails in the RSB-CMOS, which considerably reduces the voltage bounce. TSDPC modeling provides reliable estimates of noise amplitude for these circuit topologies and helps to choose and/or optimize the reduced noise designs.

3. Design of substrate noise test chip

5pcs.

CMOS

5pcs.

SGW-CMOS

RSB-CMOS(1) RSB-CMOS(2) RSB-CMOS(3)

SF+LC

(a)

SEL INA CLK1 INB CLK2 SET

Reg1 Reg2 0 0 0 0 0 0 0 0 Full Adder

CLK3

Reg3

[A]

[B] OUT

(b) A test chip shown in Fig. 5(a) was fabricated in a 0.6µm CMOS DPTM technology with a P-type bulk substrate. It includes arrays of a noise source circuit comprising two 8-bit CMOS input registers and an 8-bit CMOS full adder followed by an output register as described in Fig. 5(b), and a highly linear substrate noise detector (SF+LC). The arrays each includes 10 pieces of the identical CMOS circuit while uses conventional, SGW, and RSB topologies at physical level design. Power-supply wirings are separated among the arrays. The number of the circuits to activate is controllable. The power-supply voltage of 3.3 V was used. The chip has the area of 4.5 mm × 4.5 mm mostly occupied by the arrays and the detector senses the substrate noise locally at its position. Therefore, it is necessary to apply the chip-level substrate modeling technique for analyzing substrate noises with the effect of propagation decay.

4. Simulation and measurements We generated a set of TSDPC models of the noise source circuit with various input binary data to the registers from transistor-level circuit simulation results. Simulated substrate noise waveforms at the source, thus without a substrate model, show obvious peaks strongly correlating with

Figure 5. (a) 0.6-µm CMOS test chip. (b) Noise source circuit.

clock edges while have negligibly small dependence of the noise intensity on the input bit patterns. This reasonably indicates that the most of logic activity comes from gating in flip-flops and internal clock drivers. Therefore, one of the TSDPC models represents the noise source circuit in following full-chip substrate noise analysis. The mesh size of 151 × 151 × 6 was chosen and Fmatrices of Fh and Fv with 151 × 151 nodes were defined for all layers identically inside the bulk substrate. Figure 6 shows a simplified ground wiring system of the chip used for defining the surface F-matrices of Fh,wire and Fv,con , where parts of the wirings and substrate contacts within every mesh region are used for determining the resistance of mesh elements. We designated 54 explicit analysis nodes all on the surface, including 1 node per 5 noise source circuits for every array, 1 node for the noise detector, and the others for ties to the system ground. The chip backside was floated in assembly. A system-level substrate noise simulation model shown

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Simulated

Vsub (mV)

CMOS SGW

Vsensor (mV)

RSB1 RSB2 RSB3

40 30 20 10 0 -10

V DDA

z

V DD

z

z

V GND

RSB1

Measured CMOS

0 RSB(1)-(3)

-20 0

10

20 time (ns)

30

40

Figure 8. Substrate noise waveforms of conventional and reduced-substrate noise CMOS circuits.

TSDPC TSDPC TSDPC

Figure 7. System-level substrate noise simulation model.

in Fig. 7 is described in a SPICE compatible netlist, which includes the chip-level substrate model, noise source circuits (TSDPC models), a noise detector, and external power sources. We inserted an inductor of 1 nH and a resistor of 1 Ω in series to every connections between ports and power sources as well as the system ground, in order to involve parasitic impedance networks resulting from the chip assembly. Figure 8 shows substrate noise waveforms simulated with the model by a SPICE simulator and those actually measured in a 100-ps 100-µV resolution by the measurement system that we have established on a mixed-signal IC tester [8]. The noises from the reduced noise design using the RSB-CMOS are also shown. Simulated and measured waveshapes are well consistent especially in primal frequency components correlating with the clock edges and peak-to-peak noise amplitudes. Differences in detailed structure arise dominantly from the simplified models of parasitic impedance networks. We found the attenuation ratio of roughly 9.5 dB for the substrate noise propagat-

Measured

Simulated

60

Substrate Voltage p-p [mV]

Detector VGNDA

z

RSB2,3

20

CLK

Figure 6. Simplified ground wiring system.

CMOS

50 CMOS

40

CMOS

30 RSB(1) RSB(2) RSB(3)

20 RSB1

10 0

RSB2,3

2

4

6

8

10

2 N Blk

4

6

8

10

Figure 9. Peak-to-peak noise amplitudes versus number of active noise source circuits.

ing from the conventional CMOS noise sources, which locate most distant from the detector as shown in Fig. 5(a). These analyses costed only 7-MByte memory and 80-sec CPU time per a waveform with a PA8500-440MHz microprocessor. Figure 9 compares simulated and measured peak-topeak noise amplitudes for different numbers of active noise source circuits, which match roughly with the error of 10%. Note that the noise amplitude in the RSB-CMOS seems to be smaller than the lower limit of the measurements due to

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background noises mainly from I/O circuits.

5. Conclusions A substrate noise analysis methodology employing chiplevel substrate modeling based on F-matrix computation and digital substrate-noise injection modeling with the time-series divided parasitic capacitance model for timedomain power-supply current estimation has been demonstrated. System-level simulation models generated accordingly to the methodology provide rapid yet reliable estimates of substrate noise waveforms. In addition, the models can be re-used among the designs with various powersupply network topologies, which is very helpful to the physical-level design optimization of mixed-signal chips for achieving substrate noise reduction and/or tolerance.

environment,” IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, 19(6):671–678, June 2000. [8] M. Nagata, J. Nagai, K. Hijikata, T. Morie, and A. Iwata, “Physical design guides for substrate noise reduction in CMOS digital circuits,” IEEE J. Solid-State Circuits, 36(3):539–549, Mar. 2001.

Acknowledgments This work is supported in part by Industrial Technology Research Grant Program from NEDO and by Semiconductor Technology Academic Research Center (STARC). Chips are fabricated by Rohm Corp. and Toppan Printing Corp. through VLSI Design and Education Center (VDEC), the Univ. of Tokyo.

References [1] D. K. Su, M. J. Loinaz, S. Masui, and B. A. Wooley, “Experimental results and modeling techniques for substrate noise in mixed-signal integrated circuits,” IEEE J. Solid-State Circuits, 28(4):420–430, Apr. 1993. [2] N. K. Verghese, T. J. Schmerbeck, and D. J. Allstot, Simulation Techniques and Solutions for Mixed-Signal Coupling in Integrated Circuits, Boston, MA: Kluwer Academic Publishers, 1995. [3] I. L. Wemple and A. T. Yang, “Integrated circuit substrate coupling models based on Voronoi tessellation,” IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, 14(12):1459–1469, Dec. 1995. [4] E. Charbon, R. Gharpurey, R. G. Meyer, and A. SangiovanniVincentelli, “Substrate optimization based on semi-analytical techniques,” IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, 18(2):172–190, Feb. 1999. [5] T. A. Johnson, R. W. Knepper, V. Marcello, and W. Wang, “Chip substrate resistance modeling technique for integrated circuit design,” IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, CAD-3(2):126–134, Apr. 1984. [6] Y. Murasaka, M. Nagata, T. Ohmoto, T. Morie, and A. Iwata, “Substrate noise analysis using fundamental matrix computation,” In Proc. IEEE Int. Symp. Quality Electronic Design, pages 482–487, Mar. 2001. [7] M. Nagata, J. Nagai, T. Morie, and A. Iwata, “Measurements and analyses of substrate noise waveform in mixed signal IC

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