Substrate Noise Analysis And Simulation With Substratestorm

Substrate Noise Analysis and Simulation with SubstrateStorm

Philippe Duchene [email protected]

© Copyright 2001 Simplex Solutions, Inc.

1

Complete SoC Verification Suite Power Integrity

VoltageStorm™ SoC

Timing Integrity

Fire & Ice® QX ClockStorm™

Signal Integrity

SubstrateStorm™ SI Report™

Reliability

ElectronStorm™

© Copyright 2001 Simplex Solutions, Inc.

2

The Substrate Crisis

Digital Noise

Sensitive Section

Noise Generation

Noise Sensitivity

Number devices - UP Frequency - UP Rise / fall time - DOWN

Signal resolution - UP Frequency - UP Power - DOWN

At 0.13 micron Noise generation increases by 50% Noise © Copyright 2001 Simplex Solutions, Inc. sensitivity increases by 100%

3

ADI Disaster Example: Trial & Error • Video converter with 27 MHz PLL failed • VCO locked to substrate clock • Various solution techniques attempted • What worked?

www.imse.cnm.es/esd-msd/WORKSHOPS/ESSDERC2000 © Copyright 2001 Simplex Solutions, Inc.

4

What designs need SubstrateStorm? • Mixed-Signal SoCs – Digital Noise Generation + Noise Transmission + Analog Sensitivity – 100 MHz or above

Std cell Logic Embedded Memory

A/D D/A

• RF designs – Wireless, Bluetooth, 3G, SiGe – GHz range

• Sensitive analog designs I/O

Std cell block PLL

– A/D’s, D/A’s CPU core

I/O

• High-speed I/O’s – 1 GHz or above

• High-speed PLL’s – 500 MHz or above

© Copyright 2001 Simplex Solutions, Inc.

5

Typical Substrate Related Questions • I have 5 isolation structures – which is optimal for this design?

• How wide should my guard ring be? • How will a technology port effect my design performance? • What immunity do I gain by backside plating? • What benefit do I get by splitting my power supply? ••• © Copyright 2001 Simplex Solutions, Inc.

6

SubstrateStorm Design Flow IC Design

SubstrateStorm

Layout

Substrate Abstract View

LVS/LPE

Substrate Extraction

Edit

Technology Description

Netlist

Simulation

Visual Analysis CDS DFII or Standalone GUI

© Copyright 2001 Simplex Solutions, Inc.

7

Model Extraction Strategy

Technology Technology description description

Layout Layout IN

3-D 3-DModel Model

OUT Electrical Electrical simulation simulation

© Copyright 2001 Simplex Solutions, Inc.

Visual Visual analysis analysis

8

Modeling the Substrate Bonding Wire

Noise Source

Noise Victim

P+ contacts

•

N+ contact

Substrate Abstract View Definition -

•

Nwell

Process regions (wells, buried layers, deep trenches, …) Ports connecting the ideal circuit to the substrate Equivalent ideal circuit model for interactive visual analysis

RC Model Extraction

© Copyright 2001 Simplex Solutions, Inc.

9

3D Modeling

poly p+ nwell y

}

LAYOUT

interconnect contact

device

z

nwell p-substrate

© Copyright 2001 Simplex Solutions, Inc.

PROCESS

p+

(doping profiles)

x

10

Distributed RC Model poly p+

n+

p+

nwell p-substrate

resistive substrate

well-substrate junction capacitance

resistive well

Modeling

© Copyright 2001 Simplex Solutions, Inc.

11

Self-Adjusting Grid

•

Unlimited chip size

•

Highest accuracy where needed

•

Non-manhattan shapes

© Copyright 2001 Simplex Solutions, Inc.

12

SubstrateStorm™ TCT

SubstrateStorm Technology Characterization

Substrate Extraction

Technology Description

Fabrication Process TCAD

Measurement

Doping Profiles

Patents granted © Copyright 2001 Simplex Solutions, Inc.

13

Simplex Foundry Partners Measurement or TCAD Simulations Doping Profiles

• Simplex teams up with foundry partners to provide acurate substrate parameters Designer Technology Description

Technology Characterization Tool © Copyright 2001 Simplex Solutions, Inc.

Substrate Extraction 14

Full-chip Analysis •

Design Example – Effect of pad ring switching noise on PLLs

•

Exploration Questions – Noise frequency dependence – Splitting ground lines – Backside grounding – Number of VSS pins (package inductance) – Guard rings – etc.

© Copyright 2001 Simplex Solutions, Inc.

15

PLL Affected By Output Ring • Design – 1M gates, 0.18µ – 100MHz clock (PLL)

• PLL Noise Concerns: – Noise propagated from the output buffer ring – Explore various solutions to improve noise immunity

© Copyright 2001 Simplex Solutions, Inc.

16

Buffer Creates Substrate Noise

GDS

not shown on customer request

Noise Color Map

Substrate Abstract View

abstraction

analysis extraction

simulation © Copyright 2001 Simplex Solutions, Inc.

SPICE substrate subnetlist 17

Pad Ring Creates Substrate Noise • SubstrateStorm – surface distribution of the noise

• Conditions – – – –

© Copyright 2001 Simplex Solutions, Inc.

400ps rise/fall time 30pF off-chip load 2nH bond inductance Plotted @ 350MHz

18

Noise Is Collected By PLL

PLL is well protected by its guard rings

BUT Guard rings also carry noise !!

© Copyright 2001 Simplex Solutions, Inc.

19

Noise Increases with Frequency

DC

350 MHz

Noise isolation typically degrades at higher frequencies Isolation is 6dB @ DC, but -0.42dB @ 350MHz © Copyright 2001 Simplex Solutions, Inc.

20

Splitting Power Reduces Noise VSS1

VSS1

VSS2

Effective way of improving isolation (-0.42dB to -9.5dB) Requires additional pins but no additional space © Copyright 2001 Simplex Solutions, Inc.

21

Backside Grounding Has Little Effect

With backside connection through a 5nH bond wire: F

Isolation at PLL ring improved by only 0.03dB

F

Not worth the cost !

© Copyright 2001 Simplex Solutions, Inc.

22

Exploration Questions •

What if you: – – – – – – –

added a N-well guard ring around your PLL? used a triple-well process? used a low-resistivity substrate? introduced a grounded backside connection? took the seal ring into account? cut the VSS ring to avoid noise transportation … Etc …

Each question only takes minutes to answer using SubstrateStorm © Copyright 2001 Simplex Solutions, Inc.

23

Detailed Cell-level Analysis

Sensitive analog cell (op-amp)

Noise source (substrate propagation only) Goal: locate the most sensitive parts of the analog cell and improve the noise immunity (lightly doped substrate) © Copyright 2001 Simplex Solutions, Inc.

24

Simulation Set-Up

Noise source

Non-inverter amplifier, gain = 1000 © Copyright 2001 Simplex Solutions, Inc.

25

Substrate Impact

e t s i No pac im

Output Noise 220mV Noise source

Through the substrate

tr = 350 ps © Copyright 2001 Simplex Solutions, Inc.

26

What Is the Most Sensitive Part?

Differential input pair? Input current mirror? Output driver? Output current mirror? Active load? Compensation circuit? Combination of them?

© Copyright 2001 Simplex Solutions, Inc.

27

Differential Input Pair VDDA

VSSA

Substrate model extraction Circuit netlist back-annotation SPICE simulation Output noise < 1% Total noise

Substrate © Copyright 2001 Simplex Solutions, Inc.

No impact from this stage 28

Active Devices < 1% Total Noise

Input Current Mirror Output Driver Output Current Mirror Active Load Differential Input Pair

© Copyright 2001 Simplex Solutions, Inc.

29

Feedback Circuitry VDDA

VSSA

Substrate model extraction Circuit netlist back-annotation SPICE simulation Output noise > 95% Total noise

Substrate © Copyright 2001 Simplex Solutions, Inc.

Major noise collector is feedback capacitor 30

Immunity Increase 1st Solution: extending the n-well under the compensation devices

Result:

1: noise immunity improved: 50% 2nd Solution: p+ ring around the cell

Result:

2: noise immunity improved: 80%

Design trade-off: What’s your choice? © Copyright 2001 Simplex Solutions, Inc.

31

Substrate Technology You Need • Unique Solution – Technology Characterization + Accurate Modeling – Visual Analysis

• Flow Integration – Standalone: GDS to Spice – Diva, Calibre, Assura, Dracula – Seamless Integration in Cadence Virtuoso and Analog Artist

• 2 Use Models – Detailed Cell Analysis and Simulation – Chip-level Floorplan Analysis

• Foundry Program – TSMC, ST, UMC

• Currently Used In Production Designs

© Copyright 2001 Simplex Solutions, Inc.

32

New in SubstrateStorm V4.0 • Performance & Capacity – Upgraded extraction & analysis kernel • speed 3-5x

– RC Netlist reduction • capacity 5x

– Macro-modeling

• Ease-of-Use – Automation of common tasks – Multiple object edition

• Flow Integration – Cadence 4.4.5, 4.4.6 – Calibre, Assura, Dracula

© Copyright 2001 Simplex Solutions, Inc.

33

STV0399 - first single chip CMOS integration

• • • •

“Until now, two or more ICs have been required to implement these functions, at a cost some 25 - 50% higher.” Zero IF tuner multistandard demodulator (QPSK and 8-PSK) Forward Error Correction (FEC) 950-2200 MHz RF input

“We have already applied SubstrateStorm successfully to several designs, one of which is a very advanced single-chip satellite RF receiver for cable television. We have been impressed that the first silicon confirmed the predictions of SubstrateStorm in that the digital block interference with the RF blocks was sufficiently low as to make the chip functional.” Philippe Magarshack Central R&D Group Vice President for Design Automation and Libraries © Copyright 2001 Simplex Solutions, Inc.

34

SoC + Analog = Substrate Noise

Substrate noise kills analog performance ... Don’t wait for it to kill your design !

© Copyright 2001 Simplex Solutions, Inc.

35