Statistically-aware Sram Memory Array Design

Statistically-Aware SRAM Memory Array Design Evelyn Grossara, Michele Stucchi, Karen Maexa and Wim Dehaenea

a

IMEC , Leuven, Belgium Also at Department of Electrical Engineering (ESAT) , Katholieke Universiteit Leuven, Belgium [email protected]

ISQED 2006 San Jose, CA, USA

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Outline Introduction Statistically-Aware Optimization Modeling the distributions of the performance parameters Statistical sensitivities Results

Conclusions

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Introduction Parametric variations affect device [Asenov, ESSCIRC’04] performance S G variations in D the number and position of dopants

Device performance variations affect yield High frequency High standby leakage current Low frequency Low standby leakage current

Icrit ∆ Id,sub

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∆ Vth

significant parameter variations (∆ Vth , ∆ Id,sub ) from device to Evelyndevice Grossar-TAD-meeting

Distributions of frequency and standby leakage current (Isb) in microprocessors (0.18um) [Borkar, DAC’04] 3

Outline Introduction Statistically-Aware Optimization Modeling the distributions of the performance parameters Statistical sensitivities Results

Conclusions

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Statistically-Aware Optimization Statistically-Aware optimization of circuits = use statistical information on the variation of transistor parameters during circuit optimization in terms of speed, energy and yield For the SRAM cell: - explore trade-offs for optimized leakage power versus 1. delay constraint: Vdd

Read current of weakest PUP1 PUP2 SRAM cell mainly limits the 0 1 delay constraint PG1 VL VR PG2 (first order approximation) PDN1 PDN2 2. functionality constraints (read stability and write-ability) BLB

wl

wl

Vdd

Vdd

BL

gnd

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Performance parameters of SRAM cell: Read stability and write-ability Write-ability Vdd

Read Stability

SRAM cell is most vulnerable to noise during read operation V Vdd V inv1 +VnVdd wldd wl dd 1 VL

0 VR

inv2

-Vn+

VL

+Vn

Vn = 0 Vn = SNM

-Vn VR

SNM: maximum dc noise

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(Vn) (e.g. mismatches due to processing) that Evelyn Grossar-TAD-meeting

Vdd

d PG1

BL

Internal node voltage [V] Bit-line voltage Vbl [V]

BLB

VBLB dd Vd

1.5 1

Vdd ->0V

VVdd d

BL

0 1d

1 0 PUP1

PUP2

VL PDN1

VR

PG2

PDN2

VBL gnd Write-trip point = 0.606V

0.5 0 0

0.2

0.4 0.6 0.8 1 Bit-line voltage Vbl [V]

1.2

1.5

1.4

VL VR

1 0.5 0 0

0.2

0.4 0.6 0.8 1 Bit-line voltage Vbl [V]

1.2

1.4

Write-trip point: maximum Vbl at which cell changes state 6

Statistically-Aware Optimization of SRAM cell Use a constraint algorithm together with dual-Vth optimization algorithm to minimize the leakage power of the cell Constraint algorithm: selects SRAM cell design which fulfills the delay and functionality (read stability and write-ability) constraints Minimization of leakage power SRAM cell Vdd BLB

Vdd

0 wl

Vdd

0 PG1

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0 wl PUP1

PUP2

Vdd

1

VL PDN1

VR PG2 PDN2

gnd

BL

Vdd

only sub-threshold leakage current (Ids,sub ) is considered, due to Ids,sub ~ exp(Vth ) 7

Outline Introduction Statistically Aware Optimization Model distributions of performance parameters Statistical sensitivities Results

Conclusions

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Model distributions of performance parameters Vth variability propagation to performance parameters Distributions of performance in function of Vth 2 2  2  ∂ 2 SNM parameters ∂ SNM ∂ SNM 2 2 2  η SNM = SNM + 0.5∑  σ Vth σ Vth σ Vth , pgi + , pdni + , pupi   , 2 2 2  e.g. SNM ∂ V ∂ V ∂ V  i =1  th , pgi th , pdni th , pupi  2 2  ∂SNM  2      ∂ SNM ∂ SNM 2 2 2        =∑ σ Vth , pgi + σ Vth , pdni + σ Vth , pupi         i =1  ∂Vth , pgi   ∂Vth , pdni   ∂Vth , pupi    2

varSNM

Asymmetrical behavior of the SRAM cell with respect to Vl 2and finternal nodes = f V(1r − F ) min( SNMhigh , SNMlow )

SNM

SNM

Meeting the≤design constraint SNM η SNM − 3 ∗constraint: σ SNM 98.987% of the total samples of the SNM distribution fulfills the design constraint © imec 2006

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Outline Introduction Statistically Aware Optimization Modeling the distributions of the performance parameters Statistical sensitivities Results

Conclusions

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Statistical sensitivities Statistical sensitivity

gives information about direction and magnitude in which the design parameter W has to move to improve the yield of the design, which depends on the Vth intra-die variations 100 49.5% fulfills

70 60

the SNM constraint of 120mV for W pg=190nm

40

80 SNM yield [%]

Frequency

50

30 20 10 0 0.09

0.1

0.11

0.12 0.13 SNM [V]

0.14 70

Wpg Wpup Wpdn

0.15

60

40

slope = statistical sensitivity

20

60

Frequency

0 1.9

29.8% fulfills the SNM constraint of 120mV for W pg = 200nm

50 40 30

2

2.1 2.2 Transistor Width [m]

2.3

2.4 -7 x 10

20 10 © imec 2006

0 0.09 Evelyn Grossar-TAD-meeting

0.1

0.11

0.12 0.13 SNM [V]

0.14

0.15

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Outline Introduction Deterministic Method for SRAM Cell Optimization Stability, delay and leakage power definition Deterministic optimization approach Worst-Case optimization approach Results

Statistically Aware Optimization Modeling the distributions of the performance parameters Statistical sensitivities Results

Conclusions

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Results compared with worst-case design -3σ

worst-case design:

-3σ

<<-3σ

+ p1

p2

φ

-sets all Vth parameters (p1, p2) to their worst-case value with respect to performance parameter φ - overestimation of the underlying process variations - increased power consumption and area

130nm statistical design: 1.85

-9 x 10 SNM Target = 120mV, Vwrite Target=0.4Vdd

Standby leakage power [W]

1.8

worst case approach statistical optimization

1.75 1.7 1.65 1.6 ca.14% 1.55

ca. 12%

1.5 1.45 1 © imec 2006

significant % over-design is needed to fulfill the design targets with the worst-case approach Iread Target Actual Iread Area -

ca. 40% 1.2

1.4 Iread Target [A]

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1.6

1.8 -4 x 10

100uA 17% 27% 170uA 10% 11% - 14% degradation of leakage power SRAM cell results in 40% read current improvement

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Outline Statistically Aware Optimization Modeling the distributions of the performance parameters Statistical sensitivities Results

Conclusions

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Conclusions 

The optimization is based on an algorithm using constraints and dual-Vth strategy: Including pdfs of the performance parameters  Using statistical information to guide the optimization  Results: - gain both in leakage power (11%) and area (27%) w.r.t worst-case design - trade-offs: improvements in read current (40%) of the cell can be obtained by degrading leakage power (14%) 

Statistically aware circuit optimization proves to be advantageous at cell level to keep both leakage power consumption and area of the SRAM cell minimal 

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Statistically Aware Optimization: Results (3)

3.5

6 x 10 Iread Target = 130uA, SNM Target = 120mV, Vwrite Target = 0.4Vdd

3

worst-case approach statistical approach

Frequency

2.5 mean = 178.41uW sigma = 0.140uW

2

mean = 192.26uW sigma = 0.130uW

1.5

Total standby leakage power distribution for an array matrix of 16kB SRAM is approximated by a Gaussian distribution.

1 0.5 0 1.7

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1.75

1.8 1.85 1.9 1.95 Total standby leakage power [W]

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2

2.05 -4 x 10

Central Limit Theorem states that the sum of independent identical distributions of any type approaches a normal distribution

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Statistically-Aware Optimization of SRAM cell (2) Compare with Worst-Case design approach: -3σ

<<-3σ

-3σ

+ p2

p1

φ

- sets all Vth parameters (p1, p2) to their worst-case valu with respect to the performance parameter φ - overestimation of the underlying process variations - increased power consumption and area Delay constraint of SRAM cell: Vdd BLB

wl

wl

Vdd

PUP1

PUP2

VL PDN1

VR

1 PG1

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0

PDN2

gnd

Vdd

PG2

BL

Read current of weakest SRAM cell mainly limits the delay constraint (first order approximation) 17