Sandeep
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COMPARATOR compares till 96 and goes high
CLK 25MHZ [9:0]counter_h_i mod 800
DI CLK
D FLIP-FLOP
o_h_synch
count<96
50 MHZ CLK
Clock Enabler
And which goes high when the count is 799 [9:0]counter_v_i which counts up to 521 horizontal cycles
CLK [9:0]COMPARATOR compares till the count value reaches2 and generates high pulse
D FLIP-FLOP
o_v_synch
DI
Count < 2
[2:0]o_rgb_data rgb generator enabler
>48 And gate <68
CLK 25MHZ [9:0]counter_h_i mod 800
DI CLK
D FLIP-FLOP
o_h_synch
count<96
50 MHZ CLK
Clock Enabler
And which goes high when the count is 799 [9:0]counter_v_i which counts up to 521 horizontal cycles
CLK [9:0]COMPARATOR compares till the count value reaches2 and generates high pulse
D FLIP-FLOP
o_v_synch
DI
Count < 2
[2:0]o_rgb_data rgb generator enabler
>48 And gate <68
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