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DESIGN AND IMPLEMENTATION OF FOUR BIT RIPPLE CARRY ADDER USING 180NM CMOS TECHNOLOGY

1.

INTRODUCTION

Most of the VLSI applications, such as digital signal processing, image and video processing and microprocessors, extensively use arithmetic operations. Addition, subtraction, multiplication and multiply and accumulate (MAC) are examples of the most commonly used operations. The 1-bit full-adder cell is the building block of all these modules. Thus, enhancing its performance is critical for enhancing the overall module performance. The most important performance parameters for future VLSI systems are speed and power consumption. this paper we present a novel 1-bit full adder cell which offers faster operation and consumes less area and power than standard implementations of the full adder cell. With the popularity of portable systems as well as fast growth of power density in integrated circuits, power dissipation becomes main design objectives equal for digital system has become main goal. Generally ripple carry adders are used among all types of adders because of its compact design but it is the slowest adder. Several ripple carry adders have been proposed using different full adder cells targeting on design accents such as power, delay and area. Among those designs with less transistor count using transmission gate logic have been widely used to reduce area. The proposed ripple carry adder is implemented using Cadence EDA too. The tool provides sophisticated features such as Cadence Virtuoso Schematic Editor which provides sophisticated capabilities which speed and ease the design, Cadence Virtuoso Visualization and Analysis which efficiently analyzes the performance of the design and Cadence Virtuoso Layout Suite that speeds up the physical layout of the design. In this paper, we propose a design of ripple carry adder using full adder cell with 18 transistors. The paper is organized as follows: in section II, previous work is reviewed. Subsequently, in section III, the proposed design of ripple carry adder is presented. In section IV, the schematic and layout of the adders are presented. In section V, the simulation results are given and discussed. The comparison and evaluation for proposed and conventional designs are carried out. Finally a conclusion will be made in the last section

1.1 EXISTING SYSTEM Adding two single-bit binary values with the inclusion of a carry input produces two

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DESIGN AND IMPLEMENTATION OF FOUR BIT RIPPLE CARRY ADDER USING 180NM CMOS TECHNOLOGY

outputs, a sum and a carry; this circuit is called a full adder. The relation between the inputs A, B, Cin and the outputs Sum and Cout are expressed as:

Sum = A xor B xorCin Cout = (A and B) or (B and Cin) or (A and Cin)

The truth table of full adder is shown below. Table: 1.1.1 Truth Table of Full Adder Inputs

Outputs

A

B

Cin

Sum

Cout

0

0

0

0

0

0

0

1

1

0

0

1

0

1

0

0

1

1

0

1

1

0

0

1

0

1

0

1

0

1

1

1

0

0

1

1

1

1

1

1

Different logic styles can be investigated from different points of view. Evidently, they tend to favor one performance aspect at the expense of others. In other words, it is different design constraints imposed by the application that each logic style has its place in the cell library development. Even a selected style appropriate for a specific function may not be suitable for another one. For example, static approach presents robustness against noise effects, so automatically provides a reliable operation. The issue of ease of design is not always attained easily. The CMOS design style is not area efficient for complex gates with large fan-ins. Thus, care must be taken when a static logic style is selected to realize a logic function

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DESIGN AND IMPLEMENTATION OF FOUR BIT RIPPLE CARRY ADDER USING 180NM CMOS TECHNOLOGY

Fig 1.1.2 Conventional Full Adder

The conventional full adder shown in Fig 1.1 is a complementary CMOS (CCMOS) full adder with 28 transistors. It is a combination of PMOS pull up transistors and NMOS pull down transistors. It is well known for its robustness and scalability at low supply voltages. The complementary CMOS logic circuit has the advantages of layout regularity and stability at low voltage due to the complementary transistor pairs and smaller number of interconnecting wires. But its power consumption and transistor count are relatively high for low power arithmetic circuits. In this full adder, interdependence between signals generation (SUM signal relies on the generation of COUT signal) causes the problem of delay imbalance. Ripple carry adder is built using multiple full adders such as the above discussed conventional full adder. In ripple carry adder each carry bit from a full adder "ripples" to the next full adder. The simple implementation of 4-bit ripple carry adder is shown below. C0 is the input carry, x0 through x3 and y0 through y3 represents two 4-bit input binary numbers.

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Fig 1.1.3 4- Bit ripple carry adder

1.2 PROPOSED SYSTEM The proposed ripple carry adder is designed using a full adder cell with 18transisitors based on transmission gate. It uses a novel exclusive-or (XOR) gate. The schematic for this XOR gate is shown in Fig.1.3.

Fig 1.2.1 Transmission Gate XOR

As a point to note, switch-level simulators have problems with this gate. The operation of the gate is explained as follows: 1.

When signal A is high, -A is low. Transistor pair P1 and N1 thus acts as inverter,

with –B appearing at the output. The transmission gate formed by transistor pair P2 and N2 is open. 2.

When signal A is low, -A is high. The transmission gate formed by transistor

pair P2 and N2 is now closed, passing B to the output. The inverter formed by transistor pair P1 and N1 is partially disabled (level reduced B passed to the output by P1, N1). Thus this transistor configuration forms a 6-transistor XOR gate. By reversing the connections of A and –A, an exclusive-nor (XNOR) gate is constructed.

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Fig:1.2.2 Transmission Gate Full Adder

Thus the proposed ripple carry adder is implemented using optimized transmission gate full adder which is efficient in terms of area.

1.3PROBLEM DEFINITION The issue of case of design is not always attained easily. The CMOS design style is not area efficient from complex gates with large fan-in's in conventional ripple carry adder. The power consumption and transistor count are relatively high for low power Arithmetic circuits. To overcome this problem we reduce the transistor count, delay and power.

1.4 MOTIVATION OF THE PROJECT The motive of this project is that reducing area and transistor count and high performance applications. Optimizations for basic logic gates are fundamental in order to get better the performance of a variety of low power and high performance devices. . This technique allows reducing power consumption, delay and area efficiency.

1.5 OBJECTIVE OF THE PROJECT The main objective of this project that a novel full adder designed using 18 transmission gates is presented in this paper that targets low transistor count and area. .

1.6 CONCLUSION

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In this two different ripple carry adders have to be implemented, simulated, analyzed and compared. A full adder is designed using 18 transmission gate is presented, that targets low transistor count and area. Thus we have to implement a ripple carry adder which is optimized in terms of transistor count.

1.7 ORGANIZATIONOFTHESIS This is report contains six chapters. CHAPTER 1: Introduction about the Project. CHAPTER 2: Literature Survey introduction to VLSI. CHAPTER 3: Hardware Description. CHAPTER 4: Software Description. CHAPTER 5: Results. CHAPTER 6: Conclusion and Future Scope.

2 . LITERATURE SURVEY 2.1 INTRODUCTION TO VLSI VLSI stands for "Very Large Scale Integration". This is the field which involves packing more and more logic devices into smaller and smaller areas. Thanks to VLSI, circuits that would have taken boardfuls of space can now be put into a small space few millimetres across! This has opened up a big opportunity to do things that were not possible before. VLSI circuits are everywhere ... your computer, your car, your brand

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new state-of-the-art digital camera, the cell-phones, and what have you. All this involves a lot of expertise on many fronts within the same field. VLSI has been around for a long time, there is nothing new about it ... but as a side effect of advances in the world of computers, there has been a dramatic proliferation of tools that can be used to design VLSI circuits. Alongside, obeying Moore's law, the capability of an IC has increased exponentially over the years, in terms of computation power, utilisation of available area, yield. The combined effect of these two advances is that people can now put diverse functionality into the IC's, opening up new frontiers. Examples are embedded systems, where intelligent devices are put inside everyday objects, and ubiquitous computing where small computing devices proliferate to such an extent that even the shoes you wear may actually do something useful like monitoring your heartbeats! These two fields are kind of related, and getting into their description can easily lead to another article. The invention of the transistor by William B. Shockley, Walter H. Brattain and John Bardeen of Bell Telephone Laboratories drastically changed the electronics industry and paved the way for the development of the Integrated Circuit (IC) technology. The first IC was designed by Jack Kilby at Texas Instruments at the beginning of 1960 and since that time there have already been four generations of ICs .Viz SSI (small scale integration), MSI (medium scale integration), LSI (large scale integration), and VLSI (very large scale integration). Now were ready to see the emergence of the fifth generation, ULSI (ultra large scale integration) which is characterized by complexities in excess of 3 million devices on a single IC chip. Further miniaturization is still to come and more revolutionary advances in the application of this technology must inevitably occur. Over the past several years, Silicon CMOS technology has become the dominant fabrication process for relatively high performance and cost effective VLSI circuits. The revolutionary nature of this development is understood by the rapid growth in which the number of transistors integrated in circuits on a single chip.

2.2 HISTORY OF VLSI The First Transistor in 1947 John Bardeen and Walter Brattain built the first functioning point contact transistor at Bell Labs. In 1959, Dawon Kahng and Martin M.

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DESIGN AND IMPLEMENTATION OF FOUR BIT RIPPLE CARRY ADDER USING 180NM CMOS TECHNOLOGY

(John) Attalla at Bell Labs invented the metal–oxide– semiconductor field-effect transistor (MOSFET) as an offshoot to the patented FET design. The method of coupling two complementary MOSFETS (P-channel and N-channel) into one high/low switch, known as CMOS, means that digital circuits dissipate very little power except when actually switched.As the number of transistors per chip increased, the idle power consumption of BJTs (which have other advantages over MOSFETS) made CMOS the dominant technology. Intel’s next generation, made in 22nm fab, will hit stores around April.The “3D” transistorredesign that hasmade 22nm and 14nm processes possible During the mid-1920s, several inventors attempted devices that were intended to control current in solid-state diodes and convert them into triodes. Success did not come until after WWII, during which the attempt to improve silicon and germanium crystals for use as radar detectors led to improvements in fabrication and in the understanding of quantum mechanical states of carriers in semiconductors. Then scientists who had been diverted to radar development returned to solid-state device development. With the invention of transistors at Bell Labs in 1947, the field of electronics shifted from vacuum tubes to solid-state devices.

With the small transistor at their hands, electrical engineers of the 1950s saw the possibilities of constructing far more advanced circuits. As the complexity of circuits grew, problems arose. One problem was the size of the circuit. A complex circuit, like a computer, was dependent on speed. If the components of the computer were too large or the wires interconnecting them too long, the electric signals couldn't travel fast enough through the circuit, thus making the computer too slow to be effective. Jack Kilby at Texas Instruments found a solution to this problem in 1958. Kilby's idea was to make all the components and the chip out of the same block (monolith) of semiconductor material. Kilby presented his idea to his superiors, and was allowed to build a test version of his circuit. In September 1958, he had his first integrated circuit ready. Although the first integrated circuit was crude and had some problems, the idea was groundbreaking. By making all the parts out of the same block of material and adding the metal needed to connect them as a layer on top of it, there

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was no need for discrete components. No more wires and components had to be assembled manually. The circuits could be made smaller, and the manufacturing process could be automated. From here, the idea of integrating all components on a single silicon wafer came into existence, which led to development in small-scale integration (SSI) in the early 1960s, medium-scale integration (MSI) in the late 1960s, and then large-scale integration (LSI) as well as VLSI in the 1970s and 1980s, with tens of thousands of transistors on a single chip (later hundreds of thousands, then millions, and now billions (109)).

2.3 Developments The first semiconductor chips held two transistors each. Subsequent advances added more transistors, and as a consequence, more individual functions or systems were integrated over time. The first integrated circuits held only a few devices, perhaps as many as ten diodes, transistors, resistors and capacitors, making it possible to fabricate one or more logic gates on a single device. Now known retrospectively as small-scale integration (SSI), improvements in technique led to devices with hundreds of logic gates, known as medium-scaleintegration (MSI). Further improvements led to large-scale integration (LSI), i.e. systems with at least a thousand logic gates. Current technology has moved far past this mark and today's microprocessors have many millions of gates and billions of individual transistors. At one time, there was an effort to name and calibrate various levels of largescale integration above VLSI. Terms like ultra-large-scale integration(ULSI) were used. But the huge number of gates and transistors available on common devices has rendered such fine distinctions moot. Terms suggesting greater than VLSI levels of integration are no longer in widespread use. As of early 2008, billion-transistor processors are commercially available. This became more commonplace as semiconductor fabrication advanced from the thencurrent generation of 65 nm processes. Current designs, unlike the earliest devices, use extensive design automation and automated logic synthesis to lay out the transistors, enabling higher levels of complexity in the resulting logic functionality. Certain highperformance logic blocks like the SRAM (static random-access memory) cell, are still designed by hand to ensure the highest efficiency. VLSI technology may be moving toward further radical miniaturization with introduction of NEMS technology.1970s -

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NMOS Technology – Intel 1101 SRAM – 256 bit static random access memory and 4004 4-bit microprocessor Late 40s Transistor invented at Bell Labs Late 50s First IC (JK-FF by Jack Kilby at TI) Early 60s Small Scale Integration (SSI) 10s of transistors on a chip Late 60s Medium Scale Integration (MSI) 100s of transistors on a chip Early 70s Large Scale Integration (LSI) 1000s of transistor on a chip Early 80s VLSI 10,000s of transistors on a chip (later 100,000s & now 1,000,000s) Ultra LSI is sometimes used for 1,000,000s.Research has a long history of involvement with IBM high-performance processor design: from the pioneering 801 RISC processor of the 1980s and ground-breaking work in Very Long Instruction Word (VLIW) architecture and systems to the first IBM mainframe with a CMOS microprocessor in 1996 and the current ultra-complex systems such as those use POWER5™. As the latest processor for IBM’s I Series™ and p Series® systems, POWER5 uses eight levels of copper wiring and over a quarter billion transistors to take full advantage of IBM’s leading-edge 130 nm. Silicon-On-Insulator (SOI) technology. Research continues to make major contributions to IBM’s microprocessors, spanning the full spectrum of system design, including micro architectures, circuits and circuit techniques, low power, design methodologies and tools, design verification, and interaction with technology development. A strong focus centers on developing advanced high-end systems. Along with industry collaborators, for example, Research is working with IBM’s Systems and Technology Group in the development of future server processors, as well as the Cell Broadband Engine™ — the next generation of scalable and power-efficient microprocessors, a multi-core architecture optimized for computer-intensive rich media applications. IBM places a significant emphasis on System-on-a-Chip (SoC) design capabilities, in which pre-design components are used to quickly compose chips with high levels of function. Research contributes to IBM’s SoC capabilities in both the design and tools areas. These capabilities played an integral part in the design of Blue Gene/L that became the world’s fastest supercomputer in 2004.

2.4 LEVEL OF INTEGRATION

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VLSI (very large-scale integration) is the current level of computer microchip miniaturization and refers to microchips containing in the hundreds of thousands of transistors. LSI (large-scale integration) meant microchips containing thousands of transistors. Earlier, MSI (medium-scale integration) meant a microchip containing hundreds of transistors and SSI (small-scale integration) meant transistors in the tens.The MOS Transistor means, Metal-Oxide-Semiconductor Field Effect Transistor which is the most basic element in the design of large scale integrated circuits(IC).These transistors are formed as a ``sandwich'' consisting of a semiconductor layer, usually a slice, or wafer, from a single crystal of silicon; a layer of silicon dioxide (the oxide) and a layer of metal. These layers are patterned in a manner which permits transistors to be formed in the semiconductor material. The MOS technology is considered as one of the very important and promising technologies in the VLSI design process. The circuit designs are realized based on pMOS, nMOS, and CMOS and BiCMOS devices. The pMOS devices are based on the p-channel MOS transistors .Specifically, the PMOS channel is part of a n-type substrate lying between two heavily doped p+ wells beneath the source and drain electrodes. Generally speaking, a pMOS transistor is only constructed in consort with an NMOS transistor. The nMOStechnology and design processes provide an excellent background for other technologies. In particular, some familiarity with nMOS allows a relatively easy transition to CMOS technology and design. The techniques employed in nMOS technology for logic design are similar to GaAs technology.. Therefore, understanding the basics of nMOS design will help in the layout of GaAs circuits In addition to VLSI technology, the VLSI design processes also provides a new degree of freedom for designers which helps for the significant developments. With the rapid advances in technology the the size of the ICs is shrinking and the integration density is increasing. The minimum line width of commercial products over the years is shown in the graph below.

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Fig 2.4 graph for commercial products The graph shows a significant decrease in the size of the chip in recent years which implicitly indicates the advancements in the VLSI technology.

2.5 Moore's Law An observation made by Intel co-founder Gordon Moore in 1965. He noticed that the number of transistors per square inch on integrated circuits had doubled every year since their invention. Moore's law predicts that this trend will continue into the foreseeable future. Although the pace has slowed, the number of transistors per square inch has since doubled approximately every 18 months. This is used as the current definition of Moore’s law. Because Moore's law suggests exponential growth, it is unlikely to continue indefinitely. Most experts expect Moore's law to hold for another two decades. Some studies have shown physical limitations could be reached by 2017.

Fig 2.5.1 chip of Intel

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Fig 2.5.2 Graph for the Moore’s Law Moore’s Law is a computing term which originated around 1970; the simplified version of this law states that processor speeds, or overall processing power for computers will double every two years. A quick check among technicians in different computer companies shows that the term is not very popular but the rule is still accepted.To break down the law even further, it specifically stated that the number of transistors on an affordable CPU would double every two years but ‘more transistors’ is more accurate.

2.6 CPU If you were to look at processor speeds from the 1970’s to 2009 and then again in 2010, one may think that the law has reached its limit or is nearing the limit. In the 1970’s processor speeds ranged from 740 KHz to 8MHz; notice that the 740 is KHz, which is Kilo Hertz – while the 8 is MHz, which is Mega Hertz.From 2000 – 2009 there has not really been much of a speed difference as the speeds range from 1.3 GHz to 2.8 GHz, which suggests that the speeds have barely doubled within a 10 year span. This is because we are looking at the speeds and not the number of transistors; in 2000 the number of transistors in the CPU numbered 37.5 million, while in 2009 the number went up to an outstanding 904 million; this is why it is more accurate to apply the law to transistors than tospeed.With all this talk of transistors the average technician or computer user may not understand what the figures mean; a simpler way to explain is

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that the earlier CPUs on the market had a single speed or frequency rating while the newer models have a rating which refers to more than one CPU.

2.7 VLSI DESIGN FLOW The VLSI IC circuits design flow is shown in the figure below. The various level of design are numbered and the gray coloured blocks show processes in the design flow

Fig 2.7 VLSI Design Flow

Specifications comes first, they describe abstractly the functionality, interface, and the architecture of the digital IC circuit to be designed. 

Behavioral description is then created to analyze the design in terms of

functionality, performance, compliance to given standards, and other specifications. 

RTL description is done using HDLs. This RTL description is simulated to test

functionality. From here onwards we need the help of EDA tools. 

RTL description is then converted to a gate-level netlist using logic synthesis

tools. A gate-level netlist is a description of the circuit in terms of gates and connections between them, which are made in such a way that they meet the timing, power and area specifications. 

Finally a physical layout is made, which will be verified and then sent to

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

The first mask defines the n-well regions. This is followed by a low dose

phosphorus implant driven in by a high temperature diffusion step to form the n-wells. The well depth is optimized to ensure against-substrate top+ diffusion breakdown without compromising then-wellton+ mask separation. The next steps are to define the devices and diffusion paths, grow field oxide, deposit and pattern the polysilicon, carry out the diffusions, make contact cuts, and finally metalize as before. lt will be seen that an n+ mask and its complement may be used to define the n- and p-diffusion regions respectively. These same masks also include the VDDandVsscontacts(respectively). It should be noted that, alternatively, we could have used a p+ mask and its complement. Since the n+ and p+ masks are generally complementary. Integration's aim is to cover every aspect of the VLSI area, with an emphasis on cross-fertilization between various fields of science, and the design, verification, test and applications of integrated circuits and systems, as well as closely related topics in process and device technologies. Design entry: It describes the RTL (Register Transfer Level) logics in HDLs. For this, we use any of the hardware description languages (HDLs) such as verilog and VHDL. This design specification contains all the details which all are required for the design architecture, RTL block diagram, clock frequency, frequency domain details, waveforms, port details etc. Logic Synthesis: The RTL logic written is synthesized to get the gate level net list. This process can be done with the help of EDA tools. The code written can be implemented on an FPGA board only if, it is synthesizable. Gate level simulation: The gate level simulation of the logic is very important in the verification. The functional check, timing checks and the Power analysis checks are included in the verification.

2.8 NEED FOR VLSI The power dissipation and speed in a circuit present a trade-off; if we try to optimise on one, the other is affected. The choice between the two is determined by the way we chose the layout the circuit components. Layout can also affect the fabrication of VLSI chips, making it either easy or difficult to implement the components on the silicon.

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Fig 2.6 VLSI chip

As we all know VLSI stands for Very large scale integration. Very large scale integration is the process of creating an integrated circuit by combining thousands of transistors into a single chip. Now the question comes why we need VLSI. So the answer is that one of the most characteristics of information service is there increasing need for very high processing and band width. The other important characteristics is that the information service tend to become more personalized, which means that the information processing device must be more intelligent and also be portable to allow more mobility. VLSI is mainly classified in two classes. VLSI back end – VLSI back-end includes Route, place and floor planning. Back end includes development and fabrication part. It is too costly and time consuming process. Physical designing and layout refers to back end. VLSI front end – VLSI Frontend includes designing and testing part. It uses Verilog and HDL, VHDL .RTL designing, minimizing delay and simulation refers to Front end. There are two important steps. VLSI design and design verification. VLSI design refers to the designing of VLSI circuits and its implementation. Design verification is use to test the design and verify us that the given designing is working properly or not Now, we should move towards physical and digital design of VLSI. Both are very important part of VLSI. Digital design is divided in three steps. First is, second is structural and third one is design. Behavioural describes the algorithm, structural describes component and their connections, and physical describes how circuit built.

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In standard design cycle physical design comes after the circuit design. Physical design includes both design and verification and validation of layout. At this step circuit representation is converted into geometric representation.

2.9 SOURCES OF POWER CONSUMPTION 2.9.1 Need for Low Power Design There are various interpretations of the Moore’s Law that predicts the growth rate of integrated circuits. One estimate places the rate at 2X for every eighteen months. Others claim that the device density increases ten-fold every seven years. Regardless of the exact numbers, Everyone agrees that the growth rate is rapid with no signs of slowing down. New generations of processing technology are being developed while present generation devices are at very safe distance from the fundamental physical limits. A need for low power VLSI chips arises from such evolution forces of integrated circuits. The Intel 4004 microprocessor, developed in 1971, had 2300 transistors, dissipated about 1watts of power and clocked at 1MHz. Then the Pentium in 2001, with 42 million transistors, dissipating around 65 watts of power and clocked at 2.40 GHz. While the power dissipation increases linearly as the years go by, the power density increases exponentially, because of the ever-shrinking size of the integrated circuits. If this exponential rise in the power density were to increase continuously, a microprocessor designed a few years later, would have the same power as that of the nuclear reactor. Such high power density introduces reliability concerns such as, electro migration, thermal stresses and hot carrier induced device degradation, resulting in the loss of performance. Another factor that fuels the need for low power chips is the increased market demand for portable consumer electronics powered by batteries. The craving for smaller, lighter and more durable electronic products indirectly translates to low power requirements. Battery life is becoming a product differentiator in many portable systems. Being the heaviest and biggest component in many portable systems, batteries have not experienced the similar rapid density growth compared to the electronic circuits. The main source of power dissipation in these high performance batteryportable digital systems running on batteries such as note-book computers, cellular

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phones and personal digital assistants are gaining prominence. For these systems, low power consumption is a prime concern, because it directly affects the performance by having effects on battery longevity. In this situation, low power VLSI design has assumed great importance as an active and rapidly developing field. At the circuit design level, considerable potential for power savings exists by means of proper choice of a logic style for implementing combinational circuits. This is because all the important parameters governing power dissipation switching capacitance, transition activity, and Short-circuit currents are strongly influenced by the chosen logic style.

2.9.2 Logic Style Requirements for Low Power According to the formula:

Pdyn = V2dd. fclk . ∑nαn .cn + Vdd. ∑niscn1.1 The dynamic power dissipation of a digital CMOS circuit depends on the supplyvoltageVdd, the clock frequency fclk the node switching activities αn, node capacitances cn, the node short- circuit currents iscn, and the number of nodes n. A reduction of each of these parameters results in a reduction of dissipated power. However, clock frequency fclk reduction is only feasible at the architecture level, whereas at the circuit level frequency is usually regarded as constant in order to fulfill some given throughput requirement. All the other parameters are influenced to some degree by the logic style applied. Thus, some general logic style requirements for lowpower circuit implementation can be stated at this point.

2.9.3 Switched capacitance reduction Capacitive load, originating from transistor capacitances (gate and diffusion) and inter- connect wiring, is to be minimized. This is achieved by having as few transistors and circuit nodes as possible, and by reducing transistor sizes to a minimum. In particular, the number of (high- capacitive) inter-cell connection and their length (by the circuit size) should be kept minimal. Another source for capacitance reduction is found at the layout level. Transistor downsizing is an effective way to reduce switched capacitance of logic gates on noncritical signal paths. For that purpose, a logic style

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should be robust against transistor downsizing, i.e., correct functioning of logic gates with minimal or near minimal transistor sizes must be guaranteed.

2.9.4 Supply voltage reduction The supply voltage and the choice of logic style are indirectly related through delay-driven voltage scaling. That is, a logic style providing fast logic gates to speed up critical signal paths allows a reduction of the supply voltage in order to achieve a given throughput. For that purpose, a logic style must be robust against supply voltage reduction.

2.10 Design Depiction VLSI

configuration

style

basically

utilizes

three

areas

of

plandepiction,viz.Thebehavioral, the portrayal of the capacity of the plan; the auxiliary, the depiction of the type of the usage; and the physical, and the depiction of the physical execution of the outline.There are numerous conceivable portrayals of a circuiting every depiction, and a reasonable selection of portrayals is critical in instrument designee. The VLSI designee style is appeared in beneath. Towards the start of a plan, it is vital to determine the prerequisites without unduly limiting the outline. The question is to portray the reason for the outline including all angles, for example, the capacities to the acknowledged, timing imperatives, and power dissemination necessities, and so on. Depictions in piece level may indicate either information stream, control system, or both. The individual squares by and large compared to equipment modules. The utilitarian plan determines the practical connections among subunits or registers. By and large, a portrayal of the IC in either the practical or the piece chart space comprises both information yield depiction, and how conduct is to be acknowledged as far as subordinate modules.

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Fig.2.10 . VLSI Design Style

Chain of importance and measured quality are utilized as a part of piece outlines or PC programs. In these spaces pecking, order smothers superfluous points of interest, improves framework plan through a “partition and overcome” system and prompts even more effectively comprehended outlines that areeven more promptly fixed and archived.

2.10.1 Full Custom Design Full-hand craft is a technique for planning coordinated circuits by determining the format of every individual transistor and the interconnections between them. Other options to full-hand craft incorporate several types of semi-specially craft, for example, the redundancy of little transistor sub circuits; one such strategy is the utilization of standard cell libraries is appeared in beneath. Full-hand craft possibly boosts the execution of the chip, and limits its range, yet is greatly work escalated to actualized. Full-specially craft is constrained to IC’s that are to be manufactured in greatly high volumes, strikingly certain chip and few ASICs.

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

Full-custom format driven by zone confinements or extraordinary application

needs; this sort of design is comprised of rehashed complex structures like sense speakers and decoders. 

Adders, multipliers-when all is said in done, an informative way with tight

control over the region, flag commotion, bit symmetry. We allude to this kind of format as “information way design”. 

Full-custom format to address elite or simple hardware outline: this incorporates

stage bolted circles i.e., PLL, computerized to-simple converters or simple to advanced converters like/known as DACs/ADCs, electrostatic release known as ESD structures, controllers, radio recurrence i.e., RF speed necessities, or systems to meet low-control needs. We call this sort of format “uncomplicated design’. 

Full-custom format that requires more prominent consideration regarding region

and execution than the full advanced i.e., ASIC stream yet has less stringent prerequisites for speed and less requirement for control over gadget level design than information way or simple format: we call this kind of format “custom computerized design”. Full-custom design for cell improvement: cells are characterized as legitimate building obstructs that is a piece of a group of segments that offer normal projection rules, execution attributes, or usefulness. Cases would incorporate the cells inside a standard cell library or group of pad cells. We should call this kind of design “cell format”. 

All four sorts of full-custom format are driven by a schematic-based plan style

versus a dialect-based outline style which utilizes Verilog or VHDL the reason for the ASIC configuration stream. Each of these full-custom design classifications ought to be utilized as expected to accomplish the general prerequisites of the IC being worked on and, when all is said in done, the tradeoffs between the format styles based on region and execution contemplations.

2.11 Introduction of MOS 2.11.1 MOS Device

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The area demonstrates the CMOS transistor, its design, static qualities and dynamic characteristics. The vertical piece of the device and the three-dimensional layout of the products are in like manner portrayed.

2.11.2 MOS as a switch The MOS transistor is basically a switch. Exactly when used as a piece of reason cell layout, it can be on or off. At whatever point on, a current can stream among drain and source. At whatever point off, no present stream among exhaust and source. The MOS is turned on or off dependent upon the portal voltage. In CMOS advancement, both n-channel or N-MOS and the p channel MOS or P-MOS gadget exist. The N-MOS and P-MOS pictures are represented underneath. By then channel MOS is produced using poly silicon as the door material and N+ spread to manufacture the source and exhaust. The p-channel MOS is gathered using poly silicon as the entry way material and p+ spread to fabricated the source and drain. The pictures for the ground voltage source is 0 (or) VSS and the supply is 1 (or) VDD.

Fig.2.11.2 MOS Symbol

The N-channel MOS contraption requires a rationale esteem 1 (or) a supply VDD to be on. In the inverse, the p-channel MOS device requires a rationale esteem 0 to be on. Right when the MOS device is on, the association between the source and exhaust is indistinguishable to a security. He ask for or extent of this ‘on’ assurance is 100W5KW. The off resistance is seen as unlimited at first demand, as its esteem is a couple of MW.

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2.12 CMOS Complementary metal oxide semiconductor, abbreviated as CMOS, is a development for building coordinated circuits. CMOS innovation is utilized as a part of a chip, microcontrollers, static RAM, and other propelled method of reasoning circuits. CMOS development is similarly used for a couple of basic circuits, for instance, picture sensors, data converter, and extremely consolidated handsets for a few sorts of correspondence. In the year 1963, Frank Wanlass who was working for Fairchild Semiconductor, authorized CMOS. CMOS is suggested as correlative symmetry metaloxide-semiconductor or COS-MOS from time to time. CMOS is moreover from time to time suggested as correlative symmetry metaloxide-semiconductor or COS-MOS. The words “comparing symmetry” suggest the way that the ordinary arrangement style with CMOS uses correlative and symmetrical arrangement of p-sort and n-sort metal oxide semiconductor field effect transistors i.e., MOSFET’s for justification limits.

Fig.2.12 CMOS Inverter

Two imperative attributes of the CMOS device are high commotion invulnerability and low static power utilization. Since one transistor of the match is constantly off, the arrangement mix draws noteworthy power just quickly amid turning amongst on and off states. Thus, CMOS device doesn’t deliver as much waste warmth as several types of rationale, for instance, transistor rationale i.e., TTL or N-MOS rationale, which ordinarily make them stand currently notwithstanding when not evolving state. CMOS likewise permits a high thickness of rationale works on a chip. It

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was essentially thus that CMOS turned into the most utilized innovation to be executed in VLSI chips.

2.12.1 N-MOS Logic N-sort metal-oxide-semiconductor reason uses n-sort field effect transistors i.e., MOSFET’s to execute method of reasoning gateways and other automated circuits. These N-MOS transistors work by influencing an inversion to layer in a p-sort transistor body. This inversion layer, called the N-channel, can lead electrons between n-sort “source’ and ‘exhaust” terminals. The N-channel is made by applying a voltage to the third terminal, called the entryway. N-MOS transistor has four techniques for operation like cut-off, triode, inundation and speed drenching The MOSFET’s are n-sort redesign mode transistors, organized in a gathered “pull down Network’ i.e., PDN between the method of reasoning entryway yield and negative supply voltage which is consistently the ground. A draw up i.e., a “stack” that can be thought of as a resistor, see underneath is set between the positive supply voltage and each justification entryway yield. Any method of reasoning passage, including the logical inverter, would then have the capacity to be realized by illustrating an arrangement of parallel and also course of action circuits, to such a degree, to the point that if the desired yield for a particular blend of Boolean data regards is zero (or) false, the PDN will be dynamic, inferring that no short of what one transistor is allowing a present route between the negative supply and the yield. This cause a voltage drop over the stack and in this way a low voltage at the yield, addressing the zero. Form long ago; these N-MOS circuits were considerably speedier than equivalent P-MOS and CMOS circuits, which is needed to use P-channel transistors which are slow. It was likewise less demanding to produce N-MOS tan CMOS, as the last need to execute p-direct transistors in uncommon n-wells on the p-substrate. The real disadvantage with N-MOS and most other rationale families is that a DC current must course through a rationale door notwithstanding when the yield is in a relentless state low in account of N-MOS. This implies static power scattering, i.e., control deplete notwithstanding when the circuit isn’t exchanging.

2.12.2 P-MOS Logic

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P-type metal oxide semiconductor rationale utilizes P-channel metal oxide semiconductor field impact transistors i.e., MOSFET’s to execute rationale doors and other advanced circuits. P-MOS transistors work by making a reversal layer in an Ntype transistor body. This reversal layer, called the p-channel, can lead openings between p-type “source” and “deplete” terminals. The p-channel is made by applying a voltage to the third terminal, called the door. Like typical MOSFET’s, P-MOS transistors has four methods of operation which are cut-off, triode, immersion i.e., dynamic and speed immersion. While P-MOS rationale is anything but difficult to outline and produce a MOSFET can be made to work as a resistor, so the entire circuit can be made with PMOS FETs, it has a few deficiencies too. The most exceedingly terrible issue is that there is an immediate current i.e., DC through a P-MOS rationale entryway when the PUN i.e., “Pull Up Network’ is dynamic, that is, at whatever point the yield is high, which prompts static power scattering notwithstanding when the circuit sits out of gear. The P-MOS circuits are ease back to progress from high to low. When there is a change in the transition from low to high, the transistors gives low protection and the capacitive charge at the yield collects rapidly like charging a capacitor at the output with a low protection. Be that as it may, the protection between the yield and negative supply rail is substantially more noteworthy, so the high-to low change takes longer like the release of a capacitor through a high protection. Utilizing a resistor of lower esteem will accelerate the procedure yet, in addition, builds static power scattering.

3 SOFTWARE DESCRIPTIONS 3.1 Tools Used The tools used in the thesis are as follows: Simulation Software: Cadence EDA Tool

3.1.1 Boolean Algebra Boolean algebra is the field of mathematics that deals exclusively with the set of values consisting of True and False [8]. It is the mathematical foundation for all digital Department of ECE,NNRG

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electronics, and a review of this subject is absolutely necessary to understand the design of the adder. In addition, we will see how Boolean algebra provides useful abstractions for the construction of virtually any type of digital circuit.

3.1.2 Logical Operations and Truth Tables Logical operations are operations that output the Boolean values True or False (1 or 0) from a series of Boolean inputs. The simplest conceptual example of the logical operation is the AND operation, which takes two inputs A and B. The output of the AND operation will be 1 (True) if and only if both A and B are also 1; the output will be 0 otherwise. While these operations may seem useless by themselves, it turns out that the judicious combination of logical operations result in the construction of arithmetic operations, including addition. To that end, I will study many types of logical operations for future use in the adder, including the NOT, NAND, OR and XOR operations, and an implementation of each operation using transistors is provided in Appendix I. Table 3.1.2 provides an example of some common logical operations in the form of their truth tables, in which all possible combinations of the inputs A and B are listed with their corresponding outputs. Truth tables are a useful tool for the construction of more complex Table 1: From left to right: truth table representations of the NOT, AND, OR, and NAND logical operations. A horizontal bar over a value indicates that its value has been inverted: e.g. A = NOT(A). Also note that the “.” symbol is the logical AND symbol, while is the logical OR symbol l.

Table:3.1.2

A A 0 1 1 0

A 0 0 1 1

B 0 1 0 1

A•B 0 0 0 1

A 0 0 1 1

B 0 1 0 1

A+B 0 1 1 1

A 0 0 1 1

B 0 1 0 1

A•B 1 1 1 0

Operations, most of which will have far more than two inputs and one output. These tables allow us to write the output in terms of its specified inputs. Take for example, the following truth table that has three inputs A, B and C:

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A B C OUT 0 0 0 0 0 0 1 1 0 1 0 1 0 1 1 0 1 0 0 1 1 0 1 0 1 1 0 0 1 1 1 0 Table : 3.1.3 An Example Truth Table. This truth table has a range of input combinations, only three of which output 1. We can write this mathematically using the following notation: OUT = A • B • C + A • B • (7 + A- B- CJ. In this expression, the symbol refers to the logical OR operation, while the “ s ym b o l is the AND operation. It is very convenient to write out truth tables as combinations of these operations, because the AND and OR operations are commutative, associative, and distributive over each other [8] (a more complete list of the properties of logical operations is provided in Appendix II). This means that OUT could be written many different ways,including the following: OUT = A • B • C + A • B . (7 + A- i? - CJ =A • (B • C + B • C) + A • B • C = A . B . C +

C

7 ( A . B + A . B ) =etc.

The properties of these logical operations make them extraordinarily useful to physicists and engineers, as it gives them the flexibility to choose between many possible implementations of the same function (some of which may be much easier than others to actually build). To see this, let us look at the example of the XOR gate. Example: The XOR Gate

The XOR gate, also called the “exclusive-OR gate”，is a modified version of the OR gate, in which the output is 1 if A or B is 1, but 0 if both A and B are 1. Its truth table is given below, and at first glance it does not seem much more complex than any of the gates listed above; however, it is deceptively challenging to actually implement using discrete transistors. As an exercise, let us apply some of the principles of Boolean algebra to implement the XOR gate as a combination of simpler logical opera tions.

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A 0 0 1 1

B 0 1 0 1

A㊉B 0 1 1 0

Table 3.1.4 A ㊉B = A • B + A • B. By the Complementation and Identity over OR Laws (see Appendix II), I can also add the following terms without changing the output: A ㊉B = B • A + A • B + A • A + B • B. The additions of these terms allows us to simplify the expression: A ㊉B = B • A + A • B + A • A + B • B=A(B+ A) + B(B+ A)(Distributive over OR) =(A + B) • (B+ A)(Distributive over AND) =(A + B) • (A • B)(De Morgan’s Law) This result is something that can be easily implemented. It consists of an OR operation, a NAND operation, and then performs an AND on the two results. Hence, the XOR gate can be implemented in the following way:

Fig: 3.1.4 XOR GATE For a transistor-level implementation of this gate, see Figure 10 in Appendix I.

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This is a very simple example of how the principles of Boolean algebra can be used to design a digital circuit from logical operators. Although addition is a more complicated operation than XOR, the ideas and techniques illustrated here will translate over to the design of the adder very nicely Example: Implementation of the NAND gate using MOSFET,s

Fig3.1.5: Implementation of the NAND gate using two n-type MOSFET’s. This circuit has inputs A and B, and an output A- B. So far in this section, I have discussed how logical operations can be used to construct digital components, but how can transistors be used to implement these logical operations in the first place? For example, consider the NAND gate, which has an output of 0 if both of its inputs are 1, and an output of 1 otherwise (refer to Table I for the full truth table). This function can be created by attaching two n-type MOSFET’s in series, with one transistor’s source terminal attached to the other’s drain terminal (see Figure 5). The output of such a circuit would be 0 if both A and B were 1, because both transistors would be allowing current to pass through directly to ground. If only one (or neither) transistor were on, then the output would have to be high. There were some design choices made in Figure 5. For one, the values of the voltage source and the pull-up resistor are arbitrary, depending on what output current is desired. Also, Figure 5 does not represent the only possible implementation of the NAND gate. There are many possible variations, some of which may be more elegant than the one pictured above. However, it is the opinion of this author that Figure 5 represents the simplest implementation of the NAND gate that is to be constructed using

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discrete components; were I to be designing a true integrated circuit, I might consider another method. This NAND gate implementation will be used for the construction of the adder, as will many other types of logic gates. For a complete list of all logic gates used, and their transistor- level implementations, refer to Appendix I.

3.1.3 Binary Encoding: the 2JsComplement Method 1. Having established how the principles of Boolean algebra can be used to design digital circuits, we now look at how complex information can be written only using only the allowed values of 0 and 1. There are many ways to translate information into binary values, including the 1’s complement, 2’s complement, and Signed Magnitude methods. In this paper, I will discuss the 2’s complement method, as it allows both positive and negative numbers to be written in binary form. 2.The easiest way to understand 2’s complement is to start with a binary string, for example: 00101111. The lowest-ordered bit is the bit farthest to the right (1 in this case). The highest-ordered bit is the bit farthest to the left (0 in this case). The method for converting this string into an integer is as follows: the integer value of the lowestordered bit corresponds to the product of 20 and the magnitude of the lowest-ordered bit. Take this value, and add it to the product of 21 and the magnitude of the next-lowest ordered bit. Continue by adding this sum to the product of 22 and the magnitude of the next-lowest ordered bit, and so on until you reach the next-to-highest ordered bit. Using our example string 00101111, this corresponds to: 3.(1 • 20) + (1 • 21) + (1 • 22) + (1 • 23) + (0 • 24) + (1 • 25) + (0 • 26) + (0 • 27) = 47. 4

The conversion from integer to binary is slightly more involved than binary-to-integer, but is still relatively straightforward. Take an example integer, say 107. First, find the largest power of two that is less than or equal to that integer. Recall that 2 6 is 64, but 27 is 128, so 6 is the highest power of 2. This tells us we need 8 bits to represent this number: 7 to represent magnitude (not 6: remember the 0th order is included), and one to represent sign. 107 is positive, so the sign bit (the highest-ordered bit) will be zero. The next-highest ordered bit represents the factor of 26, which is less than 107, so it will be a 1. Then, take 107 - 64 to get 43. Now, we again find the highest power of two less than or equal to 43. In this case, we remember that 25 is 32, so the the bit corresponding

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to 25 will also be a 1. Repeat this process again: 43 32 is 11. 23 is 8, but 24 is 16. Therefore, the bit corresponding to 24 will be 0, and the bit corresponding to 23 will be a one. Continuing on: 11 - 8 is 3, so the 21 bit will be 1 and the 22 bit will be 0. Finally 3 2 is 1, so the lowest-ordered bit will be a 1. This results in: 5 6

107 = (1 • 26) + (1 • 25) + (0 • 24) + (1 • 23) + (0 • 22) + (1 • 21) + (1 • 20) = 01101011. Note that in our previous examples, both integers were positive. If the integer is negative (or we know that the resulting integer should be negative), the conversion is a little harder. In 2's complement, the most-significant bit determines the sign of the integer. If it is a 0, the corresponding integer is positive; if it is a 1, the integer is negative. However, under the 2's complement method we cannot simply flip the leftmost bit and expect the sign to change while leaving the magnitude the same (the Signed Magnitude method actually does do this). Instead, for 2's complement, when confronted with a negative bit string like 11101011, we must do the following procedure: invert all of the bits, and then add 1 to it. Flipping the bits results in 00010100. Adding 1 to this, we get 00010101. Now, we can convert this to integer using the same method outlined above: 00010101 = 21, but we have already determined

7

that our integer is negative, so 11101011 is equivalent to -21.

8

3.1.4 Limitations of 25s Complement 2’s complement is not a perfect representation of data. The keen observer may ask, what if I want to represent a fraction or a decimal in binary? For that matter, what if I want to represent a letter or some other non-numerical character in binary? These are things 2’s complement does not do well, and other encoding schemes are advised if those are your goals. However, 2’s complement is a fine way to represent integers as binary, which will allow us to perform arithmetic operations on numbers going forward. In addition to being an imperfect representation of non-integer data, 2's complement has other limitations that we must be aware of. First, consider the case where a device has a set 8-bit architecture. If this device uses the 2’s complement method, it only has 7 bits to assign magnitude because 1 bit is necessary to determine sign. While this does allow for the use of negative numbers, it effectively halves the range of allowed values. Another issue that will arise during the design of the adder is the problem of overflow. Consider again the case of an 8-bit architecture, which allows for values

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between -128 and 127. Suppose we want to use our device to add 120 and 9. Both are valid integers under this architecture, but their sum of 129 is not. A conscientious user will be aware of this limitation and take steps to avoid it during use, but finding a way to alert the user that overflow has occurred will be an important part in the design of the adder.

3.2 Design of the Adder 3.2.1 Binary Addition Binary addition is similar in many respects to decimal addition, but there are some important differences. Consider the following example: 0100 1001 + 0001 1111 ? Binary addition, much like decimal addition, proceeds for each pair of bits from right to left. However, we must remember the digits for the sum are also restricted to 0’s and 1’s. Therefore, when we add the first two right-most bits (1 and 1), we actually get 0, with a carry-out of 1. This carry-out is then added to the next pair of bits, just like it would be in arithmetic addition. This example would then proceed as follows: 00011 1110 0100 1001 (73) + 0001 1111 (31) 0110 1000 (104) For this example, the top row represents the carry-outs for each pair of bits. For clarity, I also included the decimal equivalents on the side. Notice that in this example, I assumed an initial carry-in of 0. This is reasonable, but must not be assumed to always be true. So for each pair of bits, the adder will have three inputs (A, B, and Cin) and two outputs (SUM and Cant). I have established that two 1’s produce a sum of 0 and a carry-out of 1. The only other rule to remember is that if two 1’s are added, and the carry-in is also 1, then both SUM and carry.

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A 0 0 0 0 1 1 1 1

B 0 0 1 1 0 0 1 1

G

in 0 1 0 1 0 1 0 1

SUM 0 1 1 0 1 0 0 1

G

out 0 0 0 1 0 1 1 1

Table 3.2.1 : The Full-Bit Adder Truth Table.

Gout are also 1. From these rules a truth table for the adder can be produced, which is given on Table 4. Table 4 provides the basis from which a 1-bit adder can be constructed. Generally speaking, however, merely adding one bit to another bit is not that interesting. Much more interesting would be creating a circuit that could compute the above example, which contained two 8-bit inputs. This is entirely possible to do, since the operation is exactly the same for each pair of bits. All that we need to do is design multiple 1-bit adders from Table 4, and connect them in series such that Gout from the first pair of bits is Gin for the second pair, and so on. This serialization of 1-bit adders through the carryout is the defining feature of the “ripple-carry” adder.

3.2.2 1-Bit Adder Table 4 tells us that our circuit will have two distinct outputs, SUM and Gout. Let us work with just one at a time, starting with SUM. Using the Boolean algebraic methods outlined previously, we can write SUM as: SUM = A • B • G + A • B • (7 + A- iB- (7 + A- B- G. We can rewrite and simplify this expression as follows: SUM = ,4 • B • Cin+ A • B • 0~+ A • B • 0~ + A • B • Cin = C i n • (A • B + A • B) + Cin • (A • B+ A • B)(Distributive over OR) = C i n • (A ㊉B) + Cin • (A ㊉B)(Definition of XOR) Cin㊉(A ㊉B)(Definition of XOR)

=

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This last equation is something that can be easily implemented using two XOR gates, which w

Fig: 3.2.1 Design of the SUM component of the full-bit adder using two XOR gates. As developed previously (see Figure 4). Figure 6 illustrates this component of the adder. Now for the carry-out. Cout can be written as: C

out = A • B • Cin+ A • B • C+ A • B • Cin+ A • B • Cin

= C i n • (A • B + A • B) + (A • B) • (Cin+ Cin)

(Distributive over OR)

=Cin • (A ㊉B) + A • B

(Def. of XOR, and

Complementation Law) This result for Cout is simple enough to implement, especially since I already have an XOR gate that compares A and B for the sum. I can reuse the output for that gate to reduce the number of total gates in the adder like so:

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Fig: 3.2.2 The complete full-bit adder. Note that the multi-colored wires indicate that there is no junction where they cross. Figure 7 represents the complete 1-bit adder, which I can implement and duplicate four times to make a 4-bit, ripple carry adder.

3.2.3 4-Bit Adder The design of the 4-bit adder, based on the 1-bit adder, is almost trivial. As stated previously, all we need to do is duplicate the 1-bit adder four times, and connect each carryout to the carry-in of the next adder in the series. This design scheme is presented graphically in Figure 8. This method for constructing a multi-bit adder is perfectly extendable, so much so that it would not be challenging to design even a full 64-bit adder.

Fig: 3.2.3 A graphical representation of the 4 bit adder with ripple carry Again, however breadboard space is apremium, especially when working with bulky discrete components, so I will only be building a 4-bit adder.

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3.2.4 Overflow Detection Earlier while discussing the limits of 2’s complement encoding, I brought up the issue of overflow. Recall that overflow occurs when two valid binary numbers are added, but an invalid answer is returned. There are two ways this can happen: when two positive numbers are added and a negative number is returned, or when two negative numbers are added and a positive number is returned. For example, take the two positive 4-bit binary strings 0111 and 0100, and add them together. The result of this operation is the following: 0111

(7)

+ 0100

(4)

1011 (-5?) Notice that the result (1011) is a negative value under the 2’s complement method, but logically this cannot be: the sum of two positive integers cannot be negative. The reason for this error has to do with the number of bits we are using. In this example, we only use four bits under the 2’s complement scheme which restricts our range of values to -8 to 7. If the sum is outside this range, an incorrect value will be returned. Also notice that when this error occurs, regardless of the exact values of either initial integer, the penultimate carry-out must be a 1. If it were not, there would be no way for the most-significant bit of the result to be a 1, since both most-significant bits of the initial values are 0 by definition. This also means that the very last carry-out will be a 0, because 1 + 0 + 0 = 1, with no carry. Next, consider the case of adding two negatives together to get a positive. Try adding the values 1001 and 1010: 1001 (-7) + 1010 (-6) 0011 (3?) In this case, it is the final carry-out bit that must be a 1, because both mostsignificant bits of the inputs were 1, by definition. Also, the penultimate carry-out must be a 0, otherwise the final answer would be negative. From these two cases, a solution for overflow detection can be derived. We have shown that if either the last carry-out bit or the next-to-last carry-out bit are 1, but not both and not neither, then overflow has occurred. Therefore, the solution is to XOR the

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last and next- to-last carry-outs. If the result is 1, then there has been overflow. If it is 0, the sum is valid. This XOR gate is visualized in its appropriate place in Figure 9, and will be implemented during the construction of the adder.

3.3 Adders architecture In electronics, an adder or summer is a digital circuit that performs addition of numbers. In many computers and other kinds of processors, adders are used not only in the arithmetic logic units, but also in other parts of the processor, where they are used to calculate addresses, table indices, and similar operations. Although adders can be constructed form any numerical representations, such as binary-coded decimal orexcess3, the most common adders operation binary numbers. In

cases where two’s

complement or one’s complement is being used to represent negative number.

3.3.1 Half adder The half adder is an example of a simple, functional digital circuit built from two logic gates. The half adder adds to one-bit binary numbers (AB). The output is the sum of the two bits(S) and the carry(C). Note how the same two inputs are directed to two different gates.

Fig3.3.1: Schematic diagram of half adder

Table:3.3.1

3.3.2 Full adder A full adder adds binary numbers and accounts for values carried in as well as

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out. A one-bit full adder adds three one-bit numbers, often written as A, B and Cin; A and B are the operands, and Cin is a bit carried in from the previous less significant stage. The Full adder is usually a component in a cascade of adders, which add 8,16, 32, etc. bit binary numbers. The circuit produces a two-bit output, output carry and sum. Whereas the equation of the sum and carry is

S=AXORB ;------------------------------------------(1) Cout=AANDB ; --------------------------------------------(2)

Fig3.3.2schematicdiagramoffulladder

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Table3.3.2: Truth table of Full adder (1Bit)

3.4 Ripple Carry Adder Arithmetic operation like addition, subtraction, multiplication, division are basic operation to be implemented digital computer using basic gates among all arithmetic operation if we can implemented addition then it is easy toperform multiplication repeated addition. Half adders can be used to add two one bit binary numbers. It is also possible to create a logical circuit using multiple adders to add N bit binary number, each full adder inputs carry, which is the output carry of the previous adder. This kind of adder is a ripple carry adder, since each carry bits “ripples” to the next full adder .the first full adder may be replaced by the half adder.

Fig 3.4: Ripple carry adder

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3.4.1 Carry look-ahead adder: The ripple-carry adder, its limiting factor is the time it takes to propagate the carry. The carry look-ahead adder solves this problem by calculating the carry signals in advance, based on the input signals. The result is a reduced carry propagation time. To be able to understand how the carry look-ahead adder works, we have to manipulate the Boolean expression dealing with the full adder. The Propagate P and generate G in a full-adder, is given as: Pi= Ai⊕ BiCarry propagate Gi= AiBi

Carry generator

Notices that both propagate and generate signals depend only on the input bits and thus will be valid after one gate delay. The new expressions for the output sum and the carryout are given by Si= Pi⊕ Ci-1 C = G+ PC i+1

i

i

These equations show that a carry signal will be generated in two cases: 1) if both bits Aiand Biare 1 2) if either Aior Biis 1 and the carry-in Ciis 1. Let's apply these equations for a 4-bit adder: C1 = G0 + P0C0 C2 = G1 + P1C1 = G1 + P1(G0 + P0C0) = G1 + P1G0 + P1P0C0 C =G +P C =G +P G +P P G +P P P C 3

2

2 2

2

2

1

2 1

0

2 1 0 0

C4 = G3 + P3C3 = G3 + P3G2 + P3P2G1 + P3P2P1G0 + P3P2P1P0C0 These expressions show that C2, C3 and C4 do not depend on its previous carry-in. Therefore C4 does not need to wait for C3 to propagate. As soon as C0 is computed, C4 can reach steady state. The same is also true for C2 and C3

The general expression is Ci+1= Gi + PiGi-1 + PiPi-1Gi-2 + ……. PiPi-1….P2P1G0 + PiPi-1 ….P1P0C0.

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This is a two level circuit. In CMOS however the delay of the function is non linearly dependent on its fan in. Therefore large fan in gates are not practical. Carry look-ahead adder’s

structure can be divided into three parts:

the

propagate/generate generator Fig.1, the sum generator Fig. 2 and the carry generator Fig.

Fig 3.4.1 Carry Look ahead Adder

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3.4.2 Carry select adder A Carry Select Adder is a particular way to implement an adder, which is a logic element that computes the (n+1) bits um of town-bit numbers. The carry-select adder is simple but rather fast. The carry-select adder generally consists of two ripple carry adders and a multiplexer. Adding town-bit numbers with a carry-select adder is done with two adders(therefore two ripple carry adders) in order to perform the calculation twice, one time with the assumption of the carry being zero and the other assuming one. After the two results are calculated, the correct sum, as well as the correct carry, is then selected with the multiplexer once the correct carry is known.

Fig 3.4.2 Carry select adder

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4 SOFTWARE DESCRIPTION 4.1 Introduction The intentions for this manual is to serve as an introduction to the Cadence design environment and describe the methodology used when designing integrated circuits. The department is not giving courses in Cadence but in integrated circuit design so only the minimum knowledge, needed to run the laboratories, of Cadence can be gained from this manual. Also this manual describes the environment currently at the department which is Cadence version 4.45 in conjunction witch a Design Kit from AMS (Austria Mikro System International AG) which contains a set of rules and designs for a 0.35 µm CMOS process. For a more thorough understanding of Cadence the extensive on line manual set is recommended. These are accessed from any of the tools by pressing the help button. More information about the topics in the first two chapters can be found in the manuals Design Framework II Help and Cadence Application Infrastructure User Guide. The Cadence tool kit consists of several programs for different applications such as schematic drawing, layout, verification, and simulation. These applications can be used on various computer platforms. The open architecture also allows for integration of tools from other vendors or of own design. The integration of all this tools is done by a program called Design Framework II (DFW). The DFW-application is the cornerstone in the Cadence environment. It provides a common user interface and a common data base to the tools used. This makes it possible to switch between different applications without having to convert the data base. ECE Department NNRGIES

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This chapter will give an overview of the user interface supplied by DFW and present some of the Cadence tools that will be used.

4.2 Importance of Cadence Tool Cadence is a leading provider of EDA and semiconductor IP. Their custom/analog tools help engineers design the transistors, standard cells, and IP blocks that make up SoCs. Their digital tools automate the design and verification of gigascale, giga-hertz SoCs at the latest semiconductor processing nodes. Their IC packaging and PCB tools permit the design of complete boards and subsystems. Cadence also offers a growing portfolio of design IP and verification IP for memories, interface protocols, analog/mixed-signal components, and specialized processors. And reaching up to the systems level, Cadence offers an integrated suite of hardware/software co-development platforms. In short, Cadence® technology helps customers build great products that connect the world. Which makes Cadence a world’s #1 VLSI Software Company in Silicon Valley, CA, USA. The goal of the Cadence® University Software programs is to grant easy access to leading electronic design automation (EDA) tools for educational institutions around the world. Customers rely on skilled engineers entering the work force. As the leader in electronic design automation, they are committed to helping their customers by giving future engineers access to their world-class tools. In fact, they reach over thirty thousand students each year through these programs. By making their products readily available for instruction and academic research, Cadence is helping the electronics industry speed ideas to reality.

Cadence Design Systems, a leader in EDA (Electronic Design Automation) technologies and has been in the forefront, offering complete VLSI solutions. Cadence’s India University Software Program has been very unique, aimed at developing trained manpower trained on world-class tools that are used by the industry today. Now The Software program is stared at Bangladesh. ECE Department NNRGIES

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4.3 Cadence User Interface In Cadence the user interface is graphic and based on windows, forms, and menus. The main windows of DFW are: Command Interpreter Window (CIW) is controlling the environment. Other tools can be started from here and it also serves a log window for many applications. Library Manager gives a view of the design libraries and the different constructions that exists therein. Design Window (DW) shows the current design. It is possible to have several DW opened at the same time with different, or the same, tools. Text Window (TW) shows text. It can be a log or report that was asked for, or an editor. The menus in Cadence are mostly pull-downs, i.e. the menu will appear when the title are clicked with the left button on the mouse. There are also pop-up menus that appear in the background of the design window on a middle button press. The forms are used for entering some specific information that is needed by the function called, the size of a transistor for instance.

4.4 Getting Started Log in to your workstation utilizing the username an secret key. The home index has a cshrc record with ways to the Cadence establishment.

In a terminal window, sort csh at the summon provoke to conjure the C shell.  Csh  Source cshrc

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To check that the way to the product is legitimately set in the cshrc document, sort the beneath summon in the terminal window and enter: > Which virtuoso It gives the entire way of IC617 instrument Installation. >which apparition It gives the total way of MMSIM101 apparatus Installation. >which assura It gives the total way of Assura410 apparatus Installation.

4.5 Starting of Cadence Utilize the introduced database to do your work and the means are as per the following: Change to course registry bh entering this charge >cd~/Database/cadence_analog_613 You will begin the rhythm outline structure II condition from this registry since it contains CSD.lib, which is the nearby introduction record. The library look ways are characterized in this record. The cadence_analog_613 registry contains arrangements organizer and furthermore work envelope. Inside work envelope you can make new cell/alterations of the phone locally without influencing your source cell show inside arrangements catalog. /solution - Contains an area copy of all the workplace experiments as well as check circuit for simulation. /libs.cdb - Contains a technology library for the planning (gpdk 180nm). /models - Contains spectra models of elements for simulation in gpdk180nm technology. /stream - Contains layer map file for GDSII format /pv- Containing the Assura and Diva verification files /tech files - contains ASCII versions of OA22tech files ECE Department NNRGIES

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/dig_source - Contains Verilog codes for SAR register and clock/cds. lib -File containing pointer to the Cadence OA22 formatting file. /cds.lib - File containing pointer to the cadence OA22 initialisation file. /hdl.var - file defines the work library for AMS simulation /docs - manual and user manual for gpdk180nm technology. /docs - Reference manual and user manual for gpdk180nm technology. In the same terminal window, enter: Virtuoso& The virtuoso or Command Interpreter Window (CIW) shows up at the base of the screen

Fig.4.5 Virtuoso window

If the "What's New..." window appears close it with the File Close command. ECE Department NNRGIES

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Keep opened CIW window.

4.6 The Design Process The design tools have a common structure of the designs. It is hierarchical and consists of libraries, views, and instances.

4.6.1Libraries and Views All design data in Cadence are organized in libraries. There are Reference Libraries which contains basic building blocks usable in the construction and Design Libraries which embodies the current design. Every library consists of cells and their different views, as in fig. A cell is a database object which forms a building block, an inverter for instance. A view represents some level of abstraction of the cell. It can be a schematic drawing, layout, or maybe some functional description.

4.6.2 Instances and Hierarchy The main reasons for using hierarchical designs are to save design time and minimize the size of the data base. Say that a design would need 500 gates of the same type. Then instead of building it 500 times, it is designed once and then used were it is needed. In this way one cell can be used (not copied) several times and each such use is called an instance of the cell. In order to be instantiated every cell needs a symbol view which acts as a handle to the cell it represents. Only the symbol is shown when a cell is instantiated. Thus by creating more complex structures by instantiating simple instances a hierarchical design is formed. It is possible to move up and down and work on a selected level in the hierarchy. When a design is opened, the highest level is the default one.

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Since there are different semiconductor processes (with different set of rules and properties), Cadence has to know the specifications for the one that is to be used. This information is stored in a set of files called Technology Files which exists on different locations on the system. When a library is created it is therefore connected to a specific technology. The technology files contains information about: Layer definitions: Conductors, contacts, transistors... Design rules: minimum size, distance to objects... Display: Colours and patterns to use on the screen. Electrical properties: resistance, capacitance... The technology files are usually supplied by the silicon vendor, that is to fabricate the design, along with some libraries of standard cells and IO pads that can be used by the designer. Such a collection is called a Design Kit.

4.6.4 The SKILL Programming Language When a command is performed, from a form or a menu, the system is executing functions written in the SKILL language. SKILL is developed by Cadence and is based on Lisp. The Cadence tools are using SKILL for internal communication and for the tool-design communication. SKILL is also accessible for the designers. Commands can be written in the CIW- window or placed in command files for execution. it can be used for simple tasks like executing a command or building more complex functions to perform various tasks. 4.6.5 The Design Flow The abbreviated flow in figure 3.3.5 shows some of the steps in designing integrated circuits in the Cadence environment.

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FIG 4.6.5 Design Flow The step Create the Design consists of drawing schematic views of all cells and blocks. The schematic view contains transistor symbols, and maybe other components such as resistors and capacitances, and wires connecting them. From the schematic view

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the symbol view is created (almost automatically) so that the cell can be used on a higher level in the hierarchy. The step analyse the design includes functional verification (simulation) of the design on a schematic level. The third step, Create Layout, is done in a Layout Editor. Here the final semiconductor layers are represented by different colours. All the cells and blocks used have the size they will have on the final chip. The last step is Verification of the design. The layout is examined for violations against the geometric or electrical rules, and to verify the function of the physical implementation.

4.7 Schematic and Symbol tools To create the schematic the tool Virtuoso Schematic Composer is used. This editor is an interactive system for building schematics by instantiating some basic components (transistors, capacitances, etc.) and to connect them to each other. The values (properties) of the components can be edited to suit the specifications. Text and comments can also be included. The editor will also create symbols of the cells so that they can be used in other parts of the constructions.

4.8 Schematic Entry To make a library and assemble a schematic of an inverter. Underneath steps clarify the production of new library “myDesignLib” and we will utilize the same all through this course to build different cells that we going to make in the following labs. Execute Tools-library manager in the virtuoso window to open library manager.

4.8.1 Making a new library 1.

In the library manager, execute File  New  Library. The new library frame

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2.

In the “New Library” shape, sort “my Design Lib” in the name area.

3.

In the field of Directory area, confirm that the way to the library is set to

/Database/cadence_analog_labs_613 and click OK. Note: An innovation record isn’t required on the off chance that you are not intrigued to do the formats for the plan. 4. In the following “Innovation File for New library” frame, select choice Attach to a current tech file and snap OK.

Fig: 4.8.21 Technology file from window library

5. After enabling the attach existing option and clicking on ok there is a new window pops out, which is used for attach the tech library files such as gpdk180, gpdk90, gpdk45 etc. as shown below.

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Fig.4.8.2 Attach library to Technology Library

6. After clicking on ok there is a new library formed by the name given by user, which can be seen by user by view into library manager directory as shown in the screenshot, here you can also observe the attached tech library such as gpdk180, gpdk90, gpdk45 etc. is combined with the library which is created by the user.

Fig4.8.3 Library Manager Director

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4.9 Creating a schematic cell view: The main aspect of this creating a schematic cell view is that, here we will know how to open new window for schematic in the new library created by the user and implement an inverter schematic. 1.

Same as the library creation, here we need to go to File New cell view. Setup the

new document frame as takes after.

Fig.4.9 Creating Cell View

2.

Try not to alter the Library way document and the one above may be not quite the

same as the way appeared in your frame. 3.

Snap OK when done the above settings. A clear schematic window for the inverter

configuration shows up.

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4.10Adding components to schematic In the inverter schematic window, tap the instance settled menu symbol to show the include instance shape. Tip: You can likewise execute Create  Instance or press I. By doing this a window pops out which helps us choose the segments which are needed from the library program. Where you need to give Library Name, Cell Name, and the design values which can be used by the user schematic circuit diagram, given in the table on the following page as for the every segment that is needed. After you finish the Add Instance shape, move your cursor to the schematic window and snap left to put a part. This is a table of segments for building the inverter schematic.

Table: 4.10Transistor Values of Inverter

On the off chance that you put a segment with a wrong parameter esteems, utilize the Edit  Properties  Objects charge the parameters. Utilize the Edit Move order on the off chance that you put parts in the wrong area.

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You can pivot parts at the time you put them or utilize the Edit  Rotate charge after they are set. In the wake of entering segments, click cancel in the Add Instance shape or press Esc with your cursor in the schematic window.

4.11 Adding pins to schematic Tap the pin settled menu symbol in the schematic window. You can likewise execute make  pin or press p. The Add stick frame shows up. Sort the accompanying in the correct request leaving space between the sick names. Ensure that the bearing field is set to enter / yield / input-output while setting the information/yield/in-out sticks separately and the usage field is set to schematic. Select Cancel from the Add  stick shape in the wake of putting the pins. In the schematic window, execute Window  Fit or press the f bind key.

4.12Adding wires to a schematic Add wires to associate parts and sticks in the outline. 1.

Click the wire icon in the schematic window. You can also press the w key or

execute create  wire. 2.

In the schematic window, tap on a stick of one of your segments as the primary

point for your wiring. A precious stone shape shows up finished the beginning stage of this wire. 3.

Take after the prompts at the base of the plan window and snap left on the goal

point for your wire. A wire is directed between the source and goal focuses. 4.

Finish the wiring as appeared in figure and when done wiring press ESC enter in

the schematic window to scratch off wiring.

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5 SIMULATION The reproduction device is begun straightforwardly from the schematic proof reader and all the fundamental net records portraying the plan will be made. A reproduction is normally preformed in a test seat, which is likewise a schematic, with a genuine outline included as a case. The test seat additionally incorporates flag source and power supply. By using parameters for the properties of the parts utilized it is conceivable to rapidly breakdown the outline for an extensive variety of factors. The test systems keep running from inside Affirma Analog Circuit Design Environment which are an instrument that handles the interface between the client and the test system. The present form of Cadence utilized at the office (4.45) utilizes the AffirmaSpecter Circuit Simulator. The test system offers an extensive variety of investigations (DC, recurrence clear, transient, clamor, and so on.) and be introduced graphically and be spared. The outcomes (voltage levels, streams, clamor, and so forth.) can be bolstered into a mini-computer which can exhibit different parameter of the investigated circuit – postpone time, rise time, slew rate, stage edge, and numerous other fascinating properties. It is likewise conceivable to set up the logarithmic articulation of in or yield flag which can be pointed as an element of some other variable. In this segment, we will run the reenactment for Inverter and plot the transient , DC attributes and we will do Parametric Analysis after the underlying reenactment.

5.1

Starting The Simulation Environment



Begin the Simulation Environment to run a reproduction.



In the Inverter_ Test schematic window, execute Dispatch – ADE L



The Virtuoso Analog Design Environment (ADE) reproduction window shows up. ECE Department NNRGIES

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5.1.1 Choosing a Simulator Set the earth to utilize the Spectra apparatus, a fast, exceedingly exact simple test system. Utilized this test system with the Inverter _ Test outline, which is comprised of simple parts. 

In the reproduction window (ADE), execute



Setup- Simulator/Directory/Host.



In the Choosing Simulator form, set the Simulator filed to spectra and click OK.

5.1.2 Choosing Analysis This segment shows how to see and select the distinctive sorts of examinations to finish the circuit when running the reenactment . 1.

In the Simulation window (ADE), tap the Choose – Analyses symbol. You can

also execute Analyses Choose. The Choosing Analysis frame shows up. This is a dynamic frame, the base of the shape changes in light of the choice above. 2.

To setup for transient investigation.

a.

In the Analysis area select tran.

b.

Set the stop time as 200n.

c.

Snap at the direct or enabled catch at the base, and after that snap apply.

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Fig.5.1.2Choosing Trans Analysi

5.1.3 Setting Design Variables Set the estimation of any

outlines factors in the circuit before responding.

Something else, the reproduction won’t run. 1.

In

the Simulation window, tap the Edit Variable symbol. The Editing Design

variables form appears. 2.

Click Copy from at the bottom of the form. The design is scanned, and all variables

found in the design are listed, In a few moments, the wp variable appears in the Table of Design variables section. 3.

Set the value of the wp variable. With the wp variable highlighted in the Table of

Design variables click on the variable name wp and enter the following. Snap Change and notice the refresh in the Table Design Variables. 4.

Snap OK or Cancel in the Editing Design Variables Window.

5.1.4 Selecting Outputs for Plotting

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1.

Execute Outputs

To be plotted  Select on Schematic in the recreation

window. 2.

Take after the provoke at the base of the Schematic window, Click on yield net Vout, input net Vin of the Inverter, Press ESC with the cursor in the schematic subsequent to choosing it.

Fig.5.1.4 ADEL Window

5.2 Running the Simulation 1.

Execute Simulation – Netlist and Run in the simulation window to start the

Recreation or the symbol, this will make netlist and in addition run the reenactment. 2.

At the point when recreation completes, the Transient, DC plots naturally will be

flown up alongside log record.

5.2.1 Saving the Simulator state We can spare the test system state, which stores data, for example, demonstrate library document, yields, investigation, variable and so forth. This data reestablishes the reproduction condition without typing in all of setting once more. ECE Department NNRGIES

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1.

In the Simulation window, execute Session save state. The Saving State shape

shows up. 2.

Set the Save as field to state 1_ inv and ensure all alternative are chosen under what

to spare field. 3.

Snap OK in the paring state frame. The Simulator state is spared.

5.3 Loading the Simulator 1. From the ADE window execute Session–Load State. 2. In the Loading State window, set the State name to state1_inv as appeared. 3. Click Ok in the Loading State window.

5.4 Layout Tool The Virtuoso Layout Editor is used for drawing the layout. A layout consists of geometrical agues in different colours. From the size and colour of this figures it is later possible to generate the final mask layers which are used in the fabrication of the design. It is possible to include other cells by instantiating their layout views. To verify that the layout fulfills all electrical and geometric rules Design Rule Check (DRC) program is used. This manual will describe Assura Diva verification which can be called upon directly from the layout editor. This tool will mark any error in the design and can also extract (i.e. convert to a net list) the layout so it can be simulated.

5.5 Place and Route The final stage of the construction of a large design is called place and route. This is the process when all the different components of the chip is placed on its locations and connected to each other. Since a design can easily consist of thousands of connection points it would be tedious and time consuming to do the connections manually. The designer might also want to try various alternatives in placing the components, output buffers, memory structures, amplifiers, etc. The place and route tool that will be described later in this manual is named Envisia Silicon Ensemble. It is a very potent

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program that that can place and route a very large design while respecting some design constraints (restrictions on delay and size) at the same time. Usually Silicon Ensemble is used for Standard Cell designs - this is when all the cells are of the same height so they can be placed in contact (abutted) with each other - but it can handle other structures. Since not all designs that is to be routed are created in Cadence this manual will describe how to run Silicon Ensemble as a standalone tool. In some other design tools the function of a digital design is described in a functional language which is the compiled (synthesized) into a net list that can be fed into Silicon Ensemble.

5.6 Advantages Cadence tools provide digital and analog both verification where other tools like Synopsis provides digital verification only. Cadence is only tool in the world which is used for all IC’s Verification before Fabrication. Cadence tools have different tools for top end and back end verification like Assura, Composer, Affirma, Diva etc. Cadence tools are less expensive than other tools.

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6. RESULTS 1. Conventional full adder designed by using cadence

Fig 6.1 full adder by using cadence

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2. Conventional full adder output

Fig6.2 full adder output

3. Design of 4-bit ripple carry adder in cadence

Fig 6.3 design of 4- bit ripple carry adder

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4. 4-Bit Ripple Carry Adder Output When Cin =0

Fig 6.4 4- bit ripple carry adder when cin=0

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5. 4-Bit Ripple Carry Adder Output When Cin =1

Fig 6.5 4- Bit ripple carry adder when cin=1

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6. Optimized Transmission Gate Full Adder

Fig 6.6 Optimized Transmission Gate Full Adder 7. Proposed Full Adder Output

Fig 6.7 Proposed Full Adder Output

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8. Proposed Ripple Carry Adder

Fig 6.8 Proposed Ripple Carry Adder

9. Proposed Ripple Carry Adder

Fig 6.9 Proposed Ripple Carry Adder Circuit Diagram

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10.Proposed Ripple Carry Adder Output cin=0

Fig 6.10 Ripples Carry Adder Output cin=0

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11.Proposed Ripple Carry Adder Output cin=1

Fig 6.11 Proposed Ripple Carry Adder Output cin=1

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7. CONCLUSION AND FUTURE SCOPE 7.1 CONCLUSION In this paper two different ripple carry adders have been implemented, simulated, analyzed and compared. A novel full adder designed using 18 transmission gate is presented in this paper that targets low transistor count and area. The characteristics of the adder circuit are compared against conventional complementary CMOS full adder based on the transistor count and delay. The optimized layout is drawn for the proposed full adder cell and the ripple carry adder in Cadence tool using sea of gate arrays concept. Thus we have implemented a ripple carry adder which is optimized in terms of transistor count and area and is more efficient than the ripple carry adder using conventional complementary CMOS full adder. Power, delay and area are the constituent factors in VLSI design that limits the performance of any circuit. This work presents a simple approach to reduce the area, delay and power of CSLA architecture. The conventional carry select adder has the disadvantage of more power consumption and occupying more chip area. All the three models of CSLA are designed and are implemented in vhdl using Xilinx14.1ISE tool and there salts are compared in terms of delay and power. The CSLA with DLatch proves to be the High Speed and Low Power CSLA. It is

also implemented with

Spartan 6FPGA. 7.2 FUTURE SCOPE This work has been designed for 8-bit, 16-bit, 32-bit and 64-bitword size and results are evaluated for parameters like area, delay and power. This work can be further extended for high renumber of bits. New architectures can be designed in order to reduce the power, area and delay of the circuits. Steps maybe taken to optimize the other parameters like frequency, number of gate clocks, length etc.

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