Packages

PACKAGES

• Collection of definitions, datatypes, subprograms • Reference made by the design team • Any changes are known to the team immediately • same data types ("downto vs. to") • extended functions for all

• A package is a collection of definitions of data types, subprograms, constants etc. This is especially useful in teamwork situations where everyone should work with the same data types, e.g. the same orientation of a vector range. This simplifies the connection of the modules of different designers to the complete VHDL model later on. Necessary changes are also circularized immediately to all persons concerned.

• t is possible to split a package into a header and a body section. The package header contains prototype declarations of functions or procedures, the definition of all required data types and so on. • The actual implementation of the subprograms can be placed in the body section. • This simplifies the compilation process, because only the usually rather short package header must be read in order to decide whether the current VHDL code conforms to the previous declarations/definition

• A package is referenced by a use clause. After the keyword ' use ' follows the so called "selected name". • This name consists of the library name where the compiled package has been placed, the package name itself and the object name which will be referenced. • Usually, the keyword ' all ' is used to reference all visible objects of the package.

Library • All analysed objects - packages, package bodies, entities, architectures and configurations can be found in a library. In VHDL, the library is a logical name with which compiled objects can be grouped and referenced. The default library is called "work". This logical name can be mapped to another logical library name as shown in the picture, but it has to be mapped to a physical path on a storing device eventually.

• Usually, every designer operates within his own work library. Yet he can use units from other libraries which might hold data from former projects (PROJEKT_1 and PROJEKT_XY) or the current project packages (USERPACK). If another library than WORK is to be used, it will have to be made visible to the VHDL compiler. • This is done with the library statement that starts with the keyword ' library ', followed by the logical name of the library. For example the library IEEE is commonly used because it contains standardized packages.

• Once a library has been declared ,all the functions ,procedures, type declarations of a package in this library can be made accessible to a VHDL model through the use clause. • Library IEEE; Use IEEE.std_logic-1164.all • These are called ‘context clause; • The second statement makes everything defined in the package to be visible to the VHDL model

• If we write use iee.std_logic_1164.my_func; only this specific function is visible. See the contents of the std_logic_1164 package in Appendix We can make any number of packages and place them in different libraries and then make them visible

• Package package-name is --packege –item declarations --subprogram declarations --type declarations --subtype declarations --constant declarations --signal declarations --variable declarations --file declarations --component declarations --attribute declarations --attribute specifications --use clauses End package-name;

• • • • • • • • •

Package body package name is --package-body-item declarations. .i.e. --subprogram bodies --complete constant declarations --subprogram declarations --type and subtype declarations --file and alias declarations --use clauses End package name ;

Example of a package Package p is End p; Package body p

End p;