Memory Org Unit Vi

UNIT VI Memory Organization

Characteristics • • • • • • • •

Location Capacity Unit of transfer Access method Performance Physical type Physical characteristics Organisation

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Location • CPU • Internal • External

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Capacity • Word size – The natural unit of organisation

• Number of words – or Bytes

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Unit of Transfer • Internal – Usually governed by data bus width

• External – Usually a block which is much larger than a word

• Addressable unit – Smallest location which can be uniquely addressed – Word internally 7/25/2009

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Access Methods (1) • Sequential – Start at the beginning and read through in order – Access time depends on location of data and previous location – e.g. tape

• Direct – Individual blocks have unique address – Access is by jumping to vicinity plus sequential search – Access time depends on location and previous location 7/25/2009 Ruikar Sachin , SAE – e.g. disk

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Access Methods (2) • Random – Individual addresses identify locations exactly – Access time is independent of location or previous access – e.g. RAM

• Associative – Data is located by a comparison with contents of a portion of the store – Access time is independent of location or previous access – e.g. cache 7/25/2009 Ruikar Sachin , SAE

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Performance • Access time – Time between presenting the address and getting the valid data

• Memory Cycle time – Time may be required for the memory to “recover” before next access – Cycle time is access + recovery

• Transfer Rate – Rate at which data can be moved 7/25/2009

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Memory Hierarchy • Registers – In CPU

• Internal or Main memory – May include one or more levels of cache – “RAM”

• External memory – Backing store

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Memory Hierarchy

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Typical memory Parameters

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Physical Types • Semiconductor – RAM

• Magnetic – Disk & Tape

• Optical – CD & DVD

• Others – Bubble – Hologram 7/25/2009

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Physical Characteristics • • • •

Decay Volatility Erasable Power consumption

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Organisation • Physical arrangement of bits into words • Not always obvious • e.g. interleaved

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Internal Memory

Location • Primary(Internal): - RAM, ROM, PROM , EPROM, EEPROM • Secondary(External): - Hard disk, Floppy disk, magnetic tape, CDROM, Thumb drive(pendrive)

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Semiconductor Memory Types

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Semiconductor Memory • RAM – Misnamed as all semiconductor memory is random access – Read/Write – Volatile – Temporary storage – Static or dynamic

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Memory Cell Operation

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Binary Storage cell made up of SRLatch

In truth table the inputs S and R stand for Set and Reset. To set a bit means to make it TRUE. To reset a bit means to make it FALSE. The outputs, Q and , are normally complementary. When R is asserted, Q is reset to 0 and does the opposite. When S is asserted, Q is set to 1 and does the opposite. When neither input is asserted, Q remembers its old value, Qprev. Asserting both S and R simultaneously doesn’t make much sense because it means the latch should be set and reset at the same time, which is impossible. The poor confused circuit responds by making both outputs 0. 7/25/2009

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1 bit Binary Cell (BC)

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Types of RAM • SRAM: Static Random Access Memory. DRAM: Dynamic Random Access Memory.

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Dynamic RAM • • • • • • • • • •

Bits stored as charge in capacitors Charges leak Need refreshing even when powered Simpler construction Smaller per bit Less expensive Need refresh circuits Slower Main memory Essentially analogue – Level of charge determines value

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Dynamic RAM Structure

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DRAM Operation • •

•

Address line active when bit read or written – Transistor switch closed (current flows) Write – Voltage to bit line • High for 1 low for 0 – Then signal address line • Transfers charge to capacitor Read – Address line selected • transistor turns on – Charge from capacitor fed via bit line to sense amplifier • Compares with reference value to determine 0 or 1 – Capacitor charge must be restored

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Static RAM • • • • • • • • • •

Bits stored as on/off switches No charges to leak No refreshing needed when powered More complex construction Larger per bit More expensive Does not need refresh circuits Faster Cache Digital – Uses flip-flops

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Stating RAM Structure

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Static RAM Operation • Transistor arrangement gives stable logic state • State 1 – C1 high, C2 low – T1 T4 off, T2 T3 on • State 0 – C2 high, C1 low – T2 T3 off, T1 T4 on • Address line transistors T5 T6 is switch • Write – apply value to B & compliment to B • Read – value is on line B 7/25/2009

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SRAM v DRAM • Both volatile – Power needed to preserve data • Dynamic cell – Simpler to build, smaller – More dense – Less expensive – Needs refresh – Larger memory units • Static – Faster – Cache 7/25/2009 Ruikar Sachin , SAE

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Read Only Memory (ROM) • Permanent storage – Nonvolatile

• • • •

Microprogramming Library subroutines Systems programs (BIOS) Function tables

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Types of ROM • Written during manufacture – Very expensive for small runs • Programmable (once) – PROM – Needs special equipment to program • Read “mostly” – Erasable Programmable (EPROM) • Erased by UV – Electrically Erasable (EEPROM) • Takes much longer to write than read – Flash memory • Erase whole memory electrically 7/25/2009

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Read Only Memories (ROM) » “Permanent” data storage » ROMs - Data is “wired in” during fabrication at a chip manufacturer’s plant Purchased in lots of 10k or more » PROMs - Programmable ROM - Data can be written once by the user employing a PROM programmer - Useful for small production runs » EPROM - Erasable PROM - Programming is similar to a PROM - Can be erased by exposing to UV light

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Read Only Memories (ROM) » EEPROMS - Electrically erasable PROMs - Can be written to many times while remaining in a system - Does not have to be erased first - Program individual bytes - Writes require several hundred usec per byte - Used in systems for development, personalization, and other tasks requiring unique information to be stored » Flash Memory - Similar to EEPROM in using electrical erase - Fast erasures, block erasures - Higher density than EEPROM

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ROM The disadvantage of a diode cell is that it does not isolate the bit line from the word line. For better isolation the diode can be replaced by gate-source connection of a NMOS transistor. Moreover, in order to achieve the programmability i.e. for multiple read write capability a modified transistor known as Floating Gate (FG) Transistor is employed. The structure is similar to a traditional MOS device, except that an extra gate is inserted between gate and channel. The threshold voltage of the FG is programmable and corresponding to its different values the level 0 and level 1 can be identified.

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ROM

In the NAND structure, a series of floating gate transistors are connected between the bit line and ground line. This organization allows the elimination of all contacts to ground line and thus reducing the area by 40% compared to NOR architecture. It has faster erase and write times, higher density, and lower cost per bit than NOR flash. This can be obtained by arranging 8 to 16 floating gate transistors connected in series as shown in the Fig. (b). However, its I/O interface allows only sequential to data. This makes it suitable for mass-storage devices such as PC cards and various memory stick cards 7/25/2009

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Here every cell is connected in NOR fashioned manner as shown in Fig. (a). Note that the transistors used are FG type and two gates can be seen in their symbols. Every source terminal of the transistor is connected to ground in NOR architecture. Metal lines are required between each individual cell to run the ground in NOR architectures and therefore they occupy more area. NOR-based flash has long erase and write times, but has a full address/data (memory) interface that allows random access to any location. This makes it suitable for storage of program code that needs to be infrequently updated, such as computers' BIOS.

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Usual Organization

1024 by 4-bit SRAM

Read Cycle and Write Cycle Timing for static RAM

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4096 by 1-bit DRAM

Read Cycle and Write Cycle Timing for Dynamic RAM

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Organisation in detail • A 16Mbit chip can be organised as 1M of 16 bit words • A bit per chip system has 16 lots of 1Mbit chip with bit 1 of each word in chip 1 and so on • A 16Mbit chip can be organised as a 2048 x 2048 x 4bit array – Reduces number of address pins • Multiplex row address and column address • 11 pins to address (211=2048) • Adding one more pin doubles range of values (capacity) 7/25/2009

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Refreshing • • • • • •

Refresh circuit included on chip Disable chip Count through rows Read & Write back Takes time Slows down apparent performance

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Typical 16 Mb DRAM (4M x 4)

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Organization of 1k x 1 Memory chip

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Organization of a 1M x 1 Memory chip.

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Packaging

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Advanced DRAM Organization • Basic DRAM same since first RAM chips • Enhanced DRAM – Contains small SRAM as well – SRAM holds last line read

• Cache DRAM – Larger SRAM component – Use as cache or serial buffer

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Synchronous DRAM (SDRAM)

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Synchronous DRAM (SDRAM) • • • •

Access is synchronized with an external clock Address is presented to RAM RAM finds data (CPU waits in conventional DRAM) Since SDRAM moves data in time with system clock, CPU knows when data will be ready • CPU does not have to wait, it can do something else • Burst mode allows SDRAM to set up stream of data and fire it out in block • DDR-SDRAM sends data twice per clock cycle (leading & trailing edge) 7/25/2009

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SDRAM

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SDRAM Read Timing

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RAMBUS • • • • •

Adopted by Intel for Pentium & Itanium Main competitor to SDRAM Vertical package – all pins on one side Data exchange over 28 wires < cm long Bus addresses up to 320 RDRAM chips at 1.6Gbps • Asynchronous block protocol – 480ns access time – Then 1.6 Gbps 7/25/2009

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RAMBUS Diagram

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DDR SDRAM • SDRAM can only send data once per clock • Double-data-rate SDRAM can send data twice per clock cycle – Rising edge and falling edge

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Cache DRAM(CDRAM) • Mitsubishi • Integrates small SRAM cache (16 kb) onto generic DRAM chip • Used as true cache – 64-bit lines – Effective for ordinary random access • To support serial access of block of data – E.g. refresh bit-mapped screen • CDRAM can prefetch data from DRAM into SRAM buffer • Subsequent accesses solely to SRAM 7/25/2009

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Design of a Simple Memory Controller Memory Subsystem Data Path

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schematic representation for the data path

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sequencer circuit diagram

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Memory Controller

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Cache • Small amount of fast memory • Sits between normal main memory and CPU • May be located on CPU chip or module

Locality of Reference • The effectiveness of the cache mechanism is based on a property of computer programs called locality of reference. • Example: loops • Two types 1)Temporal 2) Spatial • Temporal : A recently executed instruction is likely to be executed again very soon. • Spatial: The instruction which close proximity to a recently executed instruction are also likely to be executed. 7/25/2009

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Cache/Main Memory Structure

Cache operation – overview • • • •

CPU requests contents of memory location Check cache for this data If present, get from cache (fast) If not present, read required block from main memory to cache • Then deliver from cache to CPU • Cache includes tags to identify which block of main memory is in each cache slot

Cache Design • • • • • •

Size Mapping Function Replacement Algorithm Write Policy Block Size Number of Caches

Size does matter • Cost – More cache is expensive

• Speed – More cache is faster (up to a point) – Checking cache for data takes time

Typical Cache Organization

Mapping Function • Direct Mapping • Associative mapping • Set associative mapping

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Direct Mapping • • • • • • • •

•

•

A particular block of main memory can be brought to a particular block of cache memory. So, it is not flexible. The main memory address is divided into three fields. The field size depends on the memory capacity and the block size of cache. In this example, Consider a cache of 4096 (4K) words with a block size of 32 words. Therefore, the cache is organized as 128 blocks. The lower 5 bits of address is used to identify a word within a block. Next 7 bits are used to select a block out of 128 blocks (which is the capacity of the cache). The remaining 4 bits are used as a TAG to identify the proper block of main memory that is mapped to cache. So the total 12 bits of address is divided for two groups, lower 5 bits are used to select a word within a block, and higher 7 bits of address are used to select any block of cache memory. Let us consider a main memory system consisting 64K words. The size of address bus is 16 bits. Since the block size of cache is 32 words, so the main memory is also organized as block size of 32 words Out of 16 address lines of main memory, lower 5 bits are used to select a word within a block and higher 11 bits are used to select a block out of 2048 blocks.

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Direct Mapping

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Associative mapping • •

•

•

•

•

In the associative mapping technique, a main memory block can potentially reside in any cache block position. In this case, the main memory address is divided into two groups, low-order bits identifies the location of a word within a block and high-order bits identifies the block. In the example here, 11 bits are required to identify a main memory block when it is resident in the cache , high-order 11 bits are used as TAG bits and low-order 5 bits are used to identify a word within a block. The TAG bits of an address received from the CPU must be compared to the TAG bits of each block of the cache to see if the desired block is present. In the associative mapping, any block of main memory can go to any block of cache, so it has got the complete flexibility and we have to use proper replacement policy to replace a block from cache if the currently accessed block of main memory is not present in cache. It might not be practical to use this complete flexibility of associative mapping technique due to searching overhead, because the TAG field of main memory address has to be compared with the TAG field of all the cache block.

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Associative mapping

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Set associative mapping • • • • • • •

Blocks of the cache are grouped into sets, and the mapping allows a block of main memory to reside in any block of a specific set. Therefore, the flexibility of associative mapping is reduced from full freedom to a set of specific blocks. This also reduces the searching overhead, because the search is restricted to number of sets, instead of number of blocks. Organize the cache with 4 blocks in each set. The TAG field of associative mapping technique is divided into two groups, one is termed as SET bit and the second one is termed as TAG bit. Each set contains 4 blocks, total number of set is 32. The main memory address is grouped into three parts: low-order 5 bits are used to identifies a word within a block. Since there are total 32 sets present, next 5 bits are used to identify the set. High-order 6 bits are used as TAG bits.

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Set associative mapping

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Replacement Algorithms (1) Direct mapping • No choice • Each block only maps to one line • Replace that line

Replacement Algorithms (2) Associative & Set Associative • Hardware implemented algorithm (speed) • Least Recently used (LRU) • First in first out (FIFO) – replace block that has been in cache longest

• Least frequently used – replace block which has had fewest hits

• Random

Write Policy • Must not overwrite a cache block unless main memory is up to date • Multiple CPUs may have individual caches • I/O may address main memory directly

CACHE PERFORMANCE

Fig Cache read and write policies.

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Write through • All writes go to main memory as well as cache • Multiple CPUs can monitor main memory traffic to keep local (to CPU) cache up to date • Lots of traffic • Slows down writes

Write back • Updates initially made in cache only • Update bit for cache slot is set when update occurs • If block is to be replaced, write to main memory only if update bit is set • Other caches get out of sync • I/O must access main memory through cache

Cache performance • HIT RATIOS AND EFFECTIVE ACCESS TIMES

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Memory Management

Fig: Partition of main memory.

Fig: Five State process model

Fig: Partition of Main Memory

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Partitioning 1. Fixed size partitions 2. Variable size partitions

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Dynamic partitioning

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Virtual Memory • Paging – The memory is partitioned into equal fixed size chunks that are relatively small. This chunk of memory is known as frames or page frames. – Each process is also divided into small fixed chunks of same size. The chunks of a program is known as pages.

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Allocation of free frames

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Translation of Logical Address to Physical Address

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Virtual Memory Organization

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Virtual Address Translation Method

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Inverted Page table structure

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Use of an associative mapped TLB

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Address Translation proceeds as follows: • • • • • • • •

Given a virtual address, the MMU looks in the TLB for the reference page. If the page table entry for this page is found in the TLB, the physical address is obtained immediately. If there is a miss in the TLB, then the required entry is obtained from the page table in the main memory and the TLB is updated. When a program generates an access request to a page that is not in the main memory, a page fault is said to have occurred. The whole page must be brought from the disk into the memory before access can proceed. When it detects a page fault, the MMU asks the operating system to intervene by raising an exception.(interrupt). Processing of active task is interrupted, and control is transferred to the operating system. The operating system then copies the requested page from the disk into the main memory and returns control to the interrupted task. Because a long delay occurs due to a page transfer takes place, the operating system may suspend execution of the task that caused the page fault and begin execution of another task whose page are in the main memory.

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Interleaving Memory

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Memory interleaving • The lower order K bits of the memory address selects module • The high order m bits name the location within the module • Thus, any component of the system that generates request for access to consecutive memory location can keep several modules busy at one time. • Therefore, faster access to a block of data & higher average utilization of the memory system. • To implement the interleave structure, there must be 2k module, otherwise there will be gaps of nonexistent location in the memory. 7/25/2009

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External Memory

Types of External Memory • Magnetic Disk – RAID – Removable

• Optical – CD-ROM – CD-Recordable (CD-R) – CD-R/W – DVD

•7/25/2009 Magnetic Tape

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Magnetic Disk • Disk substrate coated with magnetizable material (iron oxide…rust) • Substrate used to be aluminium • Now glass – Improved surface uniformity • Increases reliability – Reduction in surface defects • Reduced read/write errors – Better stiffness – Better shock/damage resistance 7/25/2009

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Read and Write Mechanisms • • • •

Recording & retrieval via conductive coil called a head May be single read/write head or separate ones During read/write, head is stationary, platter rotates Write – Current through coil produces magnetic field – Pulses sent to head – Magnetic pattern recorded on surface below • Read (traditional) – Magnetic field moving relative to coil produces current – Coil is the same for read and write • Read (contemporary) – Separate read head, close to write head – Partially shielded magneto resistive (MR) sensor – Electrical resistance depends on direction of magnetic field – High frequency operation speed 7/25/2009 • Higher storage density Ruikarand Sachin , SAE

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Inductive Write MR Read

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Data Organization and Formatting • Concentric rings or tracks – Gaps between tracks – Reduce gap to increase capacity – Same number of bits per track (variable packing density) – Constant angular velocity

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Disk Data Layout

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Disk Velocity • • •

•

Bit near centre of rotating disk passes fixed point slower than bit on outside of disk Increase spacing between bits in different tracks Rotate disk at constant angular velocity (CAV) – Gives pie shaped sectors and concentric tracks – Individual tracks and sectors addressable – Move head to given track and wait for given sector – Waste of space on outer tracks • Lower data density Can use zones to increase capacity – Each zone has fixed bits per track – More complex circuitry

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Disk Layout Methods Diagram

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Finding Sectors • Must be able to identify start of track and sector • Format disk – Additional information not available to user – Marks tracks and sectors

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Winchester Disk Format Seagate ST506

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Characteristics • • • • •

Fixed (rare) or movable head Removable or fixed Single or double (usually) sided Single or multiple platter Head mechanism – Contact (Floppy) – Fixed gap – Flying (Winchester)

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Fixed/Movable Head Disk • Fixed head – One read write head per track – Heads mounted on fixed ridged arm

• Movable head – One read write head per side – Mounted on a movable arm

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Removable or Not • Removable disk – Can be removed from drive and replaced with another disk – Provides unlimited storage capacity – Easy data transfer between systems

• Nonremovable disk – Permanently mounted in the drive

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Multiple Platter • One head per side • Heads are joined and aligned • Aligned tracks on each platter form cylinders • Data is striped by cylinder – reduces head movement – Increases speed (transfer rate)

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Multiple Platters

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Tracks and Cylinders

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Floppy Disk • 8”, 5.25”, 3.5” • Small capacity – Up to 1.44Mbyte (2.88M never popular)

• • • •

Slow Universal Cheap Obsolete?

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Winchester Hard Disk (1) • • • •

Developed by IBM in Winchester (USA) Sealed unit One or more platters (disks) Heads fly on boundary layer of air as disk spins • Very small head to disk gap • Getting more robust 7/25/2009

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Winchester Hard Disk (2) • • • •

Universal Cheap Fastest external storage Getting larger all the time – 250 Gigabyte now easily available

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Speed • Seek time – Moving head to correct track

• (Rotational) latency – Waiting for data to rotate under head

• Access time = Seek + Latency • Transfer rate

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Timing of Disk I/O Transfer

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RAID • • • • •

Redundant Array of Independent Disks Redundant Array of Inexpensive Disks 6 levels in common use Not a hierarchy Set of physical disks viewed as single logical drive by O/S • Data distributed across physical drives • Can use redundant capacity to store parity information 7/25/2009

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RAID 0 • • • •

No redundancy Data striped across all disks Round Robin striping Increase speed – Multiple data requests probably not on same disk – Disks seek in parallel – A set of data is likely to be striped across multiple disks

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RAID 1 • • • • • •

Mirrored Disks Data is striped across disks 2 copies of each stripe on separate disks Read from either Write to both Recovery is simple – Swap faulty disk & re-mirror – No down time

• Expensive 7/25/2009

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RAID 2 • Disks are synchronized • Very small stripes – Often single byte/word • Error correction calculated across corresponding bits on disks • Multiple parity disks store Hamming code error correction in corresponding positions • Lots of redundancy – Expensive – Not used 7/25/2009

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RAID 3 • Similar to RAID 2 • Only one redundant disk, no matter how large the array • Simple parity bit for each set of corresponding bits • Data on failed drive can be reconstructed from surviving data and parity info • Very high transfer rates 7/25/2009

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RAID 4 • • • •

Each disk operates independently Good for high I/O request rate Large stripes Bit by bit parity calculated across stripes on each disk • Parity stored on parity disk

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RAID 5 • • • • •

Like RAID 4 Parity striped across all disks Round robin allocation for parity stripe Avoids RAID 4 bottleneck at parity disk Commonly used in network servers

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RAID 6 • Two parity calculations • Stored in separate blocks on different disks • User requirement of N disks needs N+2 • High data availability – Three disks need to fail for data loss – Significant write penalty

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RAID 0, 1, 2

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RAID 3 & 4

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RAID 5 & 6

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Data Mapping For RAID 0

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Optical Storage CD-ROM • Originally for audio • 650Mbytes giving over 70 minutes audio • Polycarbonate coated with highly reflective coat, usually aluminium • Data stored as pits • Read by reflecting laser • Constant packing density • Constant linear velocity 7/25/2009

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CD Operation

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CD-ROM Drive Speeds • Audio is single speed – Constant linier velocity – 1.2 ms-1 – Track (spiral) is 5.27km long – Gives 4391 seconds = 73.2 minutes

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CD-ROM Format

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Random Access on CD-ROM • • • • •

Difficult Move head to rough position Set correct speed Read address Adjust to required location

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CD-ROM for & against • • • •

Large capacity Easy to mass produce Removable Robust

• Expensive for small runs • Slow • Read only 7/25/2009

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Other Optical Storage • CD-Recordable (CD-R) – WORM – Now affordable – Compatible with CD-ROM drives • CD-RW – Erasable – Getting cheaper – Mostly CD-ROM drive compatible – Phase change • Material has two different reflectivities in different phase states 7/25/2009

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DVD - what’s in a name? • Digital Video Disk – Used to indicate a player for movies • Only plays video disks

• Digital Versatile Disk – Used to indicate a computer drive • Will read computer disks and play video disks

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DVD - technology • Multi-layer • Very high capacity (4.7G per layer) • Full length movie on single disk – Using MPEG compression

• • • •

Finally standardized Movies carry regional coding Players only play correct region films Can be “fixed”

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DVD – Writable • Loads of trouble with standards • First generation DVD drives may not read first generation DVD-W disks • First generation DVD drives may not read CD-RW disks • Wait for it to settle down before buying!

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CD and DVD

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Magnetic Tape • • • •

Serial access Slow Very cheap Backup and archive

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Questions ?

Applications • •

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RAM ROM – Code converter – Arithmetic look up table – Random logic – Waveform generator – Master scan character generator – Microprogramming A B C D E

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Example cache performance We record the events as the program executes as shown in Figure 7-18. Since the memory is initially empty, the first instruction that executes causes a miss. A miss thus occurs at location 48, which causes main memory block #3 to be read into cache slot #3. This first memory access takes 2500 ns to complete. Load-through is used for this example, and so the word that causes the miss at location 48 is passed directly to the CPU while the rest of the block is loaded into the cache slot. The next event consists of 15 hits for locations 49 through 63. The events that follow are recorded in a similar manner, and the result is a total of 213 hits and five misses. The total number of accesses is 213 + 5 = 218. The hit ratio and effective access time are computed as shown below:

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