Input Output Org Unit 5

Chapter 5 Input/Output Organization

Contents: Accessing I/O devices, Interrupts, Direct memory access, Buses, Interface circuits

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Input/Output Problems • Wide variety of peripherals – Delivering different amounts of data – At different speeds – In different formats

• All slower than CPU and RAM • Need I/O modules

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Input/Output Module • Interface to CPU and Memory • Interface to one or more peripherals

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Processor

Memory

Bus

I/O device 1

I/O device n

Figure: A single-bus structure. 7/25/2009

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Generic Model of I/O Module

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External Devices • Human readable – Screen, printer, keyboard

• Machine readable – Monitoring and control

• Communication – Modem – Network Interface Card (NIC)

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External Device Block Diagram

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I/O Module Function • • • • •

Control & Timing CPU Communication Device Communication Data Buffering Error Detection

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I/O Steps • • • • •

CPU checks I/O module device status I/O module returns status If ready, CPU requests data transfer I/O module gets data from device I/O module transfers data to CPU

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I/O Module Diagram

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Address lines Bus

Data lines Control lines

Address decoder

Control circuits

Data and status registers

I/O interface

Input device

Figure I/O interface for an input device. 7/25/2009

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I/O Module Decisions • Hide or reveal device properties to CPU • Support multiple or single device • Control device functions or leave for CPU

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Input Output Techniques • Programmed • Interrupt driven • Direct Memory Access (DMA)

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Three Techniques for Input of a Block of Data

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Programmed I/O • CPU has direct control over I/O – Sensing status – Read/write commands – Transferring data

• CPU waits for I/O module to complete operation • Wastes CPU time 7/25/2009

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Programmed I/O - detail • • • • • • •

CPU requests I/O operation I/O module performs operation I/O module sets status bits CPU checks status bits periodically I/O module does not inform CPU directly I/O module does not interrupt CPU CPU may wait or come back later

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I/O Commands • CPU issues address – Identifies module (& device if >1 per module)

• CPU issues command – Control - telling module what to do • e.g. spin up disk

– Test - check status • e.g. power? Error?

– Read/Write • Module transfers data via buffer from/to device 7/25/2009

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Addressing I/O Devices • Under programmed I/O data transfer is very like memory access (CPU viewpoint) • Each device given unique identifier • CPU commands contain identifier (address)

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I/O Mapping • Memory mapped I/O – Devices and memory share an address space – I/O looks just like memory read/write – No special commands for I/O • Large selection of memory access commands available

• Isolated I/O – Separate address spaces – Need I/O or memory select lines – Special commands for I/O • Limited set 7/25/2009

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Memory-mapped I/O • Input and output buffers use same address space as memory locations • All instructions can access the buffers – Move DATAIN, R0 keyboard buffer – Move R0, DATAOUT

Read from Send to display buffer

– DATAIN, DATAOUT: addresses of keyboard and display buffers 7/25/2009 Ruikar Sachin, SAE 20

Isolated I/O • Separate address space for I/O devices • Special instructions (e.g., IN, OUT) that indicate that the address is not in memory address space • Intel processors can use either 7/25/2009

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Using the “Address Space” • Move R0, DATAOUT

• OUT R0, DATAOUT 7/25/2009

If memory-mapped, then DATAOUT (say address 123) refers to the display buffer, same address as a memory location

If isolated then DATAOUT (say address 123) refers to the display buffer, and memory location 123 is not used for this

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DATAIN

DATAOUT

STATUS

DIRQ

KIRQ SOUT

CONTROL

DEN

KEN

3

2

7

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6

5

4

SIN

1

Figure Registers in keyboard and display interfaces Ruikar Sachin, SAE

0

23

Move

#LINE, R0

Initialize memory pointer

WAITK

TestBit Branch=0 Move

#0, STATUS WAITK DATAIN, R1

Test SIN Wait for character to be entered Read the character

WAITD

TestBit Branch=0 Move Move

#1, STATUS WAITD R1, DATAOUT R1, (R0)+

Test SOUT Wait for the display to become ready Send the character to the display Store the character and advance the pointer

Compare Branch=0 Move Call

#$0D, R1 WAITK #$0A, DATAOUT PROCESS

Check if the character is CR If not, get another character Otherwise, send Line Feed Call a subroutine to process the input line

Figure : A program that reads one line from the keyboard stores it in memory buffer, and echoes it back to the display. 7/25/2009

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Interrupts • Interrupt-request line – Interrupt-request signal – Interrupt-acknowledge signal

• Interrupt-service routine – Similar to subroutine – May have no relationship to program being executed at time of interrupt • Program info must be saved • Interrupt latency

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Program 1

Program 2

COMPUTE routine

PRINT routine

1 2 Interrupt occurs here

i i +1

M

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Figure

Transfer of control through the use of interrupts. Ruikar Sachin, SAE

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Handling Interrupts • Many situations where the processor should ignore interrupt requests – Interrupt-disable – Interrupt-enable

• Typical scenario – Device raises interrupt request – Processor interrupts program being executed – Processor disables interrupts and acknowledges interrupt – Interrupt-service routine executed – Interrupts enabled Ruikar and Sachin, program execution resumed 7/25/2009 SAE

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Vdd

Processor R I NTR INTR INTR1

INTR2

INTR n

Figure : An equivalent circuit for an open-drain bus used to implement a common interrupt-request line. 7/25/2009

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I NTR

because it is active when in the low voltage state Vdd

Processor R

pull-up resistor

I NTR INTR INTR1

INTR2

INTR n

inverter (NOT gate) INTR signal is low when interrupt line is high 7/25/2009

line voltage is high (=Vdd) when inactive

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I NTR

because it is active when in the low voltage state Vdd

Processor R I NTR INTR INTR1

INTR2

INTR n

inverter INTR signal is high when interrupt line is low 7/25/2009

line voltage is low (0) when active

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device n interrupts by closing switch, bringing line voltage down to 0 30

Vdd

Processor R I NTR INTR INTR1

INTR2

INTR n

Figure : An equivalent circuit for an open-drain bus used to implement a common interrupt-request line. 7/25/2009

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Handling Multiple Devices • How can the processor recognize the device requesting an interrupt? • How can the processor obtain the starting address of the appropriate interrupt-service routine? • Should a device be allowed to interrupt the processor while another interrupt is being serviced? • How should two or more simultaneous interrupt requests be handled? 7/25/2009

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Interrupt Priority • Multi-level priority organization • During execution of interrupt-service routine – Disable interrupts from devices at the same level priority or lower – Continue to accept interrupt requests from higher priority devices – Privileged instructions executed in supervisor mode

• Controlling device requests – Interrupt-enable • KEN, DEN 7/25/2009

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Processor

INTR1 Device 1

I NTRp Device 2

INTA1

Device p INTA p

Priority arbitration circuit

Figure

Implementation of interrupt priority using individual interrupt-request and acknowledge lines.

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Processor

INTR1 Device 1

I NTRp Device 2

Device p

INTA1

INTAp

Priority arbitration circuit

Figure

Implementation of interrupt priority using individual interrupt-request and acknowledge lines.

Priority determined by the order in which processor accepts and acknowledges interrupts 7/25/2009

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Polled interrupts: Priority determined by the order in which processor polls the devices (polls their status registers)

Processor

Vectored interrupts: Priority determined by the order in which processor tells device to put its code on the address lines (order of connection in the chain)

I N T R

INTA

Device 1

Device 2

Device

n

(a) Daisy chain

Figure : Interrupt priority schemes. Daisy chaining of INTA: If device has not requested service, passes the INTA signal to next device If needs service, does not pass the INTA, puts its code on the address lines 7/25/2009

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Processor

IN TR 1

INTA1

Device

Device

Device

Device

IN T R p

INTA

p

Priority arbitration circuit

(b) Arrangement of priority groups

Figure : Interrupt priority schemes.

Priority determined by the order in which processor accepts and acknowledges interrupts from a particular group 7/25/2009

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Multiple Interrupts • Priority in Processor Status Word – Status Register -- active program – Status Word -- inactive program

• Changed only by privileged instruction • Mode changes -- automatic or by privileged instruction • Interrupt enable/disable, by device, system-wide 7/25/2009

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Main Program Move #LINE, PNTR Clear EOL BitSet #2, CONTROL BitSet #9, PS … continue to process Interrupt Service Routine READ MoveMultiple R0-R1, -(SP) Move PNTR, R0 MoveByte DATAIN, R1 MoveByte R1, (R0)+ Move R0, PNTR CompareByte #$0D, R1 Branch NZ RTRN Move #1, EOL BitClear #2, CONTROL RTRN MoveMultiple (SP)+, R0-R1 Return 7/25/2009

Initialize buffer pointer Clear end-of-line indicator Enable keyboard interrupts Set interrupt-enable bit in the PS

Push registers R0,R1 onto stack Load memory address pointer Get input character Store it in memory Update memory pointer Check if Carriage Return Indicate end-of-line Disable keyboard interrupts Pop and restore registers Return from interrupt

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Main Program Move Clear BitSet BitSet

#LINE, PNTR EOL #2, CONTROL #9, PS

Variable: Periodically checked by program to determine when line has been read

0

EOL

Initialize buffer pointer Clear end-of-line indicator Enable keyboard interrupts Set interrupt-enable bit in the PS

IE PS

DIRQ

KIRQ

3

2

1 9

8

7

6

5

4

DEN CONTROL

0

KEN 1

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5

4

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2

1

0 40

Interrupt Service Routine READ MoveMultiple Move MoveByte MoveByte Move CompareByte Branch NZ Move BitClear RTRN MoveMultiple Return

R0-R1, -(SP) PNTR, R0 DATAIN, R1 R1, (R0)+ R0, PNTR #$0D, R1 RTRN #1, EOL #2, CONTROL (SP)+, R0-R1

Push registers R0,R1 onto stack Load memory address pointer Get input character Store it in memory Update memory pointer Check if Carriage Return Indicate end-of-line Disable keyboard interrupts Pop and restore registers Return from interrupt

Invoked each time the keyboard puts a character in DATAIN and causes an interrupt Continues until CR character encountered, then keyboard interrupts are disabled until another line is requested 7/25/2009

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Interrupt Vectoring Memory Location Address of ISR

Interrupt Service Routine

Code Address Bus

Device

Interrupt Control Bus

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Common Functions of Interrupts

• Interrupt transfers control to the interrupt service routine, generally through the interrupt vector table, which contains the addresses of all the service routines. • Interrupt architecture must save the address of the interrupted instruction and the contents of the processor status register. • Incoming interrupts are disabled while another interrupt is being processed to prevent a lost interrupt. • A software-generated interrupt may be caused either by an error or a user request (sometimes called a trap). • An operating system is interrupt driven.

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Interrupts Hardware interrupts—from I/O devices, memory, processor, etc. Software interrupts—generated by a program. Interrupts signal attention requests and error conditions. Interrupts may be intrinsic or user-defined. Other terms: Trap Fault Exception System call IRQ 7/25/2009

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Interrupt Handling Interrupt Code

Memory Location

0

…00

Interrupt Vector Table Address of Timer ISR software interrupt

31

…31

Address of Disk Read ISR

32

…32

Address of Disk Read Complete ISR hardware interrupt

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87

…87

137

…137

Address of Print ISR

Address of Invalid Instruction ISR Ruikar Sachin, SAE

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Interrupt Handling • The operating system preserves the state of the CPU by storing registers and the program counter. • Determines which type of interrupt has occurred: – vectored interrupt system

• Separate segments of code determine what action should be taken for each type of interrupt 7/25/2009

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Direct Memory Access (DMA) •

•

Polling or interrupt driven I/O incurs considerable overhead – Multiple program instructions – Saving program state – Incrementing memory addresses – Keeping track of word count Transfer large amounts of data at high speed without continuous intervention by the processor

•

Special control circuit required in the I/O device interface, called a DMA controller

•

DMA controller keeps track of memory locations, transfers directly to memory (via the bus) independent of the processor

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DMA Controller • •

•

Part of the I/O device interface – DMA Channels Performs functions that would normally be carried out by the processor – Provides memory address – Bus signals that control transfer – Keeps track of number of transfers Under control of the processor

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Direct Memory Access (DMA) • OS responds to a program’s system call for Disk Read, for example • OS puts the program in the “blocked” or “waiting” or “asleep” state • Initiates the Disk Read • Starts execution of another program • When Read is completed, DMA controller sends an interrupt 7/25/2009

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31

30

1

0

Status and control

IRQ

Done

IE

R/ W

Starting address

Word count

Figure. 7/25/2009

Registers in a DMA interf ace. Ruikar Sachin, SAE

50

31 Status and control

30

1

0

1

1

0

IRQ

Done

IE

R/ W

42000

Starting address

1200

Word count

Figure 7/25/2009

Registers in a DMA interf ace. Ruikar Sachin, SAE

incremented each time a word is transferred 51

Main memory

Processor

System bus

Disk/DMA controller

Disk

Figure 7/25/2009

Disk

DMA controller

Printer

K eyboard

Network Interface

Use of DMA controllers in a computer system. Ruikar Sachin, SAE

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DMA • Processor and DMA controller(s) must “interweave” memory accesses • DMA controllers have higher priority for obvious reason, i.e., higher speed devices need higher priority

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DMA • If DMA gets a cycle at a time, then – CPU gets a memory cycle (uses bus) – CPU gets a memory cycle (uses bus) – CPU gets a memory cycle (uses bus) – CPU gets a memory cycle (uses bus) – DMA gets a memory cycle (uses bus) – CPU gets a memory cycle (uses bus) – CPU gets a memory cycle (uses bus) – CPU gets a memory cycle (uses bus)

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processor gets most cycles “cycle stealing”

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DMA • Or – – – – – –

CPU gets a memory cycle (uses bus) CPU gets a memory cycle (uses bus) DMA gets a memory cycle (uses bus) DMA gets a memory cycle (uses bus) DMA gets a memory cycle (uses bus) DMA gets a memory cycle (uses bus) . . . – DMA gets a memory cycle (uses bus) – CPU gets a memory cycle (uses bus) 7/25/2009

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“burst mode” to transfer a block of data without interruption

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Compare

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DMA Controller

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DMA Controller

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DMA Controller

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DMA Controller

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DMA Controller

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DMA Controller

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DMA Controller

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DMA Controller

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Sharing the Bus • Bus master: the device currently allowed to transfer data on the bus (CPU or DMA) • Bus arbitration: choosing the next bus master • Bus busy: BBSY set by current bus master to show that the line is in use • Bus request: BR set when device wants to become bus master – When it gets BG (bus granted), waits for BBSY to become inactive, then assumes mastership of the bus and sets BBSY 7/25/2009

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Bus Arbitration • Determination of the order in which requests for the bus are serviced – Fixed priority--each device has a priority rating – Rotating priority--devices are assigned a rotating priority value – Central arbitration--arbiter circuit determines – Distributed arbitration--all devices share in the determination

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Centralized arbitration B BSY BR Processor

BG1

Figure .

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DMA controller 1

BG2

DMA controller 2

A simple arrangement for bus arbitration using a daisy chain.

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Centralized arbitration DMA device 2 makes bus request ( BR)

Time

BR BG1

BG2

B BSY Bus master

Figure

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Processor

DMA controller 2

Processor

Sequence of signals during transfer of bus mastership for the Ruikar Sachin, SAE 68 devices

Centralized arbitration

Time

BR

BG1

BG2

B BSY Bus master

Processor

DMA controller 2

Processor

Processor responds with Bus Granted ( BG), signal daisy-chained through device 1 Figure Sequence of signals during transfer of bus mastership for the 7/25/2009 Ruikar Sachin, SAE 69 devices

Centralized arbitration

Time

BR

BG1

BG2

B BSY Bus master

Processor

DMA controller 2

Processor

Processor releases bus, sets BBSY Figure :Sequence of signals during transfer of bus mastership for the devices

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Centralized arbitration DMA device 2 removes bus request ( BR)

Time

BR

BG1

BG2

B BSY Bus master

Processor

Figure

DMA controller 2

Processor

Sequence of signals during transfer us of bmastership for the devices

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Centralized arbitration DMA device 2 assumes bus mastership sets BBSY BR

Time

Processor turns off BG signals

BG1

BG2

B BSY Bus master

Processor

Figure.

DMA controller 2

Processor

Sequence of signals during transfer of bus mastership for the devices

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Centralized arbitration DMA device 2 completes transfer, releases bus mastership

Time

BR

BG1

BG2

B BSY Bus master

Processor

DMA controller 2

Processor

Processor resumes bus mastership Figure. 7/25/2009

Sequence of signals during transfer us of bmastership Ruikar Sachin, SAE

for the de vices.

73

Distributed arbitration open collector ARB lines

Vcc

ARB3 ARB2 ARB1 ARB0 Start-Arbitration

O.C.

puts its ID on the ARB lines

“sees” this value on the ARB lines 0

1

0

1

0

1

1

1

Interface circuit for device A 7/25/2009

Figure :

A distributed arbitration scheme. Ruikar Sachin, SAE

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• A transmits 0101 • B transmits 0110 • Both “see”

its ID “

OR’ed by theARB lines

0111

• Where device sees difference (between itself and ARB lines, it changes all its bits from there “down” to zero • Thus, A changes to 0100, lines change to 0110, and B wins • More reliable--doesn’t depend on any one device • Highest number (device ID) = highest priority 7/25/2009

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Synchronous Bus • All devices clocked by a common clock line • Signals sent or data transferred at equally spaced intervals • Bus clock is not necessarily the same as the internal CPU clock (bus clock is slower, of course) 7/25/2009 Ruikar Sachin, SAE

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Time

some lines high, some low depending on bit pattern

Bus clock

Address and command

indeterminate value Data

t0

t1

t2

Bus cycle

Figure:

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Timing of an input transfer on a synchronous bus. Ruikar Sachin, SAE

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master puts address on bus, sends read signal at t0

Time

Bus clock

Address and command

Data

t0

t1

t2

Bus cycle

device (slave) puts data on bus at time t1

master strobes data into input buffer at time t2

Figure Timing of an input transfer on a synchronous bus. 7/25/2009

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time t1 - t0 must be longer than the maximum propagation delay between devices

Time

Bus clock

Address and command

Data

t0

t1

t2

Bus cycle

time t2 - t1 must be longer than the maximum propagation delay and setup time for the buffer

Clock cycle 7/25/2009

must be long enough to accommodate the slowest device79 Ruikar Sachin, SAE

T ime Bus clock

Seen by master

t

AM

Address and command

Data t

Seen by slave

DM

t AS

Address and command

Data t DS t0

t1

t2

propagation delays

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Figure : A detailed timing diagram for the input transfer Ruikar Sachin, SAE of Figure last slide

80

Time 1

2

3

4

Clock

Address

Command

Data

Slave-ready

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Figure : An input transfer using multiple clock cycles Ruikar Sachin, SAE

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Asynchronous Bus • Use of “handshake” rather than fixed clock cycles • Timing control lines – Master ready – Slave ready • Master puts information on the bus, signals “ready” • Selected slave performs the requested operation, then signals “ready” • Master removes signals and data

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Time Address and command

Master-ready

Slave-ready

Data

t0

t1

t2

t3

t4

t5

Bus cycle t3: master receives slave ready signal, waits (skew, setup) then takes Ruikar Sachin, SAE 83 the data and lowers the master ready

t2: slave device puts data on the data bus, signals slave ready

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Time Address and command

Master-ready

Slave-ready

Data

t0

t1

t2

t3

t4

t5

Bus cycle t5: device receives master ready “off” and removes data and slave Ruikar Sachin, SAE 84 ready signal from the bus

t4: master removes address and read signal

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Time Address and command

Data

Master-ready

Slave-ready

t0

t1

t2

t3

t4

t5

Bus cycle

Figure : Handshake control of data transfer during an output operation. 7/25/2009

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Interface Data Address

DATAIN

Data Encoder

Processor

R/W

SIN

Master -ready Valid

and

Keyboard

debouncing

switches

circuit

Input Slave- ready

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interface

Figure : Keyboard to processor connection. Ruikar Sachin, SAE

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Interface connects the device to the bus

bus

interface

device

“port”

Ports: parallel: serial: 7/25/2009

8 or 16 bits at a time from device 1 bit at a time from device but parallel to the bus Ruikar Sachin, SAE

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Interface • Provides storage for at least one word (or byte) of data • Contains status flags accessible by processor buffer full--for input device buffer empty--for output device • Contains address decoder • Generates timing signals for bus control protocol • Performs any required format conversion--e.g., serial to parallel 7/25/2009

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Figure 7/25/2009

Circuit

: Input Interface

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89

determines whether, what, and when the device will be “read from”

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Figure : Input Interface Circuit

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Address decoder determines whether this device is being addressed

Address lines of system bus

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Figure : Input Interface Ruikar Sachin, SAE Circuit

A0 is used to determine whether status or data is to be read 91

Figure: A two input to four output decoder 7/25/2009

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Device number 2 address decoder 2 input, 1 output Figure: A two input to four output decoder

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31 address lines of system bus carry device id

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31 input, 1 output decoder

Figure : Input Interface Ruikar Sachin, SAE Circuit

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A Read from the device will occur only when all four conditions are met

0 for read status, 1 for read data

Figure : Input Interface Circuit

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Master ready

Figure: Input interface circuit 7/25/2009

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tri-state buffers 96

e= 0

x

f

x

e f

e= 1 x

(a) Symbol

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f

(b) Equivalent circuit

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Sends “Slave-ready” if either Read is detected

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Puts SIN on the D0 data line if Read Status is detected

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Keyboard sends “valid” after data is ready in the buffer DATAIN

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D flip-flop

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Figure: Circuit for the Status Flag Ruikar Sachin, SAE

100

R

S

RS latch: R

S

SIN

1

0

0

0

1

1

Read data tries to set SIN to 0, can’t while Master Ready (being read) 7/25/2009

D flip-flop

Valid sets D flip-flop to 1, changes latch, sets SIN to 1, but only if Master Ready is 0

Sachin, SAE Figure: Circuit forRuikar the Status Flag

101

Sends “Slave-ready” if either Read is detected 7/25/2009

Puts SIN on the D0 data line Puts data on the data lines if Read data is detected if Read status is detected Ruikar Sachin, SAE

102

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Data Address Processor CPU

R-W

DATAOUT

Data

SOUT

Valid

Output interface

Idle

Master-ready Slave-ready

Printer

Figure: Printer to processor connection. 7/25/2009

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Bus D7

PA7 DATAIN

D1 D0

PA0 SIN

Input status

CA PB7 DATAOUT PB0

SOUT

Slave Ready Master Ready

Address Decoder

1

R/ W A31 A2 A1 A0

CB1 CB2

My-address

Handshake Control for output status

RS1 RS0

Figure: Combined input/output interface circuit. 7/25/2009

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Fig: Serial Interface

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Main memory

Processor

Processor bus Bridge PCI bus Ethernet interface

SCSI controller

Additional memory

USB controller

ISA interface

SCSI bus

IDE disk

Video Disk controller Disk 1

Disk 2

CDROM controller CDROM

Keyboard

Game

Figure : An example of a computer system using different interface standards. 7/25/2009

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• Bridge:

Connects buses with different characteristics Items on PCI bus appear as though on the system bus • PCI: Peripheral component interconnect— processor independent • SCSI: Small Computer System Interface—SCSI controller uses DMA approach • • • •

USB: ISA: EISA: IDE:

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Universal Serial Bus Industry Standard Architecture 32 bit version of ISA Integrated Device Electronics

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Host

PCI bridge

Main memory

PCI bus

Disk

Printer

Ethernet interface

Figure Use of a PCI bus in a computer system. 7/25/2009

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Introduction Buses • System buses • Internal – – – –

PCI AGP PCMCIA, … Focus of this chapter

• External – USB – FireWire, … – Discussed in Chapter 19 7/25/2009

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Introduction Buses • System bus consists of – Address bus – Data bus – Control bus

• Buses can be – Dedicated – Multiplexed – Synchronous – Asynchronous 7/25/2009

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Introduction Buses • Control bus – Memory read and Memory write – I/O read and I/O write – Ready – Bus request and Bus grant – Interrupt and Interrupt acknowledgement – DMA request and DMA acknowledgement – Clock – Reset 7/25/2009

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Buses Design Issue •

Need to consider several design issues – Bus width • Data and address buses – Bus type • Dedicated or multiplexed – Bus operations • Read, write, block transfer, interrupt, … – Bus arbitration • Centralized or distributed – Bus timing • Synchronous or asynchronous

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Bus Operations • Basic operations – Read and write • Block transfer operations – Read or write several contiguous memory locations • Example: cache line fill • Read-modify-write operation – Useful for critical sections • Interrupt operation • Several other types… 7/25/2009

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Bus Arbitration • Centralized arbitration • A central arbiter receives all bus requests • Uses an allocation policy to determine which request should be granted • This decision is conveyed through the bus grant lines • Distributed arbitration • Arbitration hardware is distributed among the masters • A distributed arbitration algorithm is used to determine who should get the bus

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Synchronous Bus Memory read operation with no wait states

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Synchronous Bus Memory write operation with no wait states

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Synchronous Bus Memory read operation with a wait state

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Synchronous Bus Memory write operation with a wait state

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Synchronous Bus Block transfer of data

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Bus Summary

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Buses – ISA • Supports older text-based applications – PCI • Supports modern window-based systems – AGP • Supports high-performance graphics and fullmotion video – PCI-X • Improved and faster PCI

– PCMCIA(Personal Computer Memory Card International Association) • Useful for laptops 7/25/2009

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Thank you for your endurance!

☺ 7/25/2009

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