Madhur Mehta

MADHUR MEHTA th

718, SW 16 Ave, Apt # 215 Gainesville, FL–32601

Email: [email protected] Phone #: 678-523-5213

_____________________________________________________________________________________________ Objective To secure an Internship for Fall’08 or Fulltime Position in the field of Circuit Design and Test.

Education • Master of Science, Electrical and Computer Engineering, Expected Dec 2008 GPA: 3.67/4 University of Florida, Gainesville Coursework: Bipolar Analog IC Design, MOS Analog IC Design, VLSI, Advanced VLSI, RF Circuits and Systems, Large Signal RF Integrated Circuits, DSP • Bachelor of Technology, Electronics & Communication Engineering, May 2007 GPA: 8.09/10 Jamia Millia Islamia, Central University, New Delhi, India

Computer Skills • Programming Languages: C, C++, PERL • Hardware Description Languages: Verilog HDL, VHDL • EDA Tools: Cadence Virtuoso and Spectre, SPICE, MATLAB, Agilent ADS, Xilinx ISE, SIMetrix

Academic Projects • Design and Full Custom Layout of 4-bit, 2-stage pipelined, Subthreshold MIPS Processor for Ultra Low Power Applications in 0.25um CMOS technology with power reduction achieved through the use of Sleepy SRAM. Design of Radix-4 Booth Multiplier for use in the processor to increase speed. • A novel Resistor-less Bandgap Voltage and Current Reference Circuit using Operational Transconductance Amplifiers in 0.25um CMOS Technology. • Design of a 5th Order Chebyshev Low-Pass Gm-C Filter with 1dB pass-band ripple and a cut-off frequency of 10 MHz. • Design of a 2-stage Current Mirror Op-amp in 0.25um CMOS technology and analysis of the effects of compensation, feedback, slewing, single-pole linear settling, extended settling time due to under-damping, and double-pole settling. • Design of a Double Balanced Mixer in 0.35um CMOS Technology with an input frequency range of 1.7-1.9 GHz, IIP3>10dBm, Noise Figure <15dB and Conversion Gain >10dB. • Design of a 1 GHz LC-VCO using cross-coupled transistors in 0.35um CMOS Technology, including the design of Spiral Inductor and Varactor for use in the VCO. • Design and Layout of a 1pF accumulation mode MOS varactor in 0.35um CMOS technology, including the creation of a sub-circuit model in Spectre. • Performance Evaluation of a Dual-Supply 4-bit Carry Propagate Adder in terms of layout area, power, delay and EDP. • Design and Layout of a 128-bit SRAM and a sleepy stack SRAM, and relative performance evaluation in terms of area, power and delay. • Design of a 1Gbps Wireless data link system at 60 GHz, with a Bit Error Rate better than 1E-6 using Agilent ADS. • Design and Implementation of a Vending Machine Controller using behavioral modeling in VHDL, including generation of schematic and layout, using synthesis and place and route.

Experience Internship in VLSI, Jamia Electronics Consortium, India, May-July ’06. • Learnt about the fundamentals of VLSI Design and HDL. • Implementation of a Traffic Light Controller in VHDL including synthesis, place and route, generation of schematic, layout, DRC and LVS. Internship in Basics of Telecommunication, Himachal Futuristic Communications Limited, India, May-July ’05. • Learnt about Broadband DSL, Ethernet, CSMA/CD, GSM and CDMA. Presented seminars on the same.