Lecture7 Arithmetic

In this lecture: Lecture 7: Signed Numbers & Arithmetic Circuits

• • • • • • • • • •

Dr Pete Sedcole Department of E&E Engineering Imperial College London http://cas.ee.ic.ac.uk/~nps/ (Floyd 2.5 – 2.7, 6.1 – 6.2, 6.4 – 6.6) (Tocci 6.1 – 6.5, 6.10 – 6.11, 9.1 – 9.2, 9.4)

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7.1

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Representation of signed numbers Two’s complement Sign extension Addition of signed numbers Multiplication by -1 Multiplication and division by integer powers of 2 Adder and subtractor circuits Comparators Decoder Encoders

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Review of binary representation • •

octal:

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1011 B

0011 3

10 2

110 6

011 3 7.3

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Binary coded decimal revision

We have already seen (in lecture 2) how to represent numbers in binary Review example: (179)10 = (10110011)2 = (B3)16 = (263)8 hex:

7.2

•

In BCD, each digit of a decimal number is coded using 4-bit binary

•

The 4-bit binary words are then joined

•

Example: (987)10

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9

1001

8

1000

7

0111

So 987 in decimal becomes 1001 1000 0111 in BCD

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Summary Decimal 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Binary 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000

HEX 0 1 2 3 4 5 6 7 8 9 A B C D E F 10

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BCD 0000 0000 0000 0001 0000 0010 0000 0011 0000 0100 0000 0101 0000 0110 0000 0111 0000 1000 0000 1001 0001 0000 0001 0001 0001 0010 0001 0011 0001 0100 0001 0101 0001 0110

The basics of signed numbers Octal 0 1 2 3 4 5 6 7 10 11 12 13 14 15 16 17 20

7.5

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• •

sign = 0 → +ve sign = 1 → -ve

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•

•

+27

= 0001 1011 1110 0100 = 1110 0101

-27

• • • this is called one’s complement

Taking the two’s complement again give the original number: -27 = 1110 0101 Invert all bits 0001 1010 Add 1 0001 1011 = +27

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7.7

6

sign

0 magnitude

+27 = 00011011 -27 = 10011011

Problems: – need to handle sign and magnitude separately – two values for zero (e.g., 00000000, 10000000) – not convenient for arithmetic 7.6

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Using 2’s complement for signed numbers

Solution 2 is to represent negative numbers by taking the magnitude, inverting all bits, and adding one. This is called two’s complement Positive number Invert all bits Add 1

7

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Two’s complement •

So far, the numbers are assumed to be positive – There is no sign (+ or -) in the representations, so these numbers are called unsigned How can we represent signed numbers? Solution 1: Sign-magnitude – use one bit to represent the sign, and the remaining bits to represent the magnitude

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Using 2’s complement we can represent positive and negative numbers We call this signed two’s complement form In order to do this, we change the meaning of the left-most bit (MSB) – The MSB has a negative weighting in 2’s complement form

Example for 8-bit numbers: 26

unsigned number

27 b7

20 b0

26

signed 2’s complement

-27 b7

20 b0

b7 is also known as the sign bit

x = −bn −1 2 n −1 + bn − 2 2 n − 2 + " + b1 21 + b0 20 E1.2 Digital Electronics 1

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Examples Binary

The following numbers are in signed two’s complement form: 0101, 1011, 0111, 1100 What are the decimal values? 2’s complement form -8 4 2 1 0 1 0 1 1 0 1 1 0 1 1 1 1 1 0 0

Decimal 5 -5 7 -4

Note that the range of 4-bit numbers is different for unsigned and 2’s complement: 4-bit unsigned 4-bit 2’s complement E1.2 Digital Electronics 1

0 … +15 -8 … +7 7.9

0111 0110 0101 0100 0011 0010 0001 0000 1111 1110 1101 1100 1011 1010 1001 1000

Decimal 2’s comp unsigned 7 7 6 6 5 5 4 4 3 3 2 2 1 1 0 0 -1 15 -2 14 -3 13 -4 12 -5 11 -6 10 -7 9 -8 8 6 November 2008

Why use two’s complement? •

The major advantage of using two’s complement form is that subtraction can be performed by addition using the 2’s complement of the subtrahend minuend Example: 27 – 17 using normal subtraction

+

27

0001 10112

–

17

0001 00012

10

0000 10102

27 – 17 using two’s complement addition

+

+27

0001 10112

+

-17

1110 11112

+10

0000 10102

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• • • •

7.11

6 November 2008

Sign extension

In digital electronics, we usually have a fixed number of digits in representing numbers – typically 8, 16, 32, 64 bits Sometimes this is true for decimal numbers in “real life” – e.g.: dates are often written with leading zeros: 05/01/2008 We need to be able to extend a number to one using more bits For unsigned numbers this is easy: just add zeros to the left-hand side For sign-magnitude numbers add zeros to the left-hand side of the magnitude (keep the sign bit at the front)

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If a 1 is carried over from the MSB, it is ignored

7.10

Sign extension •

subtrahend

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How can we convert an 8-bit 2’s complement form number to 16 bits? duplicate the sign bit -215 s s

s

s

s

s

s

s

-27 s

26

20

+27 s

26

20

This is called sign extension Examples of 4-bit to 8-bit conversion: +2 0010 → 00000010 -6 1010 → 11111010 E1.2 Digital Electronics 1

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Signed addition • •

•

Multiplication by -1

The same hardware can be used for addition of unsigned numbers and for two’s complement signed numbers Why? Consider 4-bit numbers: – To an adder circuit, a two’s complement negative number x looks like x + 16 (and 16 = 100002) – The result of x + y will be 16 more than it should be – But: if we ignore the carry out of the MSB, the result will be correct – providing it is in the range of -8 to +7. What if x + y is not within -8 to +7? – Sign-extend to n+1 bits – Use an n+1 bit adder

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• •

Taking the two’s complement of a number A gives –A So to find -1 x A – invert all the bits – add 1

•

There is one exception: – the maximum negative number – e.g.: -8 in a 4-bit system – because we cannot represent +8 in 4-bit two’s complement form

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Multiplication and division by 2N •

•

•

•

In decimal, multiplying a number by 10 is easy: – shift all the digits one place to the left – put a zero in the least-significant digit In binary, multiplication by 2N is also easy: – shift all bits to the left by N places – fill the LSBs with zeros Example:

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Binary

Decimal

0000 1101

13

0001 1010

26

0011 0100

52

0110 1000

104 7.15

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Shifting right by N bits divides the number by 2N: – The bit that “falls off the end” is the remainder – Sign-extension must be maintained for 2’s complement form Decimal: (486)10 divided by 10 gives 48 remainder 6 Unsigned: (110101)2 divided by 2 gives 011010 remainder 1 (53)10 (26)10 (110101)2 divided by 4 gives 001101 (53)10 (13)10 Signed 2’s complement: (110101)2 divided by 2 gives 111010 (-11)10 (-6)10 (110101)2 (-11)10

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divided by 4 gives 111101 (-3)10 7.16

remainder 01

remainder 1 remainder 01 6 November 2008

Binary adder circuits Summary of signed and unsigned numbers Unsigned

•

Revision of the binary addition process: A +B S

Signed (two’s complement)

MSB has a positive weighting e.g.: +8 in a 4-bit system

MSB has a negative weighting e.g.: -8 in a 4-bit system

The carry-out from the MSB of an nbit adder can be used as an extra bit to avoid overflow

To avoid overflow, must sign-extend to n+1 bits and use an n+1 bit adder

To increase the number of bits, add zeros on the left-hand side

To increase the number of bits, signextend by duplicating the MSB

Inverting all bits and adding 1 converts X to (2N - X)

Inverting all bits and adding 1 converts X to -X

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•

•

Truth table

Boolean equations

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Implementation (could also implement S with an XOR gate)

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C 0 0 0 1

S 0 1 1 0

Truth table

A

1 1 1

1 1 0

1 0 1

A = A3A2A1A0

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A 0 0 0 0 1 1 1 1

B 0 0 1 1 0 0 1 1

Cin 0 1 0 1 0 1 0 1

S 0 1 1 0 1 0 0 1

Cout 0 0 0 1 0 1 1 1

S = A.B.Ci + A.B.Ci + A.B.Ci + A.B.Ci = A ⊕ B ⊕ Ci

&

B

0 0 1

Carry

Full adder

S = AB + AB = A ⊕ B C = AB A

•

B 0 1 0 1

1

LSB column has 2 inputs and 2 outputs: B0 – inputs A0 – outputs S0 C1 Other columns have 3 inputs, 2 outputs: – inputs Ak Bk Ck – outputs Sk Ck+1 We use a “half adder” circuit for the LSB column We use a “full adder” circuit for all other columns

Half adder A 0 0 1 1

1

≥1

S

A

&

C

B

Boolean equations

Co = ABCi + A BCi + ABCi + ABCi = AB + ACi + BCi

&

B

= AB + Ci ( A + B ) 7.19

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Complete circuitry for a full adder FA implementation using only NAND gates A B

A

&

Ci A B

B A

&

Ci A B

&

&

&

C out

Ci

S

B

&

&

Ci

C i A

&

&

B Ci

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Full adder from half adders A 0 0 0 0 1 1 1 1

B 0 0 1 1 0 0 1 1

HA1S HA1C 0 0 0 0 1 0 1 0 1 0 1 0 0 1 0 1 A+B

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Cin 0 1 0 1 0 1 0 1

HA2S HA2C 0 0 1 0 1 0 0 1 1 0 0 1 0 0 1 0

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Full adder from half adders S 0 1 1 0 1 0 0 1

Cout 0 0 0 1 0 1 1 1

HA1S+Cin

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Parallel adder • • •

Uses 1 full adder per bit: n full adders for n-bit numbers The carry output signal from one stage propagates to the carry input of the next stage The full n-bit calculation takes a while: n times the delay of one stage

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A 4-bit parallel binary adder

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Parallel subtraction using a parallel adder • •

Subtraction can be achieved by adding the negative of the number – e.g.: 6 – 3 = 6 + (-3) In two’s complement, the negative is formed by inverting all the bits and then adding 1 – Note that adding 1 can be achieved by using the carry-in of the first stage

A – B:

An Bn

A1 B1

A0 B0

A

A

A

B Ci

B Ci

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Comparators 1-bit comparator The output is 1 when the inputs are equal

1

B Ci

2-bit comparator Co

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∑

Sn

Co

7.27

∑

S1

Co

∑

The output is 1 when A0 = B0 and A1 = B1

S0 6 November 2008

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4-bit comparator

• •

Decoders

Detects one of three conditions Only one output will be HIGH at any one time: – A greater than B (A > B) – A equal to B (A = B) – A less than B (A < B)

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•

A decoder detects the presence of a specific combination of bits

•

In this example, X will only be HIGH if: A0 = 1 A1 = 0 A2 = 0 A3 = 1

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4-bit decoder truth table

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4-bit decoder

• • • •

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Binary input ‘Decimal’ outputs Outputs are active low Only one output is active at a time

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BCD-to-decimal decoder

BCD-to-7 segment display decoder

• •

•

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LCD or LED displays often show digits made up of 7 segments or lines Use a decoder to translate 4-bit BCD numbers into 7 control signals (one for each segment) This is called a BCD/7SEG decoder

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BCD/7SEG decoder truth table

a f

b

g e

c d

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BCD/7SEG

a

a

f

b

g e

f

e

c d

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b

g c d

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Decimal-to-BCD encoder

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