Lecture10 State Diagrams

In this lecture: Lecture 10: State diagrams Dr Pete Sedcole Department of Electrical & Electronic Engineering Imperial College London http://cas.ee.ic.ac.uk/~nps/

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10.1

• Introduction to Moore and Mealy state diagrams • State tables

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State diagrams •

• •

10.3

10.2

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Moore state diagram of an S-R flip-flop

A state diagram is used for a synchronous circuit. It shows: – the circuit state – the possible transitions between states – the values of the circuit outputs There are two possible models – Moore and Mealy We will look at the Moore model first: – a circle is drawn for each state – the value of the state and the outputs are written inside each circle – arrows are drawn to show possible transitions between states – the arrows are labelled with the required input conditions for the transition to occur

E1.2 Digital Electronics 1

E1.2 Digital Electronics 1

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Transition from state a to state b when inputs SR = 10

Q

S CLK

Inputs: SR Outputs: Q

R

SR SR+SR

a/0

b/1 SR

State a: Output Q is 0 Transition from state b to state a when inputs SR = 01 E1.2 Digital Electronics 1

10.4

SR+SR

Transitions between states occur at the positive edge of the clock

State b: Output Q is 1

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Example: 2-bit Gray Code “counter” E

GCC D0 D1

E

State Tables

a/00 E

• • •

E

CLK

• b/01

d/10

E

A state table is a tabular form of the state diagram There is one row for each possible state It shows the next state that will be entered (on the next clock edge) for all possible combinations of inputs Example:

E SR

•

E

When enabled (E=1) cycles through the 2-bit Gray Code Pauses when disabled (E=0)

•

E

a/0

Present state b/1

c/11 SR+SR

SR

00 a b

a b

SR+SR

Next state inputs: SR 01 10 a b a b

11 X X

E E1.2 Digital Electronics 1

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Assigned state table (S-R flip-flop) • •

The assigned state table differs from the state table by showing the flip-flop outputs assigned to each state instead of the state label Example for SR flip-flop Present output Q 0 1

00 0 1

Next output Q+ inputs: SR 01 11 0 X 0 X

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Boolean expression from assigned state table • •

Ordering the state table inputs like a Karnaugh map enables it to be used directly as a K-map It is used to find the Boolean equations that describe the next state Q+ from the values of the present state Q and the inputs

10 1 1

Q\SR 0 1

00 0 1

01 0 0

11 X X

10 1 1

The input values here have been ordered just like a Karnaugh Map If the output of the circuit is 1, and the inputs are S=1, R=0: what will be the output of the circuit after the next +ve clock edge?

•

For the example of the SR flip-flop: – the next state Q+ is a function of Q, S, R

Answer: 1 E1.2 Digital Electronics 1

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JK flip-flop states

The Karnaugh Map for the S-R flip-flop Q\SR 0 1

00 0 1

01 0 0

11 X X

10 1 1

Q

S

R

Q

J

CLK

JK+JK 1/0

CLK

Q

Boolean expressions are found by grouping 1s as usual:

Q

K

2/1 JK+JK

JK+JK

JK+JK

Moore state diagram

Q + = S + QR Present output Q 0 1

Such equations are called characteristic equations

Next output Q+ inputs: JK 01 11 0 1 0 0

00 0 1

10 1 1

Assigned state table E1.2 Digital Electronics 1

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10.10

JK characteristic equation

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D flip-flop D

Q

D

Q + = JQ + K Q

D

1/0

2/1

D

CLK Q D

then Q+ = Q + Q = 1 then Q+ =0 then Q+ = Q (= toggle)

• • •

when J=1, K=0 when J=0, K=1 when J=1, K=1

•

The characteristic equation clearly and simply describes the circuit operation Note that JK flip-flops are usually built from master-slave latches and not D flip-flops

•

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10.11

Symbol

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Present output Q 0 1

Moore state diagram

Next output Q+ 0 0 0

Q+ = D

1 1 1

Assigned state table

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Characteristic equation

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Mealy state diagrams •

•

Mealy state diagram of a JK flip-flop

Very similar to Moore state diagrams: – circles for states, arrows for transitions – circles are labelled with states – arrows are labelled with conditions for transition to occur However: – the circuit outputs are labelled on the transitions – this means that the value of the outputs depend on the values of the inputs as well as the present circuit state

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Summary: latches, flip-flops • • •

A latch is level-sensitive: the outputs change in response to a change in the input voltage level A flip-flop is edge-sensitive: the output only changes in response to a clock edge (either negative or positive) Flip-flop characteristic equations: SR +

Q = S + QR • • •

JK +

Q = JQ + K Q

D +

Q =D

SR flip-flops are not generally used because of the invalid input combination SR=11 Circuits implemented using JK flip-flops usually have fewer gates D flip-flops use less wiring as they only have one input

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inputs (JK)

Inputs: J K Outputs: Q

10/0, 11/0

Q

J

00/0 01/0

CLK K

output (Q)

a

Q

b 01/1, 11/1

Note that here the input values are shown in binary rather than Boolean expressions. This can be done for Moore state diagrams as well. E1.2 Digital Electronics 1

00/1 10/1

10.14

State label

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