Lecture9 Latches Flipflops
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In this lecture: Lecture 9: Latches & Flip-flops • Introduction to sequential circuits • Synchronous and asynchronous circuits • Overview of flip-flops and latches
Dr Pete Sedcole Department of Electrical & Electronic Engineering Imperial College London http://cas.ee.ic.ac.uk/~nps/ (Floyd 7.1 – 7.3) (Tocci 5.1 – 5.10)
E1.2 Digital Electronics 1
9.1
13 November 2008
E1.2 Digital Electronics 1
General digital system diagram
•
•
9.3
13 November 2008
Properties of sequential circuits •
E1.2 Digital Electronics 1
9.2
13 November 2008
In the last eight lectures we have covered combinational logic – the outputs of the circuit depend only on the current values of the input variables In this lecture we will look at sequential logic circuits – the outputs can depend on the present and past values of the inputs and the outputs At any moment in time, a sequential circuit exists in one of a number of predetermined states – it moves through a defined sequence of transitions from one state to the next – the output variables are used to describe the state of a sequential circuit, either directly or through derived state variables
E1.2 Digital Electronics 1
9.4
13 November 2008
Example
Synchronous and asynchronous •
•
• •
This binary counter counts the number of times a pulse occurs on input A The outputs C[7:0] depend on the past The state of the circuit in this case is the value of C[7:0]
E1.2 Digital Electronics 1
A C[7:0]
A C[7:0] 0
1
2
3
•
•
9.5
13 November 2008
Synchronous sequential logic: – the time at which transitions between circuit states occurs is controlled by a common clock signal – changes in all variables occur simultaneously Asynchronous sequential logic: – state transitions occur independently of any clock, and normally depend on the time at which input variables change – outputs do not necessarily change simultaneously Clock – a clock signal is a square wave of a fixed frequency – it is used to trigger state transitions at fixed times in synchronous circuits
E1.2 Digital Electronics 1
Flip-flops and latches •
•
• •
E1.2 Digital Electronics 1
13 November 2008
Flip-flops and latches
Flip-flops and latches are the fundamental elements of sequential circuits – bistable (two stable states) Flip-flops and latches are essentially 1-bit storage devices – outputs can be set to store either 1 or 0 depending on the inputs – even when the inputs are deasserted, the outputs retain their prescribed values Flip-flops and latches (normally) have 2 complementary outputs – usually denoted Q and Q Three main types: – R-S J-K
9.6
Q = 1 is the SET state inputs: data/control
FF or latch
Q
normal output
Q
inverted output
Q = 0 is the RESET state
latches and flip-flops are bistable circuits
D-type
9.7
13 November 2008
E1.2 Digital Electronics 1
9.8
13 November 2008
A S-R latch built from NAND gates 1
SET
0
SET
Q
S-R latch: SET operation 1
1
1
Q
1
0
0
1
SET
0
Q
1
RESET
RESET
1
Q
t0 t1
SET
0
t0 t1
Q
1
1
t0 t1
Q
t0 t1
0 Q RESET
Q RESET
1
1
1
1
0
This NAND gate latch has two possible stable states when SET = RESET = 1
0 t0 t1
t0 t1
A negative pulse on SET puts the latch in HIGH (SET) state
E1.2 Digital Electronics 1
9.9
13 November 2008
E1.2 Digital Electronics 1
S-R latch: RESET operation
SET
1
0
0 t0 t1
SET
Q
SET
1
t0 t1
Q
RESET Q RESET
0 t0 t1
1
RESET t0 t1
0
9.11
Q
R
Output
1
1
No change
0
1
Q=1
1
0
Q=0
0
0
Invalid
0
RESET
A negative pulse on RESET puts the latch in LOW (RESET) state
E1.2 Digital Electronics 1
R
S
SET
1
t0 t1
t0 t1
Q
Q
0
1
S
Q Q
1
13 November 2008
Set-Reset latch symbol and truth table
1
1
9.10
13 November 2008
Q
E1.2 Digital Electronics 1
9.12
13 November 2008
S-R latch to debounce a switch
A NOR gate S-R latch SET
Q
Q RESET
S
R
Q
Q
S
R
Output
0
0
No change
1
0
Q=1
0
1
Q=0
1
1
Invalid
SET RESET Q
E1.2 Digital Electronics 1
9.13
13 November 2008
E1.2 Digital Electronics 1
D latch (transparent latch)
E1.2 Digital Electronics 1
9.15
9.14
13 November 2008
D latch timing
13 November 2008
E1.2 Digital Electronics 1
9.16
13 November 2008
Clock signals and flip-flops
Set-Reset (S-R) flip-flop
“positive edge” or “positive-going transition” (PGT)
Synchronous digital systems: • the state bits of the circuit all 1 change simultaneously 0 • the changes occur at fixed points in time • the control signal which indicates it is time to change is called the clock Flip-flop symbols:
“negative edge” or “negative-going transition” (NGT)
Q
data and control inputs
E1.2 Digital Electronics 1
9.17
Q CLK is activated by a negative edge
13 November 2008
E1.2 Digital Electronics 1
SET
edge detector
CLK
E1.2 Digital Electronics 1
CLK
R
Q
CLK
Output
0
↑
No change
1
0
↑
Q=1
0
1
↑
Q=0
1
1
↑
Invalid
CLOCK S
9.18
13 November 2008
Q
CLK*
Q
R
Edge detector circuits for both positive-edge and negativeedge flip-flops
CLK
R
0
J-K flip-flop
S-R latch S
CLOCK
S
Q
Internal circuitry of a S-R flip-flop This is a simplified diagram of the inside of a S-R flip-flop
Q
S
R
CLK Q
CLK is activated by a positive edge
Flip-flops are sometimes called edge-triggered
Q
CLK
Clocked flip-flop: the output only changes at the positive edges of the clock
RESET X CLK*
CLK
X CLK*
CLK
CLK X
X
CLK*
CLK* 9.19
13 November 2008
E1.2 Digital Electronics 1
9.20
13 November 2008
Internal circuitry of a J-K flip-flop
E1.2 Digital Electronics 1
9.21
D flip-flop
13 November 2008
E1.2 Digital Electronics 1
D flip-flop from a J-K flip-flop
9.22
13 November 2008
Setup and hold times CLOCK DATA time tS
tH
The data/control inputs to the flip-flop must be stable:
DATA
For a time tS before the clock edge (the setup time)
CLOCK
For a time tH after the clock edge (the hold time)
D
Q
CLK Q
Applies to all types of flip-flop E1.2 Digital Electronics 1
9.23
13 November 2008
E1.2 Digital Electronics 1
9.24
13 November 2008
Asynchronous PRESET and CLEAR • • •
The S, R, J, K and D inputs are called synchronous inputs because their effects on the output are synchronised with the CLK edge Asynchronous inputs operate independently of the clock and other inputs (they are “override inputs”) Generally used to put the FF in SET or RESET state immediately
Application: a frequency divider • •
A frequency divider circuit takes a square-wave signal at a fixed frequency f and outputs a square-wave signal at a lower frequency Example: a “divide-by-2” frequency divider, produces an output
f 2
which is
D
CLOCK1
Q
CLOCK1
CLOCK2
CLK Q
E1.2 Digital Electronics 1
9.25
13 November 2008
Parallel data transfer using D FFs
E1.2 Digital Electronics 1
9.27
13 November 2008
E1.2 Digital Electronics 1
Q Q
9.26
13 November 2008
Dr Pete Sedcole Department of Electrical & Electronic Engineering Imperial College London http://cas.ee.ic.ac.uk/~nps/ (Floyd 7.1 – 7.3) (Tocci 5.1 – 5.10)
E1.2 Digital Electronics 1
9.1
13 November 2008
E1.2 Digital Electronics 1
General digital system diagram
•
•
9.3
13 November 2008
Properties of sequential circuits •
E1.2 Digital Electronics 1
9.2
13 November 2008
In the last eight lectures we have covered combinational logic – the outputs of the circuit depend only on the current values of the input variables In this lecture we will look at sequential logic circuits – the outputs can depend on the present and past values of the inputs and the outputs At any moment in time, a sequential circuit exists in one of a number of predetermined states – it moves through a defined sequence of transitions from one state to the next – the output variables are used to describe the state of a sequential circuit, either directly or through derived state variables
E1.2 Digital Electronics 1
9.4
13 November 2008
Example
Synchronous and asynchronous •
•
• •
This binary counter counts the number of times a pulse occurs on input A The outputs C[7:0] depend on the past The state of the circuit in this case is the value of C[7:0]
E1.2 Digital Electronics 1
A C[7:0]
A C[7:0] 0
1
2
3
•
•
9.5
13 November 2008
Synchronous sequential logic: – the time at which transitions between circuit states occurs is controlled by a common clock signal – changes in all variables occur simultaneously Asynchronous sequential logic: – state transitions occur independently of any clock, and normally depend on the time at which input variables change – outputs do not necessarily change simultaneously Clock – a clock signal is a square wave of a fixed frequency – it is used to trigger state transitions at fixed times in synchronous circuits
E1.2 Digital Electronics 1
Flip-flops and latches •
•
• •
E1.2 Digital Electronics 1
13 November 2008
Flip-flops and latches
Flip-flops and latches are the fundamental elements of sequential circuits – bistable (two stable states) Flip-flops and latches are essentially 1-bit storage devices – outputs can be set to store either 1 or 0 depending on the inputs – even when the inputs are deasserted, the outputs retain their prescribed values Flip-flops and latches (normally) have 2 complementary outputs – usually denoted Q and Q Three main types: – R-S J-K
9.6
Q = 1 is the SET state inputs: data/control
FF or latch
Q
normal output
Q
inverted output
Q = 0 is the RESET state
latches and flip-flops are bistable circuits
D-type
9.7
13 November 2008
E1.2 Digital Electronics 1
9.8
13 November 2008
A S-R latch built from NAND gates 1
SET
0
SET
Q
S-R latch: SET operation 1
1
1
Q
1
0
0
1
SET
0
Q
1
RESET
RESET
1
Q
t0 t1
SET
0
t0 t1
Q
1
1
t0 t1
Q
t0 t1
0 Q RESET
Q RESET
1
1
1
1
0
This NAND gate latch has two possible stable states when SET = RESET = 1
0 t0 t1
t0 t1
A negative pulse on SET puts the latch in HIGH (SET) state
E1.2 Digital Electronics 1
9.9
13 November 2008
E1.2 Digital Electronics 1
S-R latch: RESET operation
SET
1
0
0 t0 t1
SET
Q
SET
1
t0 t1
Q
RESET Q RESET
0 t0 t1
1
RESET t0 t1
0
9.11
Q
R
Output
1
1
No change
0
1
Q=1
1
0
Q=0
0
0
Invalid
0
RESET
A negative pulse on RESET puts the latch in LOW (RESET) state
E1.2 Digital Electronics 1
R
S
SET
1
t0 t1
t0 t1
Q
Q
0
1
S
Q Q
1
13 November 2008
Set-Reset latch symbol and truth table
1
1
9.10
13 November 2008
Q
E1.2 Digital Electronics 1
9.12
13 November 2008
S-R latch to debounce a switch
A NOR gate S-R latch SET
Q
Q RESET
S
R
Q
Q
S
R
Output
0
0
No change
1
0
Q=1
0
1
Q=0
1
1
Invalid
SET RESET Q
E1.2 Digital Electronics 1
9.13
13 November 2008
E1.2 Digital Electronics 1
D latch (transparent latch)
E1.2 Digital Electronics 1
9.15
9.14
13 November 2008
D latch timing
13 November 2008
E1.2 Digital Electronics 1
9.16
13 November 2008
Clock signals and flip-flops
Set-Reset (S-R) flip-flop
“positive edge” or “positive-going transition” (PGT)
Synchronous digital systems: • the state bits of the circuit all 1 change simultaneously 0 • the changes occur at fixed points in time • the control signal which indicates it is time to change is called the clock Flip-flop symbols:
“negative edge” or “negative-going transition” (NGT)
Q
data and control inputs
E1.2 Digital Electronics 1
9.17
Q CLK is activated by a negative edge
13 November 2008
E1.2 Digital Electronics 1
SET
edge detector
CLK
E1.2 Digital Electronics 1
CLK
R
Q
CLK
Output
0
↑
No change
1
0
↑
Q=1
0
1
↑
Q=0
1
1
↑
Invalid
CLOCK S
9.18
13 November 2008
Q
CLK*
Q
R
Edge detector circuits for both positive-edge and negativeedge flip-flops
CLK
R
0
J-K flip-flop
S-R latch S
CLOCK
S
Q
Internal circuitry of a S-R flip-flop This is a simplified diagram of the inside of a S-R flip-flop
Q
S
R
CLK Q
CLK is activated by a positive edge
Flip-flops are sometimes called edge-triggered
Q
CLK
Clocked flip-flop: the output only changes at the positive edges of the clock
RESET X CLK*
CLK
X CLK*
CLK
CLK X
X
CLK*
CLK* 9.19
13 November 2008
E1.2 Digital Electronics 1
9.20
13 November 2008
Internal circuitry of a J-K flip-flop
E1.2 Digital Electronics 1
9.21
D flip-flop
13 November 2008
E1.2 Digital Electronics 1
D flip-flop from a J-K flip-flop
9.22
13 November 2008
Setup and hold times CLOCK DATA time tS
tH
The data/control inputs to the flip-flop must be stable:
DATA
For a time tS before the clock edge (the setup time)
CLOCK
For a time tH after the clock edge (the hold time)
D
Q
CLK Q
Applies to all types of flip-flop E1.2 Digital Electronics 1
9.23
13 November 2008
E1.2 Digital Electronics 1
9.24
13 November 2008
Asynchronous PRESET and CLEAR • • •
The S, R, J, K and D inputs are called synchronous inputs because their effects on the output are synchronised with the CLK edge Asynchronous inputs operate independently of the clock and other inputs (they are “override inputs”) Generally used to put the FF in SET or RESET state immediately
Application: a frequency divider • •
A frequency divider circuit takes a square-wave signal at a fixed frequency f and outputs a square-wave signal at a lower frequency Example: a “divide-by-2” frequency divider, produces an output
f 2
which is
D
CLOCK1
Q
CLOCK1
CLOCK2
CLK Q
E1.2 Digital Electronics 1
9.25
13 November 2008
Parallel data transfer using D FFs
E1.2 Digital Electronics 1
9.27
13 November 2008
E1.2 Digital Electronics 1
Q Q
9.26
13 November 2008
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