Lecture12 Fsm
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In this lecture: Lecture 12: Finite State Machines Dr Pete Sedcole Department of Electrical & Electronic Engineering Imperial College London http://cas.ee.ic.ac.uk/~nps/
E1.2 Digital Electronics 1
• Finite State Machines (FSMs) • FSM design procedure
12.1
21 November 2008
E1.2 Digital Electronics 1
Design of a synchronous binary counter CLOCK
From the last lecture:
• • •
combinational circuit ?
C1
D2 D1 D0
1D
E1.2 Digital Electronics 1
12.3
Step 1: start with the transition table of the flip-flops to be used in the FSM Output transition required
How do we design the combinational circuit? This counter is an example of a Finite State Machine (FSM) The following procedure can be used for any FSM
21 November 2008
21 November 2008
FSM design procedure 1 •
A B C
12.2
D-type FF inputs
JK-type FF inputs
D
J
K
0 to 0
0
0
X
0 to 1
1
1
X
1 to 0
0
X
1
1 to 1
1
X
0
E1.2 Digital Electronics 1
12.4
D
CLK
Output
0
↑
0
1
↑
1
J
K
CLK
0
0
↑
Output Q
1
0
↑
Q=1
0
1
↑
Q=0
1
1
↑
Q 21 November 2008
FSM design procedure 2 •
FSM design procedure 3
Step 2: for each state variable in the state transition table, construct Karnaugh maps for each input in the flip-flop transition table Current state
Next state
A
B
C
A+
B+ C+
0
0
0
0
0
1
0
0
1
0
1
0
0
1
0
0
1
1
0
1
1
1
0
0
1
0
0
1
0
1
1
0
1
1
1
0
1
1
0
1
1
1
1
1
1
0
0
0
E1.2 Digital Electronics 1
For the 3-bit binary counter example, there are 3 state bits. If we use D flip-flops, there will be 3 “next-state” functions to implement.
For this example, we will use D flip-flops D2, D1, and D0 implement the next values of A, B, and C respectively
If we use JK flip-flops, we need Kmaps for both inputs of each flipflop, which would be 6 Boolean functions. 12.5
21 November 2008
D1
D0
E1.2 Digital Electronics 1
FSM design procedure 4 •
D2
A\BC 0 1
00 0 1
01 0 1
11 1 0
10 0 1
A\BC 0 1
00 0 0
01 1 1
11 0 0
10 1 1
A\BC 0 1
00 1 1
01 0 0
11 0 0
10 1 1
12.6
21 November 2008
FSM design procedure 5
Step 3: extract the Boolean expressions from the K-maps
•
A\BC 0 1
00 0 1
01 0 1
11 1 0
10 0 1
A\BC 0 1
00 0 0
01 1 1
11 0 0
10 1 1
D1 = B C + BC = B ⊕ C
A\BC 0 1
00 1 1
01 0 0
11 0 0
10 1 1
D0 = C
Step 4: implement using combinational logic
D 2 = A BC + AB + AC CLOCK
E1.2 Digital Electronics 1
12.7
C1
21 November 2008
D2 D1 D0
E1.2 Digital Electronics 1
12.8
1D
A B C
21 November 2008
Design of arbitrary code counters
Example •
•
It may be necessary to design counters that count sequences other than binary numbers
•
Examples: – counters which never reach their maximum value, such as a zero-to-nine counter (which uses 4 bits) – counters which follow a specific code, such as a Gray Code
•
The design procedure presented for binary counters can be extended to arbitrary code counters
E1.2 Digital Electronics 1
12.9
21 November 2008
Current state
Q2 Q1 Q0 Q2+ Q1+ Q0+
State transition table: • •
•
Next state
0
0
0
0
1
0
0
1
0
1
0
1
1 0 1 1 1 0 What about states 001, 011, 1 1 0 0 0 0 100, 111? These we call undefined states – what happens if the circuit gets into an undefined state, for example at power-up? Two approaches: 1. Use a reset signal to ensure the FSM enters the “zero” state at power-up, treat undefined states as “don’t care” 2. Design the FSM to explicitly enter the “zero” state from undefined states
E1.2 Digital Electronics 1
12.11
21 November 2008
Design a 3-bit counter to count the decimal sequence: 0, 2, 5, 6, 0, 2, 5, … Decimal Q2 Q1 Q0
Counting sequence:
State diagram:
000
0
0
0
0
2
0
1
0
5
1
0
1
6
1
1
0
010
E1.2 Digital Electronics 1
101
110
12.10
21 November 2008
Undefined states as “don’t care” Circuit diagram:
RESET CLOCK combinational circuit ?
E1.2 Digital Electronics 1
R C1
D0 D1 D2
12.12
1D
Q0 Q1 Q2
21 November 2008
Undefined states as “don’t care” Current state Q2 Q1 Q0
Next state Q2+
Q1+
Q0+
0
0
0
0
1
0
0
1
0
1
0
1
1
0
1
1
1
0
1
1
0
0
0
0
Undefined states to “zero” state
D2:
Q2\Q1Q0 0 1
00 0 X
01 X 1
11 X X
10 1 0
D1:
Q2\Q1Q0 0 1
00 1 X
01 X 1
11 X X
10 0 0
D0:
Q2\Q1Q0 0 1
00 0 X
01 X 0
11 X X
10 1 0
D 2 = Q0 + Q 2.Q1
Current state Next state Q2 Q1 Q0 Q2+ Q1+ Q0+ 0 0 0 0 1 0 0 0 1 0 0 0 0 1 0 1 0 1 0 1 1 0 0 0 1 0 0 0 0 0 1 0 1 1 1 0 1 1 0 0 0 0 1 1 1 0 0 0
000 011 001
000
010
101
110
Modified state diagram
Modified state transition table
D1 = Q1
000
D0 = Q 2.Q1 E1.2 Digital Electronics 1
12.13
21 November 2008
Undefined states to “zero” state
E1.2 Digital Electronics 1
Q2\Q1Q0 0 1
00 0 0
01 0 1
11 0 0
10 1 0
D 2 = Q 2.Q1.Q0 + Q 2.Q1.Q0
D1:
Q2\Q1Q0 0 1
00 1 0
01 0 1
11 0 0
10 0 0
D0 = Q 2.Q1.Q0
Q2\Q1Q0 D0: 0 1
00 0 0
01 0 0
11 0 0
10 1 0
Q 2.Q1.Q0
D1 = Q 2.Q1.Q0 + Q 2.Q1.Q0 CLOCK C1
D2 D1 D0
The terms
Q 2.Q1.Q0 Q 2.Q1.Q0
1D
Q2 Q1 Q0
can be reused to simplify the circuitry
This approach produces more complicated circuits, but they are more robust 12.15
21 November 2008
Undefined states to “zero” state
D2:
E1.2 Digital Electronics 1
12.14
Q 2.Q1.Q0 21 November 2008
E1.2 Digital Electronics 1
12.16
21 November 2008
A +: Current state
Implementing an FSM with JK flip-flops Current state
Next state
A
B
C
A+
B+ C+
0
0
0
0
0
1
0
0
1
0
1
0
0
1
0
0
1
1
0
1
1
1
0
0
1
0
0
1
0
1
1
0
1
1
1
0
1
1
0
1
1
1
1
1
1
0
0
0
E1.2 Digital Electronics 1
The full 3-bit binary counter from earlier:
CLOCK
combinational circuit ?
C1
J2 K2 J1 K1 J0 K0
A
1J 1K
B C
12.17
21 November 2008
Binary counter circuit using JK flip-flops The Boolean equations for all Js and Ks:
In this case, the J and K inputs to each FF happen to be the same – this is not usually the case • • •
1 1
12.19
C
A+
B+ C+
0
0
0
0
0
0
0
1
0
1
0
0
1
0
0
1
1
0
1
1
1
0
0
1
0
0
1
0
1
1
0
1
1
1
0
1
1
0
1
1
1
1
1
1
0
0
0
Transition
J
K
0 to 0
0
X
0 to 1
1
X
1 to 0
X
1
1 to 1
X
0
1
K2
B +: J1 K1
C +: J0 K0
E1.2 Digital Electronics 1
00 0 X
01 0 X
11 1 X
10 0 X
A\BC 0 1
00 X 0
01 X 0
11 X 1
10 X 0
A\BC 0 1
00 0 0
01 1 1
11 X X
10 X X
A\BC 0 1
00 X X
01 X X
11 1 1
10 0 0
A\BC 0 1
00 1 1
01 X X
11 X X
10 1 1
A\BC 0 1
00 X X
01 1 1
11 1 1
10 X X
12.18
21 November 2008
CLOCK C1
A
1J 1K
B
J2 K2 J1 K1 J0 K0
1J 1K
1D
A B C
C
JK flip-flop circuits usually use less combinational logic
In VLSI integrated circuits, D flip-flops are preferred because they are smaller, faster, and require fewer wires E1.2 Digital Electronics 1
12.20
A B
C1
D2 D1 D0
21 November 2008
1 1
CLOCK
C
The Karnaugh maps using JK flip-flops have a lot of “don’t cares” The logic is usually simpler than circuits that use D flip-flops But have to work out twice as many Boolean equations
E1.2 Digital Electronics 1
B
A\BC 0 1
D flip-flop circuits are usually easier to design
C1
J2 K2 J1 K1 J0 K0
A
J2
D and JK flip-flop comparison
CLOCK
J 2 = K 2 = B.C J 1 = K1 = C J0 = K0 =1
Next state
21 November 2008
Implementing an FSM with ROM
Implementing an FSM with ROM Address A[2:0]
000
010
101
ROM programming table
110
All other locations contain 000 RESET CLOCK ROM
R C1
D0 D1 D2
1D
RESET CLOCK
Q0 Q1 Q2
A0 A1 A2
E1.2 Digital Electronics 1
12.21
21 November 2008
E1.2 Digital Electronics 1
23x3 ROM
D0 D1 D2
Data D[2:0]
A2
A1
A0
0
0
0
0
1
0
0
1
0
1
0
1
1
0
1
1
1
0
1
1
0
0
0
0
D2 D1
D0
R C1
D0 D1 D2
12.22
1D
Q0 Q1 Q2
21 November 2008
E1.2 Digital Electronics 1
• Finite State Machines (FSMs) • FSM design procedure
12.1
21 November 2008
E1.2 Digital Electronics 1
Design of a synchronous binary counter CLOCK
From the last lecture:
• • •
combinational circuit ?
C1
D2 D1 D0
1D
E1.2 Digital Electronics 1
12.3
Step 1: start with the transition table of the flip-flops to be used in the FSM Output transition required
How do we design the combinational circuit? This counter is an example of a Finite State Machine (FSM) The following procedure can be used for any FSM
21 November 2008
21 November 2008
FSM design procedure 1 •
A B C
12.2
D-type FF inputs
JK-type FF inputs
D
J
K
0 to 0
0
0
X
0 to 1
1
1
X
1 to 0
0
X
1
1 to 1
1
X
0
E1.2 Digital Electronics 1
12.4
D
CLK
Output
0
↑
0
1
↑
1
J
K
CLK
0
0
↑
Output Q
1
0
↑
Q=1
0
1
↑
Q=0
1
1
↑
Q 21 November 2008
FSM design procedure 2 •
FSM design procedure 3
Step 2: for each state variable in the state transition table, construct Karnaugh maps for each input in the flip-flop transition table Current state
Next state
A
B
C
A+
B+ C+
0
0
0
0
0
1
0
0
1
0
1
0
0
1
0
0
1
1
0
1
1
1
0
0
1
0
0
1
0
1
1
0
1
1
1
0
1
1
0
1
1
1
1
1
1
0
0
0
E1.2 Digital Electronics 1
For the 3-bit binary counter example, there are 3 state bits. If we use D flip-flops, there will be 3 “next-state” functions to implement.
For this example, we will use D flip-flops D2, D1, and D0 implement the next values of A, B, and C respectively
If we use JK flip-flops, we need Kmaps for both inputs of each flipflop, which would be 6 Boolean functions. 12.5
21 November 2008
D1
D0
E1.2 Digital Electronics 1
FSM design procedure 4 •
D2
A\BC 0 1
00 0 1
01 0 1
11 1 0
10 0 1
A\BC 0 1
00 0 0
01 1 1
11 0 0
10 1 1
A\BC 0 1
00 1 1
01 0 0
11 0 0
10 1 1
12.6
21 November 2008
FSM design procedure 5
Step 3: extract the Boolean expressions from the K-maps
•
A\BC 0 1
00 0 1
01 0 1
11 1 0
10 0 1
A\BC 0 1
00 0 0
01 1 1
11 0 0
10 1 1
D1 = B C + BC = B ⊕ C
A\BC 0 1
00 1 1
01 0 0
11 0 0
10 1 1
D0 = C
Step 4: implement using combinational logic
D 2 = A BC + AB + AC CLOCK
E1.2 Digital Electronics 1
12.7
C1
21 November 2008
D2 D1 D0
E1.2 Digital Electronics 1
12.8
1D
A B C
21 November 2008
Design of arbitrary code counters
Example •
•
It may be necessary to design counters that count sequences other than binary numbers
•
Examples: – counters which never reach their maximum value, such as a zero-to-nine counter (which uses 4 bits) – counters which follow a specific code, such as a Gray Code
•
The design procedure presented for binary counters can be extended to arbitrary code counters
E1.2 Digital Electronics 1
12.9
21 November 2008
Current state
Q2 Q1 Q0 Q2+ Q1+ Q0+
State transition table: • •
•
Next state
0
0
0
0
1
0
0
1
0
1
0
1
1 0 1 1 1 0 What about states 001, 011, 1 1 0 0 0 0 100, 111? These we call undefined states – what happens if the circuit gets into an undefined state, for example at power-up? Two approaches: 1. Use a reset signal to ensure the FSM enters the “zero” state at power-up, treat undefined states as “don’t care” 2. Design the FSM to explicitly enter the “zero” state from undefined states
E1.2 Digital Electronics 1
12.11
21 November 2008
Design a 3-bit counter to count the decimal sequence: 0, 2, 5, 6, 0, 2, 5, … Decimal Q2 Q1 Q0
Counting sequence:
State diagram:
000
0
0
0
0
2
0
1
0
5
1
0
1
6
1
1
0
010
E1.2 Digital Electronics 1
101
110
12.10
21 November 2008
Undefined states as “don’t care” Circuit diagram:
RESET CLOCK combinational circuit ?
E1.2 Digital Electronics 1
R C1
D0 D1 D2
12.12
1D
Q0 Q1 Q2
21 November 2008
Undefined states as “don’t care” Current state Q2 Q1 Q0
Next state Q2+
Q1+
Q0+
0
0
0
0
1
0
0
1
0
1
0
1
1
0
1
1
1
0
1
1
0
0
0
0
Undefined states to “zero” state
D2:
Q2\Q1Q0 0 1
00 0 X
01 X 1
11 X X
10 1 0
D1:
Q2\Q1Q0 0 1
00 1 X
01 X 1
11 X X
10 0 0
D0:
Q2\Q1Q0 0 1
00 0 X
01 X 0
11 X X
10 1 0
D 2 = Q0 + Q 2.Q1
Current state Next state Q2 Q1 Q0 Q2+ Q1+ Q0+ 0 0 0 0 1 0 0 0 1 0 0 0 0 1 0 1 0 1 0 1 1 0 0 0 1 0 0 0 0 0 1 0 1 1 1 0 1 1 0 0 0 0 1 1 1 0 0 0
000 011 001
000
010
101
110
Modified state diagram
Modified state transition table
D1 = Q1
000
D0 = Q 2.Q1 E1.2 Digital Electronics 1
12.13
21 November 2008
Undefined states to “zero” state
E1.2 Digital Electronics 1
Q2\Q1Q0 0 1
00 0 0
01 0 1
11 0 0
10 1 0
D 2 = Q 2.Q1.Q0 + Q 2.Q1.Q0
D1:
Q2\Q1Q0 0 1
00 1 0
01 0 1
11 0 0
10 0 0
D0 = Q 2.Q1.Q0
Q2\Q1Q0 D0: 0 1
00 0 0
01 0 0
11 0 0
10 1 0
Q 2.Q1.Q0
D1 = Q 2.Q1.Q0 + Q 2.Q1.Q0 CLOCK C1
D2 D1 D0
The terms
Q 2.Q1.Q0 Q 2.Q1.Q0
1D
Q2 Q1 Q0
can be reused to simplify the circuitry
This approach produces more complicated circuits, but they are more robust 12.15
21 November 2008
Undefined states to “zero” state
D2:
E1.2 Digital Electronics 1
12.14
Q 2.Q1.Q0 21 November 2008
E1.2 Digital Electronics 1
12.16
21 November 2008
A +: Current state
Implementing an FSM with JK flip-flops Current state
Next state
A
B
C
A+
B+ C+
0
0
0
0
0
1
0
0
1
0
1
0
0
1
0
0
1
1
0
1
1
1
0
0
1
0
0
1
0
1
1
0
1
1
1
0
1
1
0
1
1
1
1
1
1
0
0
0
E1.2 Digital Electronics 1
The full 3-bit binary counter from earlier:
CLOCK
combinational circuit ?
C1
J2 K2 J1 K1 J0 K0
A
1J 1K
B C
12.17
21 November 2008
Binary counter circuit using JK flip-flops The Boolean equations for all Js and Ks:
In this case, the J and K inputs to each FF happen to be the same – this is not usually the case • • •
1 1
12.19
C
A+
B+ C+
0
0
0
0
0
0
0
1
0
1
0
0
1
0
0
1
1
0
1
1
1
0
0
1
0
0
1
0
1
1
0
1
1
1
0
1
1
0
1
1
1
1
1
1
0
0
0
Transition
J
K
0 to 0
0
X
0 to 1
1
X
1 to 0
X
1
1 to 1
X
0
1
K2
B +: J1 K1
C +: J0 K0
E1.2 Digital Electronics 1
00 0 X
01 0 X
11 1 X
10 0 X
A\BC 0 1
00 X 0
01 X 0
11 X 1
10 X 0
A\BC 0 1
00 0 0
01 1 1
11 X X
10 X X
A\BC 0 1
00 X X
01 X X
11 1 1
10 0 0
A\BC 0 1
00 1 1
01 X X
11 X X
10 1 1
A\BC 0 1
00 X X
01 1 1
11 1 1
10 X X
12.18
21 November 2008
CLOCK C1
A
1J 1K
B
J2 K2 J1 K1 J0 K0
1J 1K
1D
A B C
C
JK flip-flop circuits usually use less combinational logic
In VLSI integrated circuits, D flip-flops are preferred because they are smaller, faster, and require fewer wires E1.2 Digital Electronics 1
12.20
A B
C1
D2 D1 D0
21 November 2008
1 1
CLOCK
C
The Karnaugh maps using JK flip-flops have a lot of “don’t cares” The logic is usually simpler than circuits that use D flip-flops But have to work out twice as many Boolean equations
E1.2 Digital Electronics 1
B
A\BC 0 1
D flip-flop circuits are usually easier to design
C1
J2 K2 J1 K1 J0 K0
A
J2
D and JK flip-flop comparison
CLOCK
J 2 = K 2 = B.C J 1 = K1 = C J0 = K0 =1
Next state
21 November 2008
Implementing an FSM with ROM
Implementing an FSM with ROM Address A[2:0]
000
010
101
ROM programming table
110
All other locations contain 000 RESET CLOCK ROM
R C1
D0 D1 D2
1D
RESET CLOCK
Q0 Q1 Q2
A0 A1 A2
E1.2 Digital Electronics 1
12.21
21 November 2008
E1.2 Digital Electronics 1
23x3 ROM
D0 D1 D2
Data D[2:0]
A2
A1
A0
0
0
0
0
1
0
0
1
0
1
0
1
1
0
1
1
1
0
1
1
0
0
0
0
D2 D1
D0
R C1
D0 D1 D2
12.22
1D
Q0 Q1 Q2
21 November 2008
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