Lecture Notes 14

Timing Issues in Integrated Circuits

Lecture-14 ECE467 Fall Semester Masud H Chowdhury 1

Final Exam Schedule Final Exam: ECE 467 Date: Tuesday, December 4 Time: 5:00 - 7:00 pm Lecture 12 – last lecture Plus fundamental concepts learned in the entire course

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Timing Classification of Digital System •

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Systems, where signals transition only at predetermined periods in time can be of three types – Synchronous – Mesochronous – Plesiochronous Systems, where signals can transition at arbitrary time is as known as – Asynchronous Synchronous System – A globally distributed synchronization signal enforce a well-defined ordering of the signal transition – A synchronous signal has exact same frequency as the local clock and maintains a know fixed phase offsets to that clock – The flow of data in this system is in lockstep with system clock Mesochronous System: – The signal has same frequency as the local clock, but has an unknown phase offset with respect to that clock Plesiochronous System: – The signal has a frequency that is nominally same as that of local clock Asynchronous System: – Signal is not tied to any clock, and can transition arbitrarily at any time 3

Timing Parameters of Synchronous Design •

Performance of a synchronous system is guided by the following timing parameters: – Setup time (tsu ): It is the time the data inputs (D) must be valid before the clock transition. – Hold time (thold ): The hold time is the time the data input must be valid after the clock edge. – Propagation delay of the register (tc-q ): It is the worst-case propagation delay for the input D of the register to be copied into the output Q. – Propagation delay of the logic (tlogic ): The worst delay of the combinational logic block. – Contamination Delay (tcd ): The minimum delay of any block is called the contamination delay – The positions of the rising edges of the clocks CLK1 and CLK2 relative to reference

• Ideal assumptions:

– Under ideal condition the two clocks have identical position relative to the global reference: tclk1 = tclk2 – The minimum required clock period and the hold time constraint are determined solely by the timing parameters of the register and the logic

T >= tc-q + tsu + tlogic

tcdregister

+ tcdlogic >= thold

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Clock Skew Practical Clock Signal: – The clock is practically never ideal. The rising edges of the clock signals at the two registers of a system will be neither perfectly periodic nor perfectly simultaneous – Process and environmental variations will introduce both temporal and spatial variations in clock signal – The variations, which may lead to performance degradation and/or malfunctioning, give rise to two problems in clocking synchronous system • Clock Skew: The spatial variation in arrival time of a clock transition • Clock Jitter: The temporal variation of the clock period at a given point on chip • Variation of the pulse width: Important for level sensitive clocking

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Clock Skew: – Clock skew between two points i and j on an IC is given by: δ (i,j) = ti-tj, where ti and tj are the positions of the rising edge of the clock with respect to the reference – Clock skew is caused by static mismatches in the clock paths and differences in the clock load – By definition clock skew is constant from cycle to cycle. That is, if in one clock cycle CLK2 lagged CLK1 by δ , then on next cycle, it will lag it by the same amount – Clock skew does not result in clock period variation, but only in phase shift

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Positive and Negative Clock Skew • •

Depending on the routing direction and position of the clock source clock skew can be positive or negative Consider the transfer of data between register R1 and R2. – Positive skew: the rising edge is delayed by a positive δ at the second register – Negative skew: the rising edge of CLK2 happens before the rising edge of CLK1

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Positive and Negative Clock Skew •

Impact of Positive Skew: – Since the rising edge of CLK2 is delayed by a positive δ , the time available for a signal to propagate from R1 to R2 is increased by δ – Again to avoid race, we must ensure that the minimum delay through the register and the logic is long enough that the inputs to R2 are valid for a hold time after the rising edge of CLK2. – Therefore, the constraint on the minimum clock period and hold time can be derived as follows: T + δ >= tc-q + tsu + tlogic or T >= tc-q + tsu + tlogic -δ thold + δ

< = tcdregister

+ tcdlogic

or

δ <= tcdregister

+ tcdlogic

- thold

– Positive clock skew has the potential to improve performance, since the minimum clock period required is reduced in the presence of positive clock skew – The hold time constraint gives the limiting value of positive skew to avoid race condition

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Positive and Negative Clock Skew •

Impact of Negative Skew: – Since the rising edge of CLK2 arrives earlier with respect to the reference, the time available for a signal to propagate from R1 to R2 is decreased by δ – Again to avoid race, we must ensure that the minimum delay through the register and the logic is long enough that the inputs to R2 are valid for a hold time after the rising edge of CLK2. – Therefore, the constraint on the minimum clock period and hold time can be derived as follows: T - δ >= t + t + t or T >= t + t + t +δ c-q

thold -δ

< = tcdregister

su

+ tcdlogic

logic

c-q

or

su

δ >= thold - tcdregister

logic

- tcdlogic

– Negative clock skew degrades performance, since the minimum clock period required is increased by δ – The hold time constraint ensures that the circuit never fails with negative clock skew

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Clock Jitter • • •

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Clock jitter refers to the temporal variation of the clock period at a given point on the chip Clock period can reduce or expand on a cycle by cycle basis Clock jitter is a temporal uncertainty measure, and can be measured is various ways: – Absolute jitter (tjitter): Worst case variation of a clock edge at a given location with respect to an ideal periodic reference clock edge – Cycle-to-cycle jitter (Tjitter): Time-varying deviation of a single clock cycle with respect to a reference clock. For given spatial location i, it is given by Tijitter(n) = ticlk,n+1 – ticlk,n – Tclk Here, ticlk,n+1 and ticlk,n represent the arrival time of n+1th and nth clock edge at node i, and Tclk is the nominal clock period. Impact of clock jitter: – Under the worst-case condition, the magnitude of the cycle-to cycle jitter (Tjitter) is 2tjitter

– The available time to complete the operation is reduced by 2tjitter in worst-case

T - 2tjitter >= tc-q + tsu + tlogic

or

T >= tc-q + tsu + tlogic + 2tjitter

– Therefore, jitter directly reduces performance of sequential circuit

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Combined Impact of Clock Skew and Jitter •

Impact on Minimum Clock Period: – Assume that a static positive clock skew δ exists between register R1 to R2. Also the clock experience a jitter of tjitter – The worst case occurs when the leading edge of the current clock period on CLK1 happens late (edge 3) and the leading edge of the next cycle of CLK2 happens early (edge 10). This results in the following constraint:

T + δ - 2tjitter ≥ tc-q + tsu + tlogic or T ≥ tc-q + tsu + tlogic - δ + 2tjitter

For negative skew

T - δ - 2tjitter ≥ tc-q + tsu + tlogic or T ≥ tc-q + tsu + tlogic + δ + 2tjitter

– Therefore, positive skew can provide a performance advantage, and negative skew degrades performance – But jitter always has a negative impact on the minimum clock period 10

Combined Impact of Clock Skew and Jitter •

Impact on Minimum Delay and Hold Time: – To formulate minimum delay constraint, consider the case in which the leading edge of the CLK1 cycle arrives early (edge 1), and the leading edge of the current cycle of the CLK2 arrives late (edge 6). – The separation between edges 1 and 6 should be smaller than the minimum delay through the network. This results in thold + δ

+ 2tjiter < tcdregister + tcdlogic or δ < tcdregister + tcdlogic - thold - 2tjitter

– The relation indicate that the acceptable skew is reduced by jitter of the two signals

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Sources of Clock Skew and Jitter: The sources of clock uncertainty can be divided into two categories: - Systemic - Random: Mismatches can also be characterized as - Static - Time-varying

The sources: Clock-signal generation: • Analog clock signal generators (VCO) are very sensitive to intrinsic device noise and power supply variations • Coupling with surrounding noisy digital circuits through common substrate

Manufacturing device variations: • Mismatch of buffers along different clock paths • Variation of oxide thickness, doping profile, device dimensions

Interconnect variations: • Vertical (height) and lateral (width) dimension variations • Variation in Inter-layer Dielectric (ILD) thickness

Environmental variations: • Temperature variations: •Due to variations in power dissipation • Power supply level variations: o Due to IR drop, Inductive effects o Fluctuation due to switching activities o Variable current requirements between idle and active states of the logic circuits

Capacitive Coupling: • Coupling between clock lines and adjacent signal lines 12 • Variation in gate capacitance

Clock Distribution Techniques The Design Goals: – Minimize clock skew and jitter – Reduce power dissipation in clock network

The Issues to be Considered: – – – – –

Type of material used for wire Topology and hierarchy Wire and buffer sizing Rise and fall time Partitioning of the load capacitances

Components of Clock Network: – Global clock network – Local clock network

Clock Distribution Scheme: Since the absolute delay from central clock source is irreverent and only relative phases between two clocking points is important, common approach to distribute global clock is to use balanced paths, called trees, such as – H-tree network – Matched RC trees

For local clock distribution maintaining equal delay at every point is very important. Therefore a mesh type structure is used, known as – Grid network

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Clock Distribution Techniques • H-tree network – It is the most common clock distribution scheme – The distribution is based on the shape of letter ‘H’ – Due to symmetry of the construction the distance from the center to any tip is constant. This enables balancing each path to minimize clock skew – The clock is first routed to the center point of the chip, and then balanced paths distribute the reference to various leaf nodes – This configuration is very useful for regular array network in which all elements are identical and the clock can be distributed as a binary tree – A generalized variation of H-tree network is a matched RC tree

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Clock Distribution Techniques • Matched RC tree network – In this scheme clock is distributed in such a way that interconnections carrying the clock signals to functional sub blocks are of equal length. – Therefore, this general approach does not rely on regular physical structure, but it tries to match RC values in each path

• Grid Structure: – Grids are typically used in the final stage of the clock network – Here the delay from the final driver to each load is not matched. Rather the absolute delay is minimized – The advantage of this scheme is that clock design can be changed in later phase since the clock is easily accessible at various points – But power dissipation is higher since this structure has lot of extra 15 interconnections