Lecture Notes 15

Technology Scaling Trends and Interconnect Issues Lecture-15

Fall Semester Masud H. Chowdhury Electrical and Computer Engineering University of Illinois at Chicago 1

Technology Scaling • Systems at a glance: Present Features

0.13 micron 10M/sq.cm 3.06 GHz 1.01-2.5V 70 Watts 1.2 Watts

Future Around 2012* FEATURE SIZE

0.035 micron DENSITY 180M/sq.cm ON-CHIP CLOCK 10 GHz SUPPLY VOLTAGE 0.5-0.6V POWER (HIGH PERF.) 175 Watts POWER (MOBILE) 3.2 Watts

• Interconnect Dimensions: h

d w

h M w

d

Past

0.7-.9um 0.3-0.4um 0.3-0.4um 1.7-1.9

h, w, and d going down M Mh M d w but h/w going up Reference

Present/Future

h w d h/w

0.2-0.4um 0.1-0.15um 0.1-0.15um 2.5-3.0

h w

d

Technology scaling data for metal layer 2 Technology size

h

w

d

h/w

0.5 um

0.98 um

0.75 um

0.95 um

1.31

0.25 um

0.89 um

0.48 um

0.45 um

1.85

2

Interconnect Wire Inside IC •

• •

•

Each wire in an interconnect network connects a transmitter (or transmitters) to a set of receivers and is implemented as a chain of wire segments of various lengths and geometries At the early stages the impact of these on-chip interconnect wires were negligible Wiring in current IC technologies form a complex geometry that introduces capacitive, resistive and inductive parasitics, which have become dominant over device parasitics in deep submicron technologies. These interconnect parasitics have multiple impacts on circuit behavior – Increased propagation delay – Impact on power consumption – Introduction of noise

receivers

transmitters

schematics

physical

3

Interconnect Wire Inside IC •

In current process multiple layers of aluminum or copper, and at least one layer of polysilicon wires are available to provided connectivity in very high densities ICs

Layout cross section

4

Interconnect Example: Intel 0.25 micron Process

5 metal layers Ti/Al - Cu/Ti/TiN Polysilicon dielectric

3D micro-photographic view

5

Interconnect Parasitics: Capacitance

•

Parallel Plate Model:

Current flow

Permittivity

L W

H tdi

Dielectric Substrate

Electrical-field lines

ε di cint = WL t di

S Cwire =

S 1 = S ⋅ SL SL

Here W and L are width and length of the wire; ε

di

and tdi is the permittivity and thickness of dielectric

•

Interconnect Parasitics: Capacitance

Fringing Capacitance:

– Continuous push for denser circuits leads to steady reduction of W/H ratio, which makes parallel plate assumption inaccurate – The capacitance between sidewalls of the wires and the substrate, known as fringing capacitance, can not be ignored, which is illustrated in the figure below •

•

An exact model to incorporate both parallel plate and fringing capacitance is very complex Among various models a simplified and common used model for interconnect capacitance to substrate is as shown below

(a ) H

W - H /2

• +

ground or substrate (b )

Here the model is comprised of a parallel plate capacitance determined orthogonal field between wire of width w=W-H/2, and a fringing capacitance modeled by a cylindrical wire with dimension equal to interconnect thickness H 7

•

Interconnect Parasitics: Capacitance

Fringing Capacitance Versus Parallel Plate Capacitance:

8

Interconnect Parasitics: Capacitance • Capacitance in Multi-Layer Representation:

–

= CG +orCclateral + Cpcapacitance + Cf Ctotal However, the coupling has become the dominant component among these capacitances

Cf M2

CC

M1

CG GND

Capacitance in multi-layer representation coupling/total capacitance

– As digital technology entered into the era of multi-layer interconnect lines some other capacitive components become significant – In advanced CMOS technologies the total capacitance is estimated as the sum of four components: • Line-to-ground/substrate capacitance • Coupling or lateral capacitance - between two nets on the same layers • Parallel or crossover capacitance - due to overlap area of two nets on different layers • Fringing capacitance - formed between the edge of one conductor and the surface of another conductor on different layers

Cp

M3

0.8

0.18 um

0.7

0.25 um

0.6

0.5 um

0.5 0.4 0.3 0.2 0.1 0 1

1.2

1.4

1.6

1.8

2

spacing/min spacing

Coupling capacitance compared to total capacitance with technology 9 scaling

Interconnect Parasitics: Capacitance •

Components of Wire Capacitance in Multi-Layer Representation:

fringing

parallel

10

Interconnect Parasitics: Resistance

•

Interconnect resistance can be obtained by the following simplified model

L H

W

ρ L R= HW ρ R = H = Sheet Resistance ρ = resistivity of the material 11

Interconnect Parasitics: Resistance

Dealing With Resistance: • Interconnect resistance is increasing with continuous scaling (decreasing cross-section and increasing length L with chip size), and has become very critical • Various steps have been adopted to deal with wire resistance – Use Better Interconnect Materials: Due to lower sheet resistance aluminum has been extensively used, but now it is being being replaced by copper due to its lower resistivity – Selective Technology Scaling: H is being reduced much slower than W so that wire crosssection does not decrease rapidly – More Interconnect Layers: reduce average wire-length – Advanced processes also offer silicide polysilicon and diffusion layers as alternatives to regular polysilicon Silicide PolySilicon

Silicides: WSi 2, TiSi 2, PtSi 2 and TaSi Conductivity: 8-10 times better than Poly

SiO2

n+

n+ p

12

Interconnect Parasitics: Inductance

Definition of Inductance: • A changing current passing through a conductor generates a voltage drop proportional to the rate of change of the current ∆ V = L(di/dt) • The constant of proportionality L is called the inductance of the conductor • The parasitic element defined above is also called self inductance of the conducting wire • Another inductive parasitic element is mutual inductance, whose definition is as follows: – A changing current in an inductive wire induces a voltage change on a neighboring inductive wire. The induced voltage is proportional to the rate of change of current, and the constant of proportionally M is called the mutual inductance between the conductors M = k/√(L1L2) – Here k is mutual inductive coefficient, L1 and L2 are the self inductances of the two conductors

M

Rdrv

CC L

R

CG

13

•

Ideal Wire: – – – – –

Interconnect Modeling

No impact on electrical behavior of the circuit Occur as simple lines with no attached parasitic No voltage drop along the wire – the whole wire is equipotent Signal propagates immediately from end to end – no delay in wires No wire is ideal Short Circuit

•

Practicality of Ideal Wire: – The effect of short wires inside small circuits such as gates can be ignored – In the early phase of design when the devices properties are analyzed wires can be considered as ideal to make the analysis simple – Two decades back, when the minimum feature size was about 5μm, the gate parasitic impedance dominated integrated circuit performance and interconnect lines were modeled as a short or ideal wire

14

•

Interconnect Modeling

Introduction of Wire Capacitance:

– With the continuous scaling of device and wire sizes, the interconnect capacitance to reference plane became comparable to the device capacitances, requiring the introduction of capacitance in line modeling – Since at low and medium frequency ranges resistive components is small, only capacitive component of the wire was considered at the early stages VDD

VDD M2 Vin

Cg4

Cdb2

Cgd12

M4

Vout

M1

Cdb1

Cw

Vout2

Cg3

M3

Interconnect

Fanout

Simplified Model

Vin

Vout CL

15

•

Interconnect Modeling

Lumped Capacitive Model:

– Interconnect parasitics are distributed along the length – When only one parasitic is dominant, and the interaction between the components is small, and when looking at only on aspect of the circuit behavior it is useful to model the wire parasitic as a lumped element – Lumped model can be analyzed manually using simple differential equation – In this lumped model the line is still represents an equipotent region – no voltage drop due to the wire itself – The lumped capacitor affects the performance of the driving gate – Lumped capacitive model is very simple and widely used for many short and wide lines where resistive component is insignificant

16

•

Lumped RC Model:

Interconnect Modeling

– With further scaling down of technology, the cross sectional area of the lines has been scaled down to provide more lines per unit area, while the length of the lines has increased with chip size and complexity. As a result the resistance of long signal lines increased significantly – Equipotent – zero voltage drop assumption is no longer valid, and a resistive-capacitive model is required – In this model the total wire resistance is put into a single resistor, and similarly the total capacitance is combined into one capacitor – Lumped RC model is very useful and first-order model used intensively in analyzing the transient behavior of the transistor-wire network

Rwire Driver

•

Cwire

RC Tree or Chain Model:

– Lumped RC model is pessimistic for a resistive-capacitive line – Resistance at the beginning of the line sees more capacitance than the resistance downward along the line – Scaling trends pushed interconnect modeling to the next step of modeling interconnect lines as RC Tree or RC Chain. – In this modeling a long line is broken into multiple segments, where the resistance and capacitance of each segment are lumped into one resistance and one capacitance – For analyzing this type of RC Tree or RC Chain, Elmore Delay model is used 17

Interconnect Modeling • Distributed RC Model: – RC Tree or RC Chain gives better accuracy as compared to the lumped RC model – For very high performance circuit, where margin of tolerance is very narrow a distributed RC model would be much desirable – Since the resistance and capacitance of the line are distributed along the length of the line, a truly distributed model, where the parasitic elements are distributed at every infinitesimal segment, will give accurate performance

– But analysis of pure distributed line with associated parasitics for every infinitesimal segment is very complex and time consuming – Practical analysis of high performance interconnect circuits uses RC Tree or RC Chain model between lumped and truly distributed model. – Number of segments in the RC Tree or Chain determines accuracy of analysis – Higher number of segments gives better accuracy, but makes the analysis more complex 18

•

Interconnect Delay Analysis with Different RC Line Model Delay Analysis of Lumped RC Line:

– Propagation delay is defined as the time difference between 50% transition points of input and output signals – From earlier analysis we found that delay of a CMOS inverter can be derived from its RC model VDD

VDD

t pHL = 0.69τ n = 0.69 Rn .C L

Rp Vout CL Rn

Vout CL

t pLH = 0.69τ p = 0.69 R p .C L

Cwire

Driver Rwire

t Dwire = 0.69τ wire = 0.69 Rwire .Cwire

Inver RC Model and Delay Lumped RC Line Model and Delay – For lumped RC line we can derive exactly similar delay expression

•

Delay Analysis Line Modeled as RC Chain – Elmore RC time constant at node N i

– The Propagation delay:

t

N

= 0.69τ

Dwire – The Elmore RC time constant is derived byN determining the path between node i and the source/input node. Each term in the summation expression is product of the capacitance of node i and the total resistance of that path.

19

•

Interconnect Delay Analysis with Different RC Line Model Delay Analysis of Distributed RC Line: – In distributed model the line is divided into N number of equal-length segments, each segment having a length ΔL. – Here per unit length resistance and capacitance of the line are r and c respectively – The Elmore RC time constant:

– Here R is the total resistance of the line – C is the total capacitance of the line – For distributed line N is very large:

t Dwire = 0.69τ DN = 0.69 ( •

RC ) = 0.345 RC = 0.345 rcL2 2

Observations: – We observe that the delay of RC line shows quadratic dependence on line length – The propagation delay for truly distributed line is half of the delay obtained from lumped RC model – Therefore, lumped model is pessimistic, since it overestimates interconnect delay. – RC chain or tree model is more optimistic model with better delay approximation. This model approximates Elmore RC constant somewhere between RC and RC/2 – For accurate delay analysis, distributed model is the most appropriate 20

Interconnect Modeling • Distributed RC Model with Coupling Capacitance: – In current extremely dense integrated circuits, the line-to-reference capacitance alone has become insufficient for signal behavior analysis – The lateral or coupling capacitance, formed by two parallel edges of non-overlapping conductors in the same plane, is increasing as the spacing between conducting lines in the same plane decreases, which came down close to or less than 1μm

– To improve the degrading resistance of long wires, the vertical dimensions of the lines scaled slowly as compared to the horizontal dimension, leading to a very high aspect ratio. Consequently, the coupling or lateral capacitance is becoming even stronger due to longer overlap area among lines in the same layer. – This is particularly true in the upper metal layers, where power and clock distribution networks, and global signal lines run across the whole chip area. They require longer, thicker and wider wires to ensure power and signal distribution, lower IR drop, reduced clock skew, robustness under process variations, and signal reliability. – Bus-dominant designs worsen the effects of coupling, since it results in longer parallel runs. 21

Interconnect Modeling • Introduction of Self and Mutual Inductances – Due to faster on-chip rise time and the drive for low resistive lines, currently on-chip inductance have become important – Longer and wider wires in clock distribution networks and upper metal layers exhibit significant inductive effects – Accuracy requirements at very higher operating frequencies, make it crucial to include self and mutual inductances – Figure below illustrates all the factors that influence the interaction of two adjacent interconnects lines – Therefore, in current deep submicron technology for very high performance integrated circuits analysis lines are modeled as distributed RLC lines with coupling capacitance and mutual inductances

M

Rdrv

CC

L

R

CG

All that influence performance 22

Transition of Interconnect Modeling Short Circuit Lumped C Lumped RC Distributed RC

Distributed RLC

M

Rdrv

L

CC R

CG 23

All that influence performance

Summary Interconnect parameters dominating Decreasing feature sizes Dominance of coupling capacitance Inclusion of inductances

Signal integrity issue becomes critical Increasing CCT /CTOTAL ratio Decreasing noise margin

• Power Consumption going up 24