#impact Of Technology Scaling On Substrate Noise Generation Mechanisms

IEEE 2004 CUSTOM INTEGRATED CIRCUITS CONFERENCE

Impact of Technology Scaling on Substrate Noise Generation Mechanisms Mustafa Badaroglu',*, Piet Wambacq', Geert Van der Plas', Stephane Donnay', Georges Gielen3,and Hugo De Man'.3 'IMEC, DESICS, Kapeldreef 75, B-3001 Leuven, Belgium, *Also PbD. student at ESAT, K.U. Leuven, Belgium 3ESAT, K.U. Leuven, Belgium Abstract The performance of mixed-mode ICs can be severely limited by the substrate noise that is generated by digital circuits. To reduce this problem and to assess its evolution with CMOS technology scaling, the different mechanisms that generate this substrate noise need to be well understood. In this paper we show that with technology scaling substrate noise due to power-supply-line coupling becomes the dominant coupling mechanism, which is several orders of magnitude larger than the substrate noise due to the source/drain capacitive coupling and the impact ionization. Further, we show that the peak value of the power-supply-line coupling noise becomes more dependent on the switching activity ratio of the circuit rather than the LdYdt noise as a result of the decrease in switching time with technology scaling. These insights are believed to be very useful for the development of low-noise digital design techniques in future CMOS technologies.

1. Introduction Substrate noise is a major obstacle for single-chip integration of mixed-signal systems [11. Previous publications dealing with the generation mechanisms of the substrate noise have mostly analyzed the components individually and have compared them only experimentally to each other in an effort to find the dominant mechanism without looking at the boundary conditions setting their dominance [2][3]. Knowing the chip size conditions is important for a designer in order to control the parameters for reducing substrate noise generation. For example, general practice suggests that reducing the bondwirelpackage parasitic inductance will reduce the peak value of the generated substrate noise. However, we will show in this paper that reducing the inductance is not always useful for reducing the substrate-noise peak value as one would expect. Here the only ways to reduce the substrate noise are to increase the decoupling, to decrease the power consumption, and/or to increase the isolation of the substrate. The work presented in [4] presents an effective use of low-noise digital design techniques by addressing that most of the supply current flows through the gate and its load, while a part of this current couples capacitively into the substrate and mostly flows toward the nearest substrate contacts. However, that work has not addressed the conditions that determine the dominant mechanism of the substrate noise generation. We will demonstrate further in this paper that there are other noise generation mechanisms, and that the dominance of one or the other of these mechanisms highly depends on the size of the digital circuit and on the external parasitics. The benefits of technology scaling have been exploited for decades in order to design high-performance and low-power digital circuits. The future projection of the substrate noise has usually been addressed with a focus on the efficiency of the layout-level techniques [5] or on

0-7803-8495-4/04/$20.0002004 IEEE.

the efficiency of decoupling [6] in the substrate noise reduction. In this paper, we predict the scaling of the substrate noise using the ITRS2002 [7] roadmap parameters with a focus on the significance of the generation mechanisms and with a focus on the efficiency of low-noise digital design techniques. The paper is organized as follows. In section 2 we compare the different substrate noise generation mechanisms. In section 3 we present the dominant one, namely the power-supply-line coupling. In section 4 we analyze the evolution of substrate noise using the ITRS roadmap. In section 5 conclusions are drawn.

2. Substrate noise generation mechanisms The sources of substrate noise can be grouped into three major injection mechanisms: (1) impact ionization, (2) source/drain-capacitive coupling, and (3) powersupply-line coupling (see Fig. 1).

"-.

Fig. 1: Three substrate-noise coupling mechanisms in an inverter: (lfimpact ionization, (2) source/dr&-capaciHve coupling, and (3) power-supply-line coupling.

The first mechanism is the impact ionization. The hole current flowing out of the drain into the substrate due to hot-electron effects is known as the impact ionization current, which we define as i&. We define iDs(!, as the total return current picked up by the digital ground. An approximate expression for the peak value of the impact ionization current ZDf, which is related to the peak value of the total ground return current IDS, is given by [8]: 'DI

= zDS'K,'(vLJS

-vDS,SAT)ex(-

vDs

-vivDs,T

]

(1)

where Ki and V, are parameters that must be fitted empirically to measurement data. Typical values for Ki are 1 to 3 V-', and for vi, 10 to 30V. VDS,,, is the drain-source voltage. VDs,sTis the drain-source voltage at the onset of saturation. The importance of the impact ionization current decreases exponentially with technology scaling due to its exponential dependence on the voltage, and so it can be neglected. The relative comparison with the other currents will further be demonstrated in section 4. The second mechanism is the current iDB(t) injected into the bulk via the draidsource-bulk junction when the voltage at the draidsource switches. In order to compare the fraction of this current going to the backside contact

24-6-1

Authorized licensed use limited to: University of Central Florida. Downloaded on November 8, 2008 at 21:33 from IEEE Xplore. Restrictions apply.

501

VSsvia the substrate contacts. Cd is the decoupling capacitance. C, is the total circuit capacitancebetween VO, and Vss.A'C, is the switching portion of this capacitance where A is the switching activity factor of the circuit, which is typically between 0.05 and 0.30 for telecommunication circuits. AVDD(~)and AV& are the noise on the supply and the ground, respectively. We define t, as the total duration of the current charging the switching capacitance. Voo+~~Dvoo(~)

ETLOM U')

External

ia(t)

C,+(I-A)C,

Nowswitching ircuits Vss+Avss(t)

COp=A.C,

Ut)

C,=A.C, Swaching circuits

Fig. 2: The switching in a circuitwith ideal switches.

I

CflMOS) I ~ D B LRL, Technology (rise/fall) [fF] (ridfall) [m] 1.04 13.01 3.38 0.18um 1.33 10.47 171.2 bulk-&e 1.93 8.48 4.12 0.35gm 2.44 6.85 22.07 EPI-type 3.81 9.21 1.28 OSOum FPT--,-

I

4sn

I

7n4

I

760

&ABG

I

(rise/faU) 671.98 540.78 63.91 43.54 18.82 i4?9

I

Table 1: Computation of different components of the ratio Io&c for three technologies: a 0.18pm process (bulk-type) a 0.35pm and a0 . 5 0 ~ process (both EPI-type).

The reasoning and experiments for the inverter can be repeated in a similar way for other and more complex gates and the conclusions are similar. For a fixed-height standard cell library, the area and perimeter of the draintsource regions and of the oxide and overlap regions scale at the same rate as increasing the cell width for another gate, and therefore the parasitic capacitances scale at a similar rate. So the ratio ZDS/IBG does not change significantlyfrom one cell to another. From our experiments we conclude that for EPI-type substrates the ratio of the peak value of the ground return current (ZDs) is around one or two orders of magnitude larger than the peak value of the part of the capacitivecoupling-induced drain-bulk current going to a grounded backside node (Isc),while for bulk-type @ugh-ohmic) substrates the current IDS is around two or three orders magnitude larger than ZDB. This will further motivate us to ignore the bulk current in bulk-type substrates, compared to power-supply-line coupling, which is described next.

3. Power-supply-line coupling In large digital circuits, high peaks of the supply current create power-supply-line noise in the supply network due to the RLC network formed by the chip capacitance and the decoupling between VDDand VSS,the package inductance, and the series resistance in the supply connection (see Fig. 2). In a p-type substrate this supply noise couples capacitively into the substrate ftom VDD via the n-well junction capacitance, and resistively from 502

The analysis of the switching circuit in Fig. 2 gives two extreme cases that indicate which parameters to control in order to reduce power-supply noise: (1) the case when the non-switching circuits and decoupling provide most of the current required by the switching circuits, and (2) the case when the external power supply provides most of the current required by the switching circuits. The former case occurs when ( ~ , . t , ) ~ < < where 4 U,, is the resonance frequency where wo=[(Lp+LJ.(c,+CJ"", For Lp=Lg,and Rp=Rg,the ground noise value at t=tJ2: 1 A.V,,.C, AV,(r = t , 12) = -___ 2 C,+C, Eqn. (2) suggests that a smaller ratio of the switching capacitance to the non-switching capacitance in large digital circuits is useful for noise reduction. Further, reducing the inductance will not reduce the peak value of the power-supply-noise. The supply curThe latter case occurs when (~o.t,)~>>4. rent of the switching circuits is mostly supplied by the external power supply. In this case, for Lp=Lg and Rp=Rg the ground noise value at t=tJ2: 2.A.VDD.Cc.Lp(g1 AV,(t=t,/2)= (3) fcZ

In the case where eqn. (3) is applicable, reducing the supply-line inductance and increasing the switching time reduces the power-supply noise. We define iBp(t) as the power-supply-line coupling current fiom the substrate contact, which is typically connected to the ground of a digital circuit, towards the ground of a sensitive (e.g. analog) circuit is given by:

where R,, is the resistance between the well of the digital circuit and the well of an analog circuit. This equation will be used in section 4 in order to compare the powersupply-line coupling current iBp(t) to the capacitive coupling current iBc(t),which is the fiaction of the bulk current picked up by the analog ground. From this section, we conclude that increasing the decoupling always helps for reducing the noise generation, be it at the expense of chip area, but reducing the inductance will not be helpful for reducing the peak value of the power-supply-noise in the cases when the switching

24-6-2

Authorized licensed use limited to: University of Central Florida. Downloaded on November 8, 2008 at 21:33 from IEEE Xplore. Restrictions apply.

current is balanced by the current coming from the non-switching circuits and from the decoupling capacitance if any. Also reducing the switching time tc is only useful when the switching current is balanced by the current coming from the external power supply.

4. Effect of the ITRS technology roadmap on substrate noise

I

The semiconductor industry has employed three different scaling schemes [7]: (1) constant-voltage scaling in which dimensions are downscaled by the same factor a (>l), (2) constant-field scaling in which dimensions and voltages are downscaled by the same factor a (>1), and (3) hybrid scaling in which dimensions and voltages are scaled down differently, namely by a (>I) and p (>l), respectively. In fact, hybrid scaling is a more general case of constant-field scaling where a=P. The pad pitch is downscaled by 5(>1) in order to accommodate the scaling on the values of the bondwire inductance. The relation between the substrate doping and scaling has initially been introduced in [lo]. In order to reduce the depletion region width by a factor a, the substratelwell doping should be increased with a factor &@ under hybrid scaling and with a factor & under constant-voltage regime [ IO]. Today’s technologies employ selective doping such as p-wells in a p-type substrate, rather than changing the whole doping of the substrate. Therefore, the resistivity &,b of the wafer is a given parameter by the wafer manufacturer and it does not change with scaling. In order to evaluate how scaling affects the drain current of a transistor, we assume that a transistor of a switching gate stays in velocity saturation (usually true for ultra deep submicron devices) for the entire duration of the transition. For short-channel devices the saturation current IDSAT is given by:

(5) = ~,,.C,, .W.(VGS - VT - V D S , S A T ) where usat is the saturation velocity for the elecIDSAT

tronsholes. W is the width of the transistor. From this equation, we see that the drain current scales with the same factor /3 as the voltage, due to the direct multiplication of Cox(scales with a),W (scales with I/a), and the supply voltage VDD (scales with l / p ) in eqn. (5). The propagation delay time of the circuit reduces by l/a. The substrate noise coupling consists of three mechanisms: impact ionization, sourceldrain capacitive coupling, and power-supply-line coupling (Fig. 1). We will discuss their scaling now. The resistance R, from the bulk node of a transistor to the substrate contact is approximately proportional to the inverse of the doping in the well (conductivity = q*doping level*mobility and mobility decreases slightly as the doping level increases). If we assume hybrid scaling, then this doping level and hence R, scales with a factor fld. On the other hand, the resistance Rsa from a bulk node of a transistor in digital circuits to the bulk of analog circuits is proportional to the resistivity ,&b of the substrate. By this, the impact ionization current normalized to the sup-

ply voltage (ZBINDD) scales with exp[c.(l-p)Jq/& under hybrid scaling. Here p indicates the scaling factor of the substrate resistivity with smaller technology nodes as a result of the resistance term R,,. The constant c (>>1) in the exponential refers to the term dependent on the variables VDD and of the reference technology node. For constant-voltage devices the scaling of the normalized impact ionization current will be slightly greater than p’d since scaling down the dimensions under constant voltage will reduce the saturation drain-source voltage (VDs,sAT) of the device. I I Scale Factor I Scale Factor I SeaIinp:variables Supply, threshold - VDb V, Pad pitch Substrate resistivity - p d Gate dimensions L, W. tm Substrate (well) doping - NA &=mb ln[(L+r)/r]

-

Dynamic power - P= I,, Leakage power

Fixed Supply Hybrid I l/b I/jI/< I/q I/o, I/a I/a d a@

I/&

gd

v auk fb-I)/m/4

Table 2: Scaling consequences on CMOS circuits.

The increase of the well doping also increases the junction capacitance per unit area or perimeter with a scaling factor &@I2 for an abrupt junction. Here we have assumed that the voltages scale down significantly such that the voltage dependence of the junction capacitance can be ignored. The overall junction capacitance scales down by I/(a.@”) considering the scaling of the bottom-plate area ( 1 / 4 . As a result, the normalized will sourceldrain capacitive coupling current (ZB#DD) scale by p.@’2/d(hybrid scaling). The die area downscales with & while the pad pitch area downscales with 8.In this case, the number of pads that can be put in the array packages scale with d/8 when the design is pad-limited. The inductance term (Lp, Lg) also scales with d/$. Pad-limited designs are more likely to exist in the future since the design productivity does not improve as fast as the geometric shrinking. The normalized power-suppy-line-coupling current ZBPNDI) scales either with dp’(2.D for small circuits (4OK-gates) or with p for large circuits (>1OK-gates). The condition on which scaling to use is found by checking the constraints given in the network of Fig. 2. These results show that the power-supply-line coupling be-

24-6-3

Authorized licensed use limited to: University of Central Florida. Downloaded on November 8, 2008 at 21:33 from IEEE Xplore. Restrictions apply.

503

comes a severe problem in the future while the capacitive coupling loses its importance due to the increase of the p-well doping. Table 2 summarizes the impact of technology scaling on the mechanisms of substrate noise generation for the two scaling regimes. The other scaling effects on the speed, the area, and the power are also given in the table. Fig. 3a shows the effect of scaling on the normalized substrate noise components generated by a circuit consisting of 1000 minimum-sized gates using the ITRS2002 roadmap parameters. In the figure, there are three normalized substrate noise components: 1) normalized impact ionization current (ZBI/VDD), 2) normalized sourceldrain-capacitive-coupling current (IB&'DD), and 3 ) normalized power-supply-line coupling current (L(di/dt)/sflDD or Z B p N D D ) . In fact, the last term is computed in two ways, the one using the traditional formula Ldi/dt and the other by simulating the equivalent network given by Fig. 2. During the simulations for every technology node the inductance is kept fixed at Lp(g)=O.1 nH and R,,=O.Ol C2 (a=g).However, technology scaling will increase the inductance further if one has a pad-limited design, since the bonding area (l/d does not scale down at the same rate as the chip area (I/$>. Hereby using 1000 gates is an arbitrary choice, which gives w,t,2<<4. The results will be similar for say 5M gates. It is clearly seen in Fig. 3a that the normalized power-supply-line coupling using the equivalent network does not scale with technology scaling. For this large circuit eqn. (2) is applicable. Fig. 3b shows the effect of scaling on the components of the substrate noise for a circuit with five minimum-sized gates with the same parameters. Hereby using five gates is also an arbitrary choice, which gives (wwt,)5>4. It is clearly seen that this time the normalized power-supply-line coupling noise scales at the same rate as Lpg(di/dt)/RsflDDgiven by eqn. (3). In fact, using supply-current shaping such as intentional clock skew will reduce t, [ll]. As a result of this, reducing the inductance can become much easier to achieve (w,t,)2<<4 and therefore to reduce the noise generation. From the comparison of the above results for three different types of logic in Fig. 3, we conclude that the normalized power-supply-line coupling current (in the circuit with five devices) scales up the fastest with advancing the technology node in high-performance logic due to the fact that the switching time scales up the fastest in this type of logic. On the other hand, the normalized impact ionization current downscales the slowest with advancing the technology node in low-standby-power logic due to the fact that the supply voltage downscales the slowest in this logic. All cases in the figure indicate that and source/drain capacitive impact ionization (I&'DD) coupling (IBo/V,o) can be further ignored for packaged ICs in future technology nodes.

to the capacitive coupling of the sourceldrain and due to the impact ionization current can be neglected for future technology nodes. The inductive noise (Ldildt) generated on the supply lines will be more important and the dominant mechanism in future technology nodes. When going from a 130 nm technology node to 65 nm, the ratio of the power-supply-line coupling and the supply voltage increases by a factor of three for a small switching circuit where the external power supply provides most of the current required by the switching. On the other hand, for large circuits the peak value of the power-supply-line coupling current becomes more dependent on the switching activity ratio. In such large circuits the power-supply-line coupling component is not affected by technology scaling and can only be reduced by adding more decoupling andor decreasing the dynamic power consumption.

frT&qf

FnaO. Msh-rlth

F.aaddmm+d67wpnloll0mn&

La

*-

930 ""Im

qcuaYv&d

0-

Fig. 3: Effect of scaling on the substratenoise componentsin a

circuitwith (a) 1000 and (b) 5 minimum-sized gates using the ITRS2002 Darameters.Values are normalizedto the 130nm technology node.

References S. Donnay and G. Gielen, editors, 'Substrate noise coupling in mixed-signal IC's,"Wwer Academic Publishers, 2003. J. Briaire and K.S. Krisch, "Principlesof substrate crosstalk generation in CMOS circuits,' /E€€ TCAD, vol. 19, no. 6, pp. 645653, June 2000. R. Senthinathan and J.L. Prince, "Simultaneousswitchingground noise calculation for packaged CMOS devices," E€€JSSC. Vo1.26, No.11, pp. 1724-1728, Nov. 1991. M. Nagata et al., "Physical design guides for substrate noise reduction in cmos digital circuits,"/€€E JSSC, vol. 36, no. 3, pp. 539449,2001. X. Aragones et al., "Substrate coupling trends in future CMOS technologies,"Proc. PATMOS, pp. 235244, Sept. 1997. P. Larsson, "Powersupply noise in future IC's: a crystal ball reading,"in / € € € P m . CICC, pp. 467474,1999. ITRS 2002 Edition - httpl/pub/ic.ilrs.net. K. Sakui et al., T h e effects of impact ionization on the operation of neighboring devices and circuits," /E€€ Tr. Electron Devices, Vol. 41, No. 9, pp. 1603-1607, Sept. 1994. Substratestormtool from Cadence: http:/%vww.cadence.com. R.H. Dennard et al., "Design of ion-implanted MOSFETs with very small physical dimensions,' /€€E JSSC, vol. 9, No. 5, pp. 256-268, 1974. M. Badaroglu et al., 'Modeling and experimental verification of substrate noise generation in a 22OKGates WIAN system-on-chip with multiplesupplies,"/€E€ JSSC, Vol. 38, No. 7, pp. 1250-1260,2003.

5. Conclusions We have analyzed the dominant component in substrate noise generation and its evolution with CMOS technology scaling. We have shown that the substrate noise due 504

-pout0

24-6-4

Authorized licensed use limited to: University of Central Florida. Downloaded on November 8, 2008 at 21:33 from IEEE Xplore. Restrictions apply.