#evolution Of Substrate Noise Generation Mechanisms With Cmos Technology Scaling

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Evolution of Substrate Noise Generation Mechanisms With CMOS Technology Scaling Mustafa Badaroglu, Member, IEEE, Piet Wambacq, Member, IEEE, Geert Van der Plas, Member, IEEE, Stéphane Donnay, Member, IEEE, Georges G. E. Gielen, Fellow, IEEE, and Hugo J. De Man, Fellow, IEEE

Abstract—Substrate noise is a major obstacle for single-chip integration of mixed-signal systems. To reduce this problem and to assess its evolution with CMOS technology scaling, the different mechanisms that generate substrate noise and their dependencies on different parameters need to be well understood. In this paper, we show that with downscaling of the technology, substrate noise due to supply coupling becomes the dominant coupling mechanism when the chip substrate is directly biased with the digital ground. With Kelvin ground substrate biasing on the other hand, source/drain capacitive coupling becomes the dominant coupling mechanism. Further, we show that with downscaling, the peak value of the supply coupling noise component becomes more dependent on the relative ratio of the switching capacitance to the nonswitching capacitance, which is formed by the circuit decoupling and the nonswitching circuit elements, rather than the Ldi/dt noise. These insights illustrated in a quantitative framework are believed to be very useful for the systematic use of digital low-noise design techniques in future CMOS technologies. Index Terms—Circuit analysis, deep submicron, International Technology Roadmap for Semiconductors (ITRS), low-noise design, mixed analog–digital integrated circuits (ICs), substrate noise, supply noise, technology scaling.

I. INTRODUCTION

S

UBSTRATE noise is a major obstacle for single-chip integration of mixed-signal systems [1]. The previous publications have mostly analyzed the substrate noise generation mechanisms individually and have compared them only experimentally to each other in an effort to find the dominant mechanism without looking at the boundary conditions determining their dominance [2], [3]. These publications only considered small or fixed-size circuits such as I/O buffers [4]. However, the size constraints of digital circuits together with external (package) parasitics define the boundary conditions for substrate noise generation and determine which mechanism dominates in practice. This is important for a designer to choose the most efficient technique to reduce the substrate noise generation. For example, general practice suggests that reducing the

Manuscript received June 7, 2004; revised April 26, 2005. This paper was recommended by Associate Editor M. Stan. M. Badaroglu is with the IMEC, B-3001 Leuven, Belgium (e-mail: [email protected]). P. Wambacq is with the IMEC, B-3001 Leuven, Belgium, and also with Vrije Universiteit Brussel, 1050 Brussels, Belgium. G. Van der Plas and S. Donnay are with the IMEC, B-3001 Leuven, Belgium. G. G. E. Gielen is with the Katholieke Universiteit Leuven, B-3001 Leuven, Belgium. H. J. De Man is with the IMEC, B-3001 Leuven, Belgium, and also with the Katholieke Universiteit Leuven, B-3001 Leuven, Belgium. Digital Object Identifier 10.1109/TCSI.2005.856049

Fig. 1. Three substrate noise coupling mechanisms in an inverter. (1) Impact ionization. (2) S/D coupling. (3) Supply coupling.

parasitic inductance will reduce substrate noise. However, for a large circuit a reduction of the inductance does not necessarily reduce the peak value of the substrate noise voltage [5]. If this is the case, the only ways to reduce the peak value of the substrate noise voltage are to increase the decoupling and/or to increase the isolation of the substrate. The work in [5] and [6] presents an effective use of low-noise digital design techniques by addressing that most of the supply impedance goes through the gate and current via the its load, while a part of this current capacitively couples into the substrate. However, that work has not addressed the conditions that determine the dominant noise injection mechanism. We will demonstrate that there are other noise generation mechanisms, and that the dominance of one of these mechanisms highly depends on the circuit size, on the method of substrate biasing, and on the external parasitics. In this paper, such boundary conditions are derived to find the dominant coupling mechanism. Technology scaling has been exploited in order to design high-performance and low-power digital circuits. The future projection of the substrate noise has usually been addressed with a focus on the efficiency of decoupling [7] or layout-level techniques [8]. In this paper, we predict the scaling of substrate noise using the International Technology Roadmap for Semiconductors (ITRS) 2004 [9] roadmap parameters with a focus on the significance of the generation mechanisms in the light of low-noise design techniques [10]. It is shown that the supply coupling becomes more severe in future technology nodes when the substrate is directly biased with the digital ground while the source/drain (S/D) capacitive coupling loses importance. With Kelvin ground biasing of the substrate, the S/D coupling is more dominant. The paper is organized as follows. Section II describes the mechanisms that cause substrate noise (illustrated for an inverter in Fig. 1): 1) impact ionization; 2) S/D coupling; and 3) supply

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297

TABLE I DESCRIPTION OF VARIABLES

Fig. 2. Schematic flow of the substrate currents in and around a digital gate, and an analog circuit on the same die.

Fig. 3. Equivalent resistive substrate network configurations for: (a) substrates with a grounded backside node, (b) bulk-type substrate with a floating backside node, and (c) EPI-type substrate with a floating backside node. Depending on the technology used, the proper configuration has to be inserted in Fig. 2.

coupling. Section III presents an analysis to determine the dominant injection mechanism. Section IV analyzes the future evolution of substrate noise as a function of the ITRS 2004 roadmap parameters. Section V provides conclusions. II. SUBSTRATE NOISE INJECTION MECHANISMS The flow of the generated substrate currents in and around a digital gate is shown in Fig. 2, while the different resistive substrate network configurations that depend on the type of substrate are shown in Fig. 3, with a description of all variables in Table I. The resistances are computed analytically [2], [11] or using an extraction tool [12]. The capacitances are computed using the SPICE parameters and the geometry data. The package parasitics are extracted from measurements. For the sake of simplicity in comparison, we assume that the injection mechanisms are mutually exclusive. That is, when the noise is injected into the bulk via the S/D junction capacitance, neither supply noise nor impact ionization exists, or vice versa. (similarly for ) is given as the In fact, the current sum of different injection mechanisms (1) and are the parts of the curwhere due to impact ionization, S/D coupling, and supply rent coupling, respectively. For the sake of quantitative comparison of the currents, we use the peak values of the time-varying currents although these peaks do not necessarily happen at the same time. In this paper we represent the peak value of the time-do, while we represent the dc main currents by the notation

values by uppercase symbol with no time argument. In addition, whenever it is necessary, we also discuss the power of these time-varying signals. We now consider the three injection mechanisms. A. Impact Ionization The hole current flowing out of the drain into the substrate due to hot-electron effects is known as impact ionization current . An approximate expression for the impact ionization , which is related to the total ground return current current , is given by [13]

(2) and are parameters that must be fitted empirically where are 1 to 3 V , and to measurement data. Typical values for is the drain-source voltage. for 10 to 30 V. is the drain-source voltage at the onset of saturation. is given by [14] (3) is the critical electrical field at which the mobility of where is the effective the carriers (electrons/holes) saturates. length of an nMOS (pMOS) transistor. As an illustration, we consider an nMOS device with m, V, V, V/ m, V , and V. Using (2) we find that the current is several orders of magnitude smaller than the current (Fig. 4) at = . At this point,

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Fig. 4. The [i (t)] =[i 1.8 V CMOS process with V

(t)] ratio for an nMOS device in a 0.18 m = 1:8 V.

the current in a switching digital circuit becomes maximum. In some other operating points, on the other hand, ratio is only around 100, but the the absolute values are negligibly small at these operating points. The measurements described in [3] are in line with these conclusions.

is the sum of the oxide capacitances of the fanout where logic and the interconnect capacitance seen at the output of the is the sum of all capacitances of the switching gate. switching gate, which need to be charged by the gate itself. Note also contains . that current injected from the junction splits into The represents the part taken away via the three parts: substrate contacts, whereas is the part that is picked up is the part by the sensitive analog circuit (Fig. 2), and that is picked up by the backside contact if grounded. We typisince the analog well is cally have placed far away from the digital well and also the well doping is order(s) of magnitude larger than the substrate doping. For a far away analog circuit we also have since the vertical resistance from the digital bulk to the backside node is much lower than the lateral resistance. Using the approximations above and using the networks in Fig. 3, the value is found for the following cases. • For substrates with a grounded backside node [Fig. 3(a)]

(6) B. S/D Capacitive Coupling Due to the pn-junctions between the S/D regions of the transistors and the substrate/well, switching noise is injected into the substrate during switching of a S/D node (current in Fig. 2). The unit area/perimeter capacitance of such a junction is given in [15] (4) where is the built-in junction voltage. and are the doping levels of the substrate/well (p-type) and the drain/source (nMOS) regions, respectively. is the junction grading exponent. is the magnitude of unit electronic charge ( C). is the permittivity of silicon ( F/cm). Furis the junction reverse-bias voltage. The total capacither, tance consists of the bottom-plate and sidewall components, the latter ones being negligible in modern processes that use shallow trench isolation (STI). ratio for a digWe now compute the ital gate. By assuming that the time constants of the load and of the junction capacitances are equal, we can neglect the time dependence of the ratio. We also assume that all drain nodes in the gate switch at the same time. With these assumptions, the ratio is given by the ratio of the load to the drain junction capacitances of the nMOS transistor. Note that the effect from the pMOS is neglected due to the shielding ratio is defined by by the n-well. The (5)

• For bulk-type substrates with a floating backside node [Fig. 3(b)] (7) • For EPI-type substrates with a floating backside node [Fig. 3(c)], see (8) at the bottom of the page. Similarly, the current picked up by a backside ground contact yields a conservative bound for the current leaving the well. Here, we consider a hypothetical analog circuit where we assume that its sensitive local bulk node is shorted to this ground plane and that no other analog substrate contact exists. In this case, we find for both EPI-and bulk-type substrates

(9) The resistance between the bulk underneath the drain and a square-shaped substrate contact with an edge size within the p-well and separated by a distance is given by [11]

(10) where we typically have . the resistivity of the p-well (typically 100 m cm) and contact (typically 1 m). the thickness of the

is is

(8)

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299

TABLE II COMPUTATION OF DIFFERENT COMPONENTS OF [i (t)] =[i (t)] RATIO (K ) FOR THREE TECHNOLOGIES: A 0.18-m PROCESS (BULK-TYPE), A 0.35-m AND A 0.50-m PROCESS (BOTH EPI-TYPE)

The resistance between two square p-wells with an edge size and with a separation on a bulktype substrate is given by [11] when Fig. 5. Layout and extracted substrate resistances for the nMOS device of the inverter in a 0.18-m 1.8-V CMOS process on a bulk-type substrate.

2D case when

3D case

(11)

. and where we typically have are the thickness values of the substrate and of the well, is the resistivity of the substrate (typically respectively. on bulk-type sub10 cm). For the calculation of strates, the 2-D case is applicable when analog circuits are assumed to be placed far from digital circuits with a distance larger – m). than the thickness of the substrate ( Table II lists the values computed for the load capacitances ratio for the CMOS inverter and the in several technologies: 0.18-, 0.35-, and 0.50 m CMOS. The backside contact is grounded. Each inverter drives another identical inverter. For the 0.18- m inverter, the layout and the extracted substrate parameters are shown in Fig. 5. The ratio for the 0.18 m inverter is the higher than for the 0.35 m and 0.50 m inverters due to two reasons: (1) higher resistivity of the bulk-type substrate, and (2) larger values due to a smaller S/D area due to 45 degree poly lines and STI (which reduces the drain-bulk capacitances). Similar analysis for other standard cells has shown that the resistive division from (6) and (7) has about the same value as a result of using a fixed-height standard cell library where the substrate contact area is proportional to the width of the standard cell. From the results of Table II, we conclude that the value is at least an order of magnitude larger than the value. On the other hand, these conclusions are not enough to decide that S/D coupling is not a dominant injection mechanism. Therefore, we first need to know the injection mechanism due to the supply coupling. This will be described in the next section. Then, in Section III, we present a quantitative framework that uses these results for finding which noise injection mechanism actually dominates under the size constraints of the circuit together with external (package) parasitics.

Fig. 6. Illustration of switching in a circuit with ideal switches.

C. Supply Coupling In digital circuits, high peaks of the supply current of the switching gates create supply noise in the supply network (Fig. 6). In a p-type substrate this supply noise couples cavia the n-well junction pacitively into the substrate from via the substrate contacts. capacitance, and resistively from The supply noise consists of two parts: common-mode (CM) and differential-mode (DM) noise [16]. CM noise is caused by the imbalance between supply current and ground return current when a circuit is driven by input signal(s) referenced to power region(s) different from the one of this circuit. DM noise is caused by the oscillations of the damped LC tank formed between the circuit capacitance and the supply parasitics. For a digital circuit of practical size, the portion of gates driven by input(s) referenced to different power regions is substantially low. Also the combinations of rising/falling transitions at the input(s) have a canceling effect on the CM noise, which is not the case for the DM noise. From now on, we assume that the supply noise only consists of DM noise. The amount of DM supply noise oscillations is found by analyzing the network shown in Fig. 6. In this network the equiva, which is the lent switching capacitance is represented by average (dis)charged capacitance of the switching gates. Here the term is the switching activity factor that is defined as the ratio of the equivalent switching circuit capacitance to the total . The term is typically between circuit capacitance and . We define the equivalent nonswitching capacitance of

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the circuit , which is the average capacitance of the nonswitching gates. In addition, the decoupling capacitance is a part of the equivalent nonswitching capacitance beand . We define as the total duration of the tween current charging the switching capacitance. This current is indiin Fig. 6. We assume that this current is a triancated as gular waveform with equal rise/fall times. The current coming from the external power supply and from the nonswitching caand , respectively, in pacitances are indicated as Fig. 6. There are two extreme cases that indicate which parameters to control in order to reduce the supply noise: (1) the case when the nonswitching capacitance provides most of the current required by the switching circuits, and (2) the case when the external power supply provides most of the current required by the switching circuits. where is The first case occurs when the resonance frequency where . We have in the comparison since the specis determined by tral bandwidth of the switching current either the rise or fall time, which is half of the total duration . We define the voltage transients and as the bounces on the ground and the positive supply rail, respectively, measured on the die, referred to the external power , and supply, which is assumed to be clean. For , the ground bounce value at

From Section II.A, it was concluded that the impact ionization mechanism can be neglected. The dominance of supply coupling versus S/D coupling will now be judged by comparing (7) and (14). For the sake of brevity, here we consider bulk-type substrates with a floating backside node. We will now describe the scaling of the currents . For the part we with the number of gates need to scale the resistance of a unit gate with due to many parallel resistive the total number of gates paths from the digital substrate contacts (that are connected to that models the total ground a single voltage source bounce in the system). For the part, we need to value with the total number of switching scale the . On the other hand, we do not scale the resisgates tances since for each gate the junction-related noise is injected from an individual source, which is the switching node of the circuit. We also ignore the contribution of the impedance from the substrate contact(s) to the off-chip ground on the overall impedance from the bulk node to the off-chip ground. After this scaling procedure, the supply coupling current is dominant if the following condition is satisfied:

(12)

(15)

Equation (12) suggests that a smaller ratio of the switching capacitance to the nonswitching capacitance is useful for noise reduction. . The supply The second case occurs when current of the switching circuits is now mostly supplied from the and , external power supply. In this case, for we have

where

for each gate. If the relation cable for find the

holds, then (13) is appli. By combining (13) and (15), we ratio

(13) (16) In the case where (13) is applicable, reducing the inductance and increasing the switching time has a first-order effect on reducing the supply noise [17]. current injected from the substrate contact, The which is typically connected to the ground of a digital circuit, flows toward the ground of an analog circuit. The part of the current that is picked up by the analog circuit due to the supply-cou. The value is given by pling mechanism is

Equation (16) states that using a package with a smaller inductance and/or decreasing will reduce the ratio. On the other hand, if the reholds, then (12) is applicable for lation . In this case, the ratio becomes

(14) where

is given by (11). For .

, we have

III. ANALYSIS OF DOMINANT MECHANISM IN SUBSTRATE NOISE GENERATION In the previous sections, the peak values of the currents that arise from the two major mechanisms of substrate noise injection (supply coupling and S/D coupling) have been derived.

(17) ratio Equation (17) states that the since increasing will increase does not change with at the same rate, therefore resulting in no change in the overall in a system, initially the ratio. Therefore, if we increase ratio increases with due to (16), then the ratio starts to level off as a result of the transition from

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(16) to (17) since with increasing values of , the term increases and exceeds the term . Important for substrate noise coupling is also the way in which the substrate is connected to the ground. The dedicated bias for the well, the so-called Kelvin grounding (KG), is an effective technique for avoiding the coupling of supply noise into the substrate at the expense of an increase in cell area and a reduction of decoupling capacitance. The latter is due to the fact that the well capacitance would otherwise have added to the decoupling capacitance. A reduction of decoupling increases the ground bounce in the system but the shielding between the substrate and the noisy ground rail is now better than without KG. In this case, the S/D coupling can become a dominant substrate noise injection mechanism if the following condition is satisfied:

301

Fig. 7. Effect of GR on (a) supply coupling and (b) S/D coupling.

where

(18) where is the resistance between the bulk and the is the parasitic capacitance beKelvin ground, and is tween the digital ground and the bulk. Here, the term defined as the factor of reduction of the supply coupling as a result of KG. When we have , we have . In addition, the Kelvin ground should be well separated from the digital ground to avoid capacitive coupling between these rails. In 0.18 m CMOS for a ground rail (in Metal 1) with a length of 2.0 m and a width of 0.96 m, is 0.39 fF. For a similar geomthe extracted value of is typically etry in a gate with a width of 2.0 m, in the order of a few tens of k . For instance, if for each gate in fF and a circuit we have k , then this circuit should have a resonance frequency less than 7.95 GHz in order to make KG effective. Guard rings (GRs) can also reduce the substrate noise coupling. On the other hand, the GR grounding should be properly done, otherwise, GR could act as a highway for the noise to propagate into the sensitive circuits. The use of GR grounding for the isolation of supply coupling is illustrated in Fig. 7(a). GR, the path passing through the In the case of a grounded GR node is shorted to ground with the GR ground impedance. resistance remains, hence supply couOnly the pling is reduced since where is the resistance between the digital well and the analog well before the introduction of a GR. Similar conclusions are derived for S/D coupling by means of Fig. 7(b). For instance, in [18], the authors show that properly grounding the GR reduces the spurious components in the measured output spectrum of a VCO by 75 dB below the VCO frequency at 3.5 GHz. Note that noise levels that degrade the performance of the analog circuit depend on the transfer function from sensitive substrate node(s) of that analog circuit to its output. The guard-ring impedance requirements become more difficult in a mixed-signal system with a large digital circuit. These requirements bring the need for a wider GR using extra silicon area and

Fig. 8. [i (t)] =[i (t)] ratio (from SPICE simulations) as a function of the number of gates (Lp(g ) = 1 nH and A = 0:15) for two CMOS processes with a grounded backside plane: 0.18 m on a bulk-type substrate and 0.35 m on an EPI-type substrate.

for extra I/O pins providing a low-impedance (clean) ground biasing GR [19]. ratio The derived formulas for the ratio with the are also valid for the only difference that the factor should be added in (16) to (18). This factor is not dependent on technology scaling. Here, we consider a hypothetical analog circuit where its sensitive local bulk node is shorted to the backside ground plane and that no other analog substrate contact exists. From now on we will ratio for the simulations use the presented in this section, but remember that it is proportional to ratio. the Fig. 8 demonstrates the ratio (by SPICE simulations) for two CMOS processes: (1) 0.18 m on a bulk-type substrate, and (2) 0.35 m on an EPI-type substrate. In the figure the ratio is shown as a function of the number of pH and for a unloaded inverters with grounded backside plane and with the substrate directly biased by the digital ground. The simulated netlist also contains the substrate network extracted using the tool in [12]. Note that for the values used, the saturated ratio is lower for the 0.35 m EPI-type substrate than for the 0.18 m bulk-type substrate. In fact, the ratio can be much higher in reality since the output of simultaneously switching gates can be either falling or rising when they are switching simultaneously (rather than switching all in the same direction

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K gates) when the chip substrate is directly biased with the ( digital ground. With KG the S/D coupling current becomes the dominant injection mechanism. In the next section we describe the impact of technology scaling on the significance of the injection mechanisms in the light of the efficiency of low-noise digital design techniques. IV. EFFECT OF THE ITRS TECHNOLOGY ROADMAP ON SUBSTRATE NOISE

Fig. 9. The [i (t)] and [i (t)] values as a function of the inductance with the number of inverters as a parameter and with activity factor A = 0:30.

as assumed in Fig. 8). This will create a significant reduction on the current but not on the current . In addition, the value is much larger than the value since the current consists of damped oscillations while the current is a short triangular waveform. We conclude that the supply-coupling current is always dominant above a certain circuit size ((16)) regardless of which substrate type is used. However, it is more dominant in high-ohmic substrates than in EPI-type substrates. This conclusion can also be reached by comparing the saturation values of the ratio (Fig. 8). These results are now verified by SPICE simulations for several circuits of different sizes in a 0.18 m 1.8 V CMOS process on a bulk-type substrate. The netlist also contains the substrate network extracted using the tool in [12]. Fig. 9 shows the and values as a function of the inductance with the number of unloaded inverters as parameter. The parameters and the layout of each inverter are shown in Fig. 5. Each circuit has a switching activity factor of . The values have a dependency on but the values do not. For each circuit, the value is linearly dependent on below a certain inductance value. On the other hand, reducing is always better for a reduction of the RMS value as a result of more damping. Above this value the peak value of the transients is not dependent on . We call this inductance value as the corner value of for the circuit where each value has been indicated with a circle in Fig. 9. Above the corner value, the value is determined by the circuit size , the switching activity factor , and the substrate (15). Below the corner value, the value decreases linearly with until the substrate noise is dominated by . For example, for the circuit with 5K inverters, the substrate noise is dominated by for inductance values below 2 pH. In a circuit where S/D coupling is the dominant mechanism, substrate noise can be reduced by increasing the number of substrate contacts, by increasing the isolation of the substrate, and by balancing the amount of rising and falling transitions at a given time instant. From this section we conclude that the supply coupling is the dominant injection mechanism for circuits of practical size

In the technology nodes below 0.13 m, subthreshold leakage current becomes an important limitation for further downscaling of the threshold voltages with the supply voltage when the geometric dimensions scale down. For this reason, the semiconductor industry today uses different scaling schemes for the dimensions and the voltage [9], namely by scaling factors and , respectively. The inductance is scaled down in order to accommodate the scaling of the package by inductance. In this section we describe the consequences of this scaling on the generation mechanisms of substrate noise. The relation between substrate doping and scaling has initially been introduced in [20]. In order to reduce the depletion region width by a factor , the channel doping should be in[20]. In this case, the substrate/well creased with a factor doping concentration should also be increased in order to avoid bulk punchthrough [21]. Today’s technologies employ selective doping such as p-wells in a p-type substrate, rather than changing the whole doping of the substrate. Therefore, the wafer is a given parameter by the wafer manufacturer resistivity and it does not change with scaling. We will now discuss the scaling of the substrate noise injection mechanisms: impact ionization, S/D coupling, and supply from the bulk coupling (Fig. 1). The resistance node of a transistor to the substrate contact (Fig. 2) is approximately proportional to the inverse of the well doping. Therefore, scales with a factor the doping level and hence . On the other hand, the resistance from a bulk node of a transistor in digital circuits to the bulk of analog cirof the substrate. The cuits is proportional to the resistivity is considered here due to the fact that a resistance similar equation holds for the part of the impact ionization curaffecting analog circuits: rent (19) value scales with By this, the (by using (2) and (19)). Here indicates the scaling factor of the substrate resistivity. The constant in the exponential refers to the term dependent on the variables and ((2)) of the technology node used as reference for scaling. The increase of the well doping also increases the junction capacitance per unit area/perimeter with a scaling factor of (from (4) for an abrupt junction ). The voltage dependence of the junction capacitance can be ignored due to low supply voltages. The overall junction capacitance scales down considering the scaling of the bottom-plate area by . As a result, the normalized peak value of the S/D coupling current will scale by .

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TABLE III SCALING CONSEQUENCES ON CMOS CIRCUITS AND MECHANISMS OF SUBSTRATE NOISE GENERATION

ON

The normalized peak value of the supply coupling current scales either with for small circuits ( K-gates) or with for large circuits ( K-gates). These results show that without KG supply coupling becomes a severe problem in future technology nodes while S/D coupling loses its importance due to the increase of the well doping. Table III summarizes the impact of technology scaling on the mechanisms of substrate noise generation. Technology scaling has a significant impact on the efficiency of KG where its efficiency is judged by the factor ((18)). When we have , the factor scales with , due to the direct multiplication of the terms (scales with ), (scales with , and (scales with ). Here, is a scaling factor in order to accommodate the scaling of the dielectric constant between the metal and the bulk. The term for is used in order to scale down the width of the power rail as a result of decrease in the peak current of each switching gate. It can be concluded that KG becomes more effective with technology scaling. Contrary to KG, the technology scaling does not have a significant impact on the use of GRs since the efficiency of a GR is only dependent on the substrate resistivity when the

303

TABLE IV EFFECT OF ITRS 2004 SCALING ON SUBSTRATE NOISE COMPONENTS FOR A CIRCUIT WITH 10 K (LEFT) AND 5 (RIGHT) TWO-INPUT NAND GATES (W = 10 L AND FANOUT = 3). FOR EACH COMPONENT, THE TABLE SHOWS RELATIVE FACTORS OF CHANGE WITH RESPECT TO HIGH-PERFORMANCE LOGIC IN 90 nm. EACH COMPONENT IS NORMALIZED TO THE SUPPLY VOLTAGE OF THE TECHNOLOGY NODE

grounding is properly done. On the other hand, technology scaling brings requirements for the number of ground bumps used for the GR. When supply coupling is the dominant mechanism, the resonance frequency of the supply determines this number. In this case, the number of ground bumps should scale with . When S/D coupling is the dominant mechanism, the switching time of the gates determines this number. In this case, the number of ground bumps should scale with . Next, we will illustrate this evolution using the ITRS 2004 roadmap parameters [9]. Table IV shows the effect of scaling on the normalized substrate noise components for 10 K (left) and 5 (right) two-input NAND gates . Each circuit has an activity factor . Each NAND gate drives a load equivalent to three times its input capacitance. For each technology node the noise components were computed using the formulas defined in Table III and the ITRS 2004 parameters. In Table IV there are three normalized substrate noise components: 1) impact ionization current, 2) S/D coupling current, and 3) supply coupling current without/with KG. The last term is computed in two ways, the one using the traditional formula Ldi/dt and the other simulating the network in Fig. 6. During the simulations for every technology node, the package parasitics are kept fixed at nH and the substrate resistivity does not change with scaling . Using 10 K and 5 NAND gates during the simulation is an arbitrary choice. Using 10 K gates gives while using 5 gates gives . The results for 10 K gates are similar for say 5 M NAND gates with the same inductance since for 5 M NAND gates we still have . With the choice

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of these two extreme cases, the conclusions from these simulations can be generalized for other circuits. We hereby demonstrate a worst-case situation for S/D coupling where all gates are switching in the same direction. During the simulations we consider a practical system where each gate and its input(s) are referenced to a single power region. Therefore, the supply noise only consists of DM noise. Similar conclusions can also be derived when we consider the CM noise [16]. For all cases in the simulation the significance of impact ionization decreases substantially. Therefore, it can be ignored. It scales down the slowest in low-standby-power logic due to the fact that the supply voltage scales down the slowest in this logic. For 10 K gates with no KG, the supply coupling computed using the equivalent network given by Fig. 6 does not scale with technology scaling. On the other hand, for 5 gates with no KG, the supply coupling scales at the same rate as (di/dt)/ given by (13). The rate of scaling is the fastest in high-performance logic due to the fact that the switching time scales down the fastest in this logic. In both cases the supply coupling dominates the S/D coupling. When we use KG, the situation reverses, i.e., the supply coupling scales down much faster than the S/D coupling. This means that the S/D coupling continues to be the dominant injection mechanism (if for the current technology we achieve to reduce the supply-coupling by means of KG). Fast downscaling of the supply coupling is due to downscaling of the metal-bulk parasitic capacitance of each gate despite the fact that the resonance frequency increases with technology scaling. But the impact of the decreasing capacitance is much faster than the impact of the increasing resonance frequency. This capacitance decreases since with technology scaling the metal-bulk dielectric material improves and the geometric dimensions of the power rail of each gate scale down. V. CONCLUSION In this paper we have analyzed the different generation mechanisms of substrate noise under the size constraints of the circuit together with external (package) parasitics and depending on the substrate grounding. We have also analyzed their evolution with ITRS 2004 roadmap. By knowing the significance of all injections, a designer can choose the most efficient low-noise design technique for enabling the integration of mixed-signal systems in future CMOS technologies. The supply coupling will become an even more dominant mechanism in future technology nodes when the substrate is directly biased with the digital ground. The relative ratio of the supply coupling current to the supply voltage will increase 4.5 x when a circuit is fabricated in a 22 nm technology node compared to a 90 nm realization with the same package. This increase happens for circuits having their supply resonance frequency larger than the inverse of their switching time. Otherwise, the peak value of the supply coupling becomes dependent on the switching activity factor and not on the technology scaling. The latter case is likely to dominate in future technology nodes. In this case, supply coupling can only be reduced by adding more decoupling, by shaping the supply current, and/or by reducing switching activity. The use of KG can eliminate the dominance of supply coupling but at the expense of an increase in the ground bounce

and an increase in die area. With technology scaling KG becomes more effective. With proper KG, the S/D coupling will become the dominant noise injection mechanism. In this case, substrate noise can be reduced by increasing the number of substrate contacts, by using a high-ohmic substrate, and by employing GRs. For GRs the grounding should be properly done, otherwise the GR could act as a highway for the noise to propagate into the sensitive circuits. Technology scaling increases the required number of bumps used for grounding the GR, but otherwise does not change the efficiency of a GR. For all cases the significance of impact ionization can be ignored. REFERENCES [1] S. Donnay and G. Gielen, Eds., Substrate Noise Coupling in MixedSignal ASICs. Norwell, MA: Kluwer, 2003. [2] D. K. Su, M. J. Loinaz, S. Masui, and B. A. Wooley, “Experimental results and modeling techniques for substrate noise in mixed-signal integrated circuits,” IEEE J. Solid-State Circuits, vol. 28, no. 4, pp. 420–430, Apr. 1993. [3] J. Briaire and K. S. Krisch, “Principles of substrate crosstalk generation in CMOS circuits,” IEEE Trans. Computer-Aided Design Integr. Circuits, vol. 19, no. 6, pp. 645–653, Jun. 2000. [4] R. Senthinathan and J. L. Prince, “Simultaneous switching ground noise calculation for packaged CMOS devices,” IEEE J. Solid-State Circuits, vol. 26, no. 11, pp. 1724–1728, Nov. 1991. [5] M. Badaroglu, M. van Heijningen, V. Gravot, J. Compiet, S. Donnay, G. Gielen, and H. De Man, “Methodology and experimental verification for substrate noise reduction in CMOS mixed-signal IC’s with synchronous digital circuits,” IEEE J. Solid-State Circuits, vol. 37, no. 11, pp. 1383–1395, Nov. 2002. [6] M. Nagata, J. Nagai, K. Hijikata, T. Morie, and A. Iwata, “Physical design guides for substrate noise reduction in CMOS digital circuits,” IEEE J. Solid-State Circuits, vol. 36, no. 3, pp. 539–549, Mar. 2001. [7] P. Larsson, “Power supply noise in future ICs: A crystal ball reading,” in Proc. IEEE Custom Integrated Circuits Conf., May 1999, pp. 467–474. [8] X. Aragones, J. L. Gonzales, and A. Rubio, “Substrate coupling trends in future CMOS technologies,” in Proc. 7th Int. Workshop on Power and Timing Modeling, Optimization and Simulation, Sep. 1997, pp. 235–244. [9] ITRS (Int. Technology Roadmap for Semiconductors) 2004 Edition (2004). [Online]. Available: http://public.itrs.net [10] M. Badaroglu, P. Wambacq, G. Van der Plas, S. Donnay, G. Gielen, and H. De Man, “Impact of technology scaling on substrate noise generation mechanisms,” in Proc. IEEE Custom Integrated Circuits Conf., Oct. 2004, pp. 501–504. [11] S. Kristiansson, S. P. Kagganti, T. Ewert, F. Ingvarson, J. Olsson, and K. O. Jeppson, “Substrate resistance modeling for noise coupling analysis,” in Proc. IEEE Int. Conf. on Microelectronic Test Structures, Mar. 2003, pp. 124–129. [12] Substrate Noise Analyst™ tool (2005). [Online]. Available: http://www. cadence.com [13] K. Sakui, S. S. Wong, and B. A. Wooley, “The effects of impact ionization on the operation of neighboring devices and circuits,” IEEE Trans. Electron Devices, vol. 41, no. 9, pp. 1603–1607, Sep. 1994. [14] BSIM3 Manual [Online]. Available: http://www-device.eecs.berkeley. edu/~bsim [15] S. M. Sze, Semiconductor Devices: Physics and Technology Second Edition. New York: Wiley, Sep. 2001. [16] M. Badaroglu, P. Wambacq, G. Van der Plas, L. Balasubramanian, K. Tiri, I. Verbauwhede, S. Donnay, G. Gielen, and H. De Man, “Digital circuit capacitance and switching analysis for ground bounce in ICs with a high-ohmic substrate,” IEEE J. Solid-State Circuits, vol. 38, no. 7, pp. 1119–1130, Jul. 2004. [17] M. Badaroglu, P. Wambacq, G. Van der Plas, S. Donnay, G. Gielen, and H. De Man, “Digital ground bounce reduction by supply current shaping and clock frequency modulation,” IEEE Trans. Computer-Aided Design Integr. Circuits, vol. 24, no. 1, pp. 65–76, Jan. 2005. [18] G. Van der Plas, C. Soens, M. Badaroglu, P. Wambacq, and S. Donnay, “Modeling and experimental verification of substrate coupling and isolation techniques in mixed-signal IC’s on a lightly-doped substrate,” in Proc. of VLSI Circuits Symp., Jun. 2005.

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[19] P. T. M. van Zeijl, J. W. Eikenbroek, P. P. Vervoort, S. Setty, J. Tangenberg, G. Shipton, E. Kooistra, I. Keekstra, and D. Belot, “A Bluetooth radio in 0.18 m CMOS,” in IEEE Int. Solid-State Circuit Conf. Dig. Tech. Papers, vol. 448, Feb. 2002, pp. 86–87. [20] R. H. Dennard, F. H. Gaensslen, V. L. Rideout, E. Bassous, and A. R. LeBlanc, “Design of ion-implanted MOSFETs with very small physical dimensions,” IEEE J. Solid-State Circuits, vol. SC-9, no. 5, pp. 256–268, Oct. 1974. [21] J. R. Pfiester, J. D. Shott, and J. D. Meindl, “Performance limits of CMOS ULSI,” IEEE J. Solid-State Circuits, vol. SC-20, no. 1, pp. 253–263, Feb. 1985.

Mustafa Badaroglu (S’00–M’05) received the B.Sc.degree from Bilkent University, Ankara, Turkey, in 1995, the M.Sc. degree from Middle East Technical University, Ankara, Turkey, in 1998, and the Ph.D. degree from Katholieke Universiteit Leuven, Leuven, Belgium, in 2004, all in electrical engineering. Since 1999, he has been with IMEC, Leuven, Belgium, where he is now a Senior Researcher. From 1996 to 1998, he was a Researcher with the Scientific and Technical Research Council of Turkey (TUBITAK), Ankara, Turkey, where he worked on design and implementation of embedded microcontrollers, digital signal processors, and several mixed-signal integrated circuits. At IMEC, he has worked on deep-submicron design automation, low-power design, and design and implementation of WLAN and UWB transceivers. His research interests include deep-submicron effects analysis/suppression, low-noise/power design, and supply/clock networks. Dr. Badaroglu was the recipient of the 2004 European Design and Automation Association (EDAA) doctoral dissertation award and of the Best Paper Award at the Design, Automation and Test Conference (DATE) in 2004.

Piet Wambacq (S’89–M’91) was born in Asse, Belgium, in 1963. He received the M.Sc. degree in electrical and mechanical engineering and the Ph.D. degree from the Katholieke Universiteit Leuven (K.U. Leuven), Leuven, Belgium, in 1986 and 1996, respectively. From 1986 to 1996, he was a Research Assistant at the ESAT-MICAS Laboratory, K.U. Leuven. Since 1996, he is with IMEC, Leuven, Belgium, working as a Principal Scientist on design methodologies for mixed-signal and RF integrated circuits. He is also a Lecturer at Vrije Universiteit Brussel, Brussels, Belgium. His research interests are design and computer-aided design of mixed-signal and RF integrated circuits. He has authored or coauthored two books and more than 100 papers in edited books, international journals, and conference proceedings. He is the co-inventor of two patents. Dr. Wambacq is an Associate Editor of the IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS. He is the co-recipient of the Best Paper Award at the Design, Automation and Test Conference (DATE) in 2002 and 2004. He regularly is a member of the Program Committees of international conferences (e.g., DATE).

Geert Van der Plas (S’01–M’03) was born in Merchtem, Belgium, in 1969. He received the M.Sc. and Ph.D. degrees from the Katholieke Universiteit Leuven (K.U. Leuven), Leuven, Belgium, in 1992 and 2001, respectively. From 1992 to 2001, he was a Research Assistant with the ESAT-MICAS Laboratory of K.U. Leuven, where he worked in the field of analog modeling and design automation. In 2002, he was appointed as a Postdoctoral Research Assistant in the same research group. Since 2003, he has been with the Design Technology Division of IMEC, Leuven, Belgium, where he is working on noise coupling in mixed-signal integrated circuits. His current research interests include deep-submicron signal integrity analysis and design of mixed-signal circuits.

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Stéphane Donnay (M’00) received the M.S. and Ph.D. degree in electrical engineering from the Katholieke Universiteit Leuven (K.U. Leuven), Leuven, Belgium in 1990 and 1998, respectively. He was a Research Assistant in the ESAT-MICAS Laboratory of K.U. Leuven from 1990 until 1996, where he worked in the field of analog and RF modeling and design automation. In 1997. he joined IMEC, where he is now a Program Director. His current research interests include circuit and system design in very deep submicron technologies, ultralow-power radios for sensor networks, system-in-a-package integration of RF front-ends and the modeling and simulation of substrate noise coupling in mixedsignal integrated circuits. He has authored or coauthored more than 100 papers in books, journals and conference proceedings. He is co-editor of Substrate Noise Coupling in Mixed-Signal ASICs (Norwood, MA: Kluwer, 2003). Dr. Donnay is a member of the Technical Program Committee of the European Solid-State Circuits Conference (ESSCIRC) since 2001. He was co-recipient of the best paper award at the Design, Automation and Test (DATE) conference in 2002 and 2004. Georges G. E. Gielen (S’87–M’02–SM’99–F’02) received the M.Sc. and Ph.D. degrees in electrical engineering from the Katholieke Universiteit Leuven (K.U. Leuven), Leuven, Belgium, in 1986 and 1990, respectively. In 1990, he was appointed as a Postdoctoral Research Assistant and Visiting Lecturer in the Department of Electrical Engineering and Computer Science, University of California, Berkeley. From 1991 to 1993, he was a Postdoctoral Research Assistant of the Belgian National Fund of Scientific Research at the ESAT Laboratory, K.U. Leuven. In 1993, he was appointed as a tenure Research Associate of the Belgian National Fund of Scientific Research and at the same time as an Assistant Professor at the K.U. Leuven. In 2000 he promoted to Full- Time professor at K.U. Leuven. His research interests are in the design of analog and mixed-signal integrated circuits, and especially in analog and mixed-signal computer-aided design tools and design automation (modeling, simulation and symbolic analysis, analog synthesis, analog layout generation, analog and mixed-signal testing). He is coordinator or partner of several (industrial) research projects in this area. He has authored or coauthored four books and more than 250 papers in edited books, international journals, and conference proceedings. He is Editor-in-Chief of the Integration Journal, and a member of the Editorial Board of the International Journal on Analog Integrated Circuits and Signal Processing. Dr. Gielen has been a regular member of the Program Committees of international conferences (DAC, ICCAD, ISCAS, DATE, CICC...). He received the 1995 Best Paper Award from the International Journal on Circuit Theory and Applications, and was the 1997 Laureate of the Belgian Royal Academy on Sciences, Literature, and Arts in the discipline of Engineering. He received the 2000 Alcatel Award from the Belgian National Fund of Scientific Research for his innovative research in telecommunications. He is a the President of the IEEE Circuits and Systems (CAS) society for the 2005–2006 term. Hugo J. De Man (M’81–SM’81–F’86) is Professor of Electrical Engineering at the Katholieke Universiteit Leuven, (K.U. Leuven), Leuven, Belgium since 1976. In 1975, he was a Visiting Associate Professor at the University of California, Berkeley, teaching device physics and integrated circuit design. His early research was devoted to the development of mixed-signal, switched capacitor and digital signal processing (DSP) simulation tools as well as new topologies for high-speed CMOS circuits. He is Cofounder of IMEC, where he was Vice-President from 1984–1995, in charge of design methods for DSP and telecom oriented chip architectures. Since then, he is a Senior Research Fellow of IMEC, working on design methods for low-power post-PC systems in nanoscale technologies. The work of his research team at IMEC has lead to many novel tools and methods in the area of high level synthesis, hardware-software co-design and C++ based design now available through a number of spin-off companies. Dr. De Man received the Technical Achievement Award of the IEEE Signal Processing Society, The Phil Kaufman Award of the EDA Consortium, and the Golden Jubilee Medal of the IEEE Circuits and Systems Society in 1999. In 2004, he received the lifetime achievement awards, respectively, of the European Design and Automation Association (EDAA) as well as the European Electronics Industry. He is a member of the Royal Academy of Sciences in Belgium.

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