Fabrication Of Mosfet

FABRICATION OF MOSFET MOHIT GEAT 10706059 3EC3

MOS TECHNOLOGY MOS technology is the basis for most LSI and all VLSI and ULSI digital memory and microprocessor circuits.  The most important advantage of MOS circuits over bipolar circuits for LSI is that more transistors and more circuit functions may be successfully fabricated on a single chip with MOS technology. 

There are 3 reasons for this : 1.  An individual MOS transistor occupies less chip area 2.  MOS fabrication process involves fewer steps and as a result achieves fewer critical defects per unit chip area than in bipolar circuit fabrication. 3. Dynamic circuit techniques that require fewer transistors to realise a given circuit function are practical in MOS technology. ⇒ LSI (and thus VLSI) circuits significantly cheaper to manufacture than bipolar circuits of equivalent function.

BASIC PROCESSING STEPS IN THE FORMATION OF A METAL OXIDE SEMICONDUCTOR

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The process starts with the oxidation of the silicon substrate (a), in which a relatively thick silicon dioxide layer (5000A), also called field oxide, is created on the surface (b).

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the field oxide is selectively etched to expose the silicon surface on which the MOS transistor will be created (c).

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surface is covered with a thin, high-quality oxide layer (25A), which will eventually form the gate oxide of the MOS transistor (d).

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On top of the thin oxide, a layer of polysilicon (polycrystalline silicon, 3000A) is deposited (e). Polysilicon is used both as gate electrode material for MOS transistors and also as an interconnect medium in silicon integrated circuits.

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After deposition, the polysilicon layer is patterned and etched to form the interconnects and the MOS transistor gates (f).

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The thin gate oxide not covered by polysilicon is also etched away, which exposes the bare silicon surface on which the source and drain junctions are to be formed (g). The entire silicon surface is then doped with a high concentration of impurities, either through diffusion or ion implantation (h) shows that the doping penetrates the exposed areas on the silicon surface, ultimately creating two ntype regions (source and drain junctions) in the p-type substrate. polysilicon gate, which is patterned before doping actually defines the precise location of the channel region and, hence, the location of the source and the drain regions. Since this procedure allows very precise positioning of the two regions relative to the gate, it is also called a selfaligned pr ocess.

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the entire surface is again covered with an insulating layer of silicon dioxide (i).

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The insulating oxide layer is then patterned in order to provide contact windows for the drain and source junctions (j).

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The surface is covered with evaporated aluminum (5000A) which will form the interconnects (k).

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Finally, the metal layer is patterned and etched, completing the interconnection of the MOS transistors on the surface (l).

CMOS N WELL PROCESS 

The n-well CMOS process starts with a moderately doped (impurity concentration ~1016 /cm3) p-type silicon substrate.

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Then, an initial thick “field” oxide layer (5000A) is grown on the entire surface.

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The first lithographic mask defines the n-well region.

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Donor atoms, usually phosphorus, are implanted through this window in the oxide

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Following the creation of the n-well region, a thick field oxide is grown around the transistor active regions, and a thin gate oxide (25A) is grown on top of the active regions.

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The polysilicon layer (3000A) is deposited using chemical vapor deposition (CVD) and patterned by dry plasma etching

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The created polysilicon lines will function as the gate electrodes of the nMOS and the pMOS transistors and their interconnects.

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Also, the polysilicon gates act as self-aligned masks for the source and drain implantations that follow this step

CVD CHEMICAL REACTIONS 

SiH4(gas) + O2(gas)  SiO2(solid) + 2H2 (gas)

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SiH4(gas) + H2(gas) +SiH2(gas)  2H2(gas) + PolySilicon (solid) Continuous gas flow

Diffusion of reactants Boundary layer Deposited film Silicon substrate

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Using a set of two masks, the n+ and p+ Source and Drain regions are implanted into the substrate and into the nwell, respectively The ohmic contacts to the substrate and to the nwell are implanted in this process step

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An insulating silicon dioxide layer is deposited over the entire wafer using CVD (5000A). This is for passivation, the protection of all the active components from contamination. The contacts are defined and etched away to expose the silicon or polysilicon contact windows. These contact windows are necessary to complete the circuit interconnections using the metal layer, which is patterned in the next step.

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Metal (aluminum, >5000A) is deposited over the entire chip surface using metal evaporation, and the metal lines are patterned through etching. Since the wafer surface is non-planar, the quality and the integrity of the metal lines created in this step are very critical and are ultimately essential for circuit reliability. Since the metal connects two separate devices, it is called Local Interconnect.

INTERCONNECTION MATERIALS 

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Polysilicon interconnects are used to connect Gates and other short-distance connections which have minimal currents. Polysilicon is a very stable material that rarely interacts with nearby materials. Metal interconnects have 3-5x the speed of polysilicon (electron mobility is higher) and less resistance. However, metals may react with nearby materials, and may have to be encapsulated using nitrides (e.g. Si3N4 or TiN) to prevent unwanted reactions, or partial erosion in subsequent etching procedures. This is expensive.

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The composite layout and the resulting cross-sectional view of the chip, showing one nMOS and one pMOS transistor (built-in n-well), the polysilicon and metal interconnections.

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The final step is to deposit a full SiO2 passivation layer (5000A), for protection, over the chip, except for wirebonding pad areas.

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If the wafer will be stored for some months, a final thin blanket layer of Si3N4 may be applied to prevent penetration by water vapor.

LATCH UP PROBLEM IN CMOS PROCESS The CMOS process produces parasitic transistors in the structure of CMOS bulk ICs.  Latch Up refers to a self sustaining low impedance path between the voltage applied Vdd (+5V) and ground that is created by parasitic vertical and lateral bipolar transistors.  If these transistors are properly biased, latch up can cause large currents to flow, destroying the MOS devices. 

Advanced CMOS Technologies Twin-Tub (Twin-Well) CMOS Process  

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This technology provides the basis for separate optimization of the nMOS and pMOS transistors making it possible for threshold voltage, body effect and the channel transconductance of both types of transistors to be tuned independently. the starting material is a n+ or p+ substrate, with a lightly doped epitaxial layer (~1015/cm3) on top. This epitaxial layer provides the actual substrate on which the n-well and the p-well are formed. In the conventional n-well CMOS process, the doping of the well region is typically about one order of magnitude higher than the substrate, which, among other effects, results in unbalanced drain parasitics (possible latchup). The twin-tub process, below, avoids this problem.

Advanced CMOS Technologies Silicon-on-Insulator (SOI) CMOS Process

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Rather than using silicon as the substrate material, an insulating substrate will improve process characteristics such as speed and latch-up susceptibility. The SOI CMOS technology allows the creation of independent, completely isolated nMOS and pMOS transistors virtually side-by-side on an insulating substrate. The main advantages of this technology are the higher integration density (because of the absence of well regions), complete avoidance of the latch-up problem, and lower parasitic capacitances compared to the conventional n-well or twin-tub CMOS processes.

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