Dld Final

ARITHMATIC CIRCUIT This is an arithmetic project .In this one 4 bits binary full ADDER, two 2 bits 4 x 1 MUX and one NOT GATE used. It perfumes followings arithmetic operation A+B A+B+1 A + B^ A–B A A+1 Arithmetic circuit perfume the above operation following TRUTH TABLE

S0

S1

Cin

Outputs

0 0 0 0 1 1 1 1

0 0 1 1 0 0 1 1

0 1 0 1 0 1 0 1

A A+1 A+B^ A+B^+1 A+1 A+1+1 A+B A+B+1

In this S0 and S1 are the selation lines of the MUX and Cin is the input of the FULL ADDER. In this MUX performs following task

S0

S1

Outputs

0 0 1 1

0 1 0 1

I0 I1 I2 I3

1

BLOCK DIAGRAM

B0 B^ 0 1 0

A0

MUX

S0

FA

A1 B1 B^ 1 1 0

MUX

FA

S1

FA

S2

FA

S3

A2 B2 B^ 2 1 0

MUX

A3 B3 B^ 3 1 0

MUX

COUT

74LS04

1

WIRING DIAGRAM A- 4 S- 3 A- 3 B- 3 Vcc S- 2 B- 2

bit binary-4 full adder 74LS283A

B- 4 S- 4 Cout Cin GN B-1 A-1

A-2

S- 1

En-a S-1 I3- a I2- a I1- a I0- a Z- a

Vcc En b S-0 I3-b I2-b I1-b I0-b

x 1 MUX 4 74LS153A

GNd

En-a S-1 I3- a I2- a I1- a I0- a Z- a GNd B-1 B^1 B-2 B^2

Z-b

x1MUX 4 74LS153A

Vcc En b S-0 I3-b I2-b I1-b I0-b Z-b Vcc B-3 B^3 B-4 B^4

GND

1