Dld Assignment 2.docx

Bahria University, Islamabad Subject: Digital Logic Design (CEN-120) Assignemnt # 02(CLO-2) Name: _________________________

Instructor: Ammara Nasim/Zain Bin Khalid

Class: BEE-2:

Date: 25-03-19

Enrolment: ___________________________

Question # 1 Consider you are a research engineer who is assigned to cut the hardware cost of the circuits by reducing the gate count. For this you have to find multiple options through which you can do it. A junior engineer designed a circuit for solving a problem whose end statement is 𝐹(𝐴, 𝐵, 𝐶, 𝐷) = 𝐴𝐶𝐷′ + 𝐶 ′ 𝐷 + 𝐴𝐵 ′ + 𝐴𝐵𝐶𝐷 You have the following options: 1. Use multiple AND gates and one multi input OR gate 2. Use multiple OR gates with one multi input AND gate. Implement both of these scenarios and discuss with reasons which one would be lesser in cost. Question # 2 During your current job your boss has asked you to re-implement the circuit that someone designed and implemented two years back on hardware. 1. 𝐹(𝐴, 𝐵, 𝐶, 𝐷) = ∑(5,6,7,12,14,15) 2. 𝐹(𝐴, 𝐵, 𝐶, 𝐷) = 𝐴′𝐵 ′ 𝐶 ′ 𝐷 + 𝐶𝐷 + 𝐴𝐶′𝐷 The following are requirements: 1. The number of gates in the circuit should be minimum possible. 2. Only one type of gate can be used. Implement the above circuit by choosing the optimum gate and state reasons for your choice. Question # 3 Now the stock available in your lab is limited to only one multi input NAND gate along with some OR gates. You have to utilize the available resources to implement the following circuit. 𝐹(𝐴, 𝐵, 𝐶, 𝐷) = ∑(0,4,8,910,11,12,14) The other stock room has one multi input NOR gate and some available AND gates. Solve the previous problem through this combination. Two other available combinations are NAND -AND and NOR-OR. Implement all four combinations and clearly mention the most inexpensive combination and state your reason for that. Happy designing, all engineers 😊 Page 1 of 1