Class Notes Sampling.pdf

Nov. 30, 1965

3,22 1,309

R. BENGHIAT PRIORITY INTERRUFT MONITORING SYSTEM

Filed Aug. 10, 1961

16 Sheets-S heet 1

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ARITHMETIC AND PROGRAMMER MEANS

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I N VENTOR.

RALPH BENGHIAT BY

Nov. 30, 1965

R. BENGHIAT

3,221,309

PRIORITY INTERRUPT MONITORING SYSTEM

Filed Aug. 10, 1961

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16 Sheets-Sheet 3

Nov. 30, 1965

R. BENGHIAT

3,221,309

PRIORITY INTERRUPT MONITORING SYSTEM

Filed Aug. 10, 1961

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Nov. 30, 1965

R. BENGHIAT

3,221,309

PRIORITY INTERRUPT MONITORING SYSTEM

Filed Aug. 10, 1961

16 Sheets-Sheet 8

F-

B LEVEL l '

CLOCK ROUTINE

CLOCK PULSE

(EVERY as SECONDS) INTERRUPT

STORE 5E0, COUNTER INLUC. I00

Loc. sa'b (PR'ORITY ORDERS FOR

TRANSFER TO LOC. lO/a,

LEVEL \

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‘FIGURE:

INVENTOR.

RALPH

BENGHIAT TYS.

Nov. 30, 1965

R. BENGHIAT

3,221,309

PRIORITY INTERRUPT MONITORING SYSTEM

Filed Aug. 10, 1961

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INVENTOR

RALPH‘ BENGHIAT BY

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Nov. 30, 1965

3,221,309

R. BENGHIAT PRIORITY INTERRUPT MONITORING SYSTEM

Filed Aug. 10, 1961

l6 Sheets-Sheet l3

4 LEVEL 2 -MULT|PLEXER INPUT ROUTINE MULTIPL E XER NOT BUSY

INTERRUPT STORE SEQ. COUNTER IN L0(. 200

Loc. 6Q,b(PRl0RITY ORDERS FOR LEVEL 2-73 200: 40 20!

TRANSFER TO LOC. ZOIQ. Loc. 20lcL-203b

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(Exrr SEQUENCE)

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RALPH

BENGHIAT 0,4122)

A'rrvs,

Nov. 30, 1965

R. BENGHIAT

3,221,309

PRIORITY INTERRUPT MONITORING SYSTEM

Filed Aug. 10, 1961

16 Sheets-Sheet 14

F- ‘5 LEVEL 3 .?; BINARY To DECIMAL CONVERSION ROUTINE

(4 DIGIT PosITIvE INTEGER) PSEUDO INTERRUPT FROM LEVEL 4 0R LEVEL 5

INTERRUPT

(VALUE TO BE CONVERTED Is m Acc)

5m; 5m, COUNTER IN LOQ 30o TRANSFER TO LOC. 30m

LOC. 70.,b (PRIORITY ORDER FOR LEVELS-73 300 = 40 31M)

LOC. 30m.

LOC. 303b-305

{CLEAR WORKSPACE LOC. 3201

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ADD Iooo T0 Acc.

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(RESULT OF CONVERSION '5 'N Acc')

INVENTOR.

RALPH

BENGHIAT

BY

'

I

A'r-rvs,

Nov. 30, 1965

R. BENGHIAT

3,221,309

PRIORITY INTERRUPT MONITORING SYSTEM

Filed Aug. 10, 1961

16 Sheets-Sheet l5

,6

LEVEL 4 -LOG DATA PREPARATION ROUTINE

PSEUDO INTERRUPT FROM LEVELI OR LEVEL 5 INTE RRU PT

STORE SEQ. coumen IN LOC.400 TRANSFER To me. 40m

LOC.8Q,b(PRIORITY ORDERS FOR LEVEL 4’73 400"“ 4°‘)

LOC. 40m); 1 STORE Acc. m 1.06.416 CLEAR coumsre 11v LOC.4I7

I; LDC. 4020: 404 b 7 COPY A3 MASK DIGIT5 INTO AC6.

SIGNAL P.5EUDO INTERRUPT

ADD I TO COUNTER

‘{ LOC. 408 -4Hb l

Copy DATA VALUE mrro Acc. WAIT FOR M/TERE’UPT

' INTERRUPT

COPY A7 MASK DIGITS {no 4C6. SIGNAL psauoo INTERRUPT

copy R4 MASK DIGITJ INTO Act. Ram. 94

RESTORE OLD ACC. CONTENTS

ROUTINE OF LEVEL 3

EXIT T0 LOWER LEVEL

LOC. 405a,‘:

| sroses corwaerso VALUEj LOC. 40641-4070. ‘ YES Q COUNTER = N ?

LOC. 40%

H

,NO

| TRANSFER T0 1.0:. 402a. ]

~___J INVENTOR.

RALPH

BENGHMT ATTYS.

United States Patent 0 "

3,221,309 Patented Nov. 30, 1965

1

2

3,221,309

example, a program sub-routine which is used in common with other program sub-routines is given an independent

Ralph Benghiat, Paci?c Palisades, Calif., assignor to The

priority status along with the program sub-routines which

PRIORITY INTERRUPT MONITORING SYSTEM

Scam Instrument Corporation, a corporation of Illinois

Filed Aug. 10, 1961, Ser. No. 130,615 14 Claims. (Cl. 340-1725)

use the common sub-routine.

The common or shared

routine is initiated by a program generated signal, re ferred to as a ‘*pseudo" interrupt demand signal, which is treated by the monitoring system in the same manner

This invention, in general, relates to industrial process as the aforementioned external or manual interrupt de monitoring systems or other systems wherein the system mand signals. It is important that the shared routine must examine and respond to input data as it arrives, 10 initially operated by a pseudo interrupt demand signal instead of merely storing the data for future examination from one of the other routines be non-interruptable by and use. In this, they diifer fundamentally from most the other routine or routines which share it. Otherwise, business and scienti?c data processing machines. For data developed by the common shared routine may be

safety and efficiency, the industrial process monitoring

lost when interrupted by the latter routine. This prob

system must be available at all times to attend to the needs of the process. However, some aspects of the invention have a more general application.

lem is overcome by assigning the shared routine a priority level which is higher than the program routines which could demand its operation.

A typical present day industrial process monitoring sys

The provision of pseudo interrupt demand signals and the special program routines operated by them results in an overall program of the highest possible efficiency and

tem has an electronic computer system including arith metic and memory sections. The memory section usually stores various data constants, such as high and low alarm or control limits, scale factors, and a multiplicity of pro gram routines for carrying out different types of system

operation demanded by the process being monitored, or

?exibility. The pseudo interrupt demand signal generated in a program routine can be used not only to initiate an

immediate interrupt to a program routine of higher prior ity as indicated in the above shared routine example, but

by various external signal sources such as manual switches it can also be used to initiate the later operation of pro and the like. The arithmetic section carries out various gram routines having a lower priority than the currently operated routine. arithmetic operations called for by the program, such as comparing the values of the process variables with the In accordance with another aspect of the invention, alarm or control limit values by a subtractive process individual program routines are set up to be initiated by which indicates whether an alarm or control function is 30 “not busy” or “ready” signals from various input or out put devices used in the monitoring system so that the to be carried out. One of the program routines may be a normal basic routine which includes the scanning of most efiicient use of these devices may be had. For the various process variables and examining the variable example, the scanner or multiplexer which scans the process variables are commonly provided with “ready” values for alarm conditions. The basic routine may be

momentarily interrupted or modi?ed by the presence of various external signals calling momentarily for other program routines. The operation of one manual switch,

signal generating means for indicating to the computer

changes the data constants and the operation of another

when it is ready to transfer data to the computer or other input equipment such as an analog to digital converter. The “ready” signal is used as a priority interrupt demand signal in the same way as the other discussed priority

switch may call for a program routine which reads out the stored data values to a typewriter.

interrupt demand signals so that the scanning routine is carried out immediately whenever the other demanded

for example, may call for a program routine which

Where the monitoring system almost simultaneously routines are of lower priority. Since one of the most important functions of a monitoring system is to detect receives a number of manual demands for different pro~ alarm values of variables or variables which require gram routines, the question arises as to the order in which these demand signals are obeyed and the manner in 45 special control functions, the prompt operation of the scanner becomes of extreme importance. which the currently active program routine is affected. If it is desired that all program routines be carried out In accordance with still another aspect of the invention, in an order depending upon the relative importance or the current activity of the program routines is visibly in priority of the routines, the different routines may be dicated by the energization of lamps or other visual in assigned priority level numbers in accordance with their 50 dicating means assigned to the respective program rou relative importance and the priority level number of a tines. Since many of the routines are carried out in such routine in progress compared with the priority numbers a short time period that a lamp energized for such a of the program routines whose operation have been period would not be visible, means are provided for ex demanded. The current program is immediately inter tending the period of response of each alarm lamp some rupted and replaced by the demanded program routine what beyond the time of occurrence of the program rou of a higher priority. The point of interruption of the tine involved. The provision of these indicating lamps interrupted program routine is recorded in memory so greatly facilitates the operator in his knowledge about the that it can be later resumed. After completion of all operation of the system. For example, program inter demanded program routines of higher priority, the inter rupt operations will be indicated by seemingly steady or rupted program is resumed. prolonged light indications since the activation of the The present invention is a substantial improvement program routines is extended by interrupt operations. over the basic priority interrupt scheme just outlined by The activity of uninterrupted program routines are usu increasing the flexibility and scope of priority assign ally indicatcd by blinking lamps, that is lights which are ment, simplifying the program of the monitoring system, energized only momentarily. This aspect of the invention

and greatly increasing the e?iciency of utilization of input and output devices normally repeatedly used by the system. In accordance with one aspect of the invention, certain program operations which are normally part of a larger program routine assigned to a single priority level are

has application to computer systems generally. Where a large number of external program interrupt demand signals are involved, it may become impractical to assign each routine operated by a demand signal a different priority level. The presence of a very large

given independent priority status, even though they are 70 number of demand signals and associated independent not directly demanded by external demand signals. For routines of secondary importance can encumber the speed

3,221,309

3

4

of the monitoring system and unduly complicate the tion, various program routines of secondary priority status and which could have independent priority status

FIG. 14 is a How diagram illustrating the multiplexer input routine which has been assigned priority level No. 2; FIG. 15 is a ?ow diagram illustrating the binary to decimal conversion routine which has been assigned

are grouped together in a single routine as sub-routines

priority level No. 3;

same. In accordance with another aspect of the inven

joined together by conditional transfer program steps

FIG. 16 is a ?ow diagram illustrating the log data

which branch the program to a sub-routine or sub-rou

preparation routine which has been assigned priority level

tines called for by the external demand signals involved. a single interrupt demand signal is generated which ef

No. 4; and FIG. 17 is a How diagram illustrating the operator’s request routine which has been assigned priority level

fects an interrupt operation to the common routine when

No.5.

The presence of the latter demand signals are stored and

it is the highest priority routine demanded by the sys tem.

PART I—GENERAL DESCRIPTION Refer now to FIG. 1 which illustrates the use of the

In addition to the various broad aspects of the inven present invention in connection with a system for monitor tion just outlined, the invention has many speci?c as 15 ing process or other variables in a chemical or industrial pects dealing with speci?c ways of carrying out these process. The values of the various variables of the broad features. As will appear, some of these speci?c process may be detected by suitable transducer devices

aspects have applications beyond the particular applica 2, such as thermocouples in the case of temperature vari tions illustrated above. For example, one such aspect ables. The individual electrical outputs of the transducers deals with a unique way for handling and storing in 20 2 are fed to the input of a scanner or multiplexer 4. The formation of the various external and internal interrupt scanner 4 can take any one of a number of forms well demand signals, and for examining the stored informa known in the art, but is preferably an electronic diode tion. The means for storing this information is referred matrix scanner well known in the art which can randomly to as an interrupt register. The interrupt register has select any transducer input in accordance with control provision for storing markers indicating momentary or 25 signals fed to an input 5 thereof. The output of the scan persisting demand signals and successive demand signals. ner 4 is shown connected to the input of an analog to A routine demanded by a persisting demand signal is digital converter 6 which converts an anaiog input to a locked out after it completes one cycle of operation. binary digital output in a well known manner. The out Also, a routine which is activated but not completed by put of the analog to digital converter 6 is fed to a regis a momentary signal can be caused to operate a second 30 ter 7 in turn connected to the input of a storage, arith

time automatically at a later time by the presence of a

second demand signal.

metic and program means generally indicated by ref erence numeral 8. The storage, arithmetic and program

The above and other objects, advantages and features ing functions carried out by this portion of this system is of the invention will become apparent upon making commonly carried out by electronic computers. The reference to the speci?cation to follow, the claims and 35 exact form of the computer forms no part of the present the drawings wherein: invention although, to illustrate the use of the present in FIG. 1 is a basic box diagram of a monitoring system vention, reference will be made to the model 803 com

incorporating the program interrupt system of the present

invention;

puter manufactured by Elliott Brothers, Ltd. of London, England.

A disclosure of the circuitry and mode of

FIGS. 2 and 2A together represent a more detailed 40 operation of this computer will not be disclosed or ex

box diagram of the system shown in FIG. 1; FIGS. 3, 3A, 3B, 3C and 3D represent an exemplary circuit diagram of the program interrupt control and register means forming part of the system shown in FIGS. 2 and 2A; 45

plained in any great detail in this application. However, such information is incorporated in a book in the Scienti?c Library of the Patent O?ice entitled “Handbook for the

National-Elliott 803 Computer.” Also, a block diagram of part of the computer 8 is shown in FIG. 8 and the FIG. 4 is a diagram illustrating the manner in which core circuitry of those portions of the computer to which FIGS. 3, 3A, 3B, 3C and 3D can be arranged to form an the interrupt apparatus of the invention is connected is integral circuit diagram; shown in FIGS. 5, 5A and 53. FIGS. 5, 5A and 5B show core circuit diagrams of Where an industrial process is being monitored, it is parts of an exemplary Elliott 803 computer to which the 50 normally necessary for the safety of the equipment and circuit of FIGS. 3, 3A, 3B, 3C and 3D make connection; personnel involved to continuously scan for variables FIG. 6 identi?es the various types of inputs to the core

which are in an abnormal unsafe range. The scanning op

circuits of FIGS. 5, 5A and 5B; eration should, therefore, have a relatively high order of FIG. 7 illustrates a timing diagram which relates to priority on the use of the computer 8. However, numer certain operations performed in the computer to certain 55 ous other operations are performed by the monitoring sys operations performed in the program interrupt apparatus tem other than scanning for abnormal variables, such as of the present invention; periodically feeding data on all the variables to an out FIG. 8 illustrates the types of information which cir put device 10 which may be an electric typewriter. In culates in the computer operations register; other words, many demands are made on the computer 8 FIG. 9 illustrates the arrangement of the bits of in 60 other than the demand for handling the signals obtained formation stored in the interrupt register of the present from the transducers 2. Since it takes the scanner 4 a

invention;

certain ?nite time to get set to receive new information

FIG. 10 consisting of FIGS. 10(a), 10(b) and 10(0)

and to feed it to the analog to digital conviefter 6 or to switch from one point to another, the computer 8 may in the computer memory and used to examine and reset 65 perform other functions While the scanner is getting set. the contents of the interrupt register; Normally, a scanner is provided with means for gener ating a signal which indicates whether the scanner or FIG. 11 consisting of FIGS. 11(a), 11(1)), 11(0) and

shows the binary code format for the C mask bits stored

11(d) indicates the R mask bit and pseudo mask bit multiplexer is ready to receive information from the trans code group stored in the computer memory for resetting ducer 2 and to transmit information to the analog to certain R bits in the interrupt register and for initiating 70 digital converter 6, such signal being fed to the computer pseudo demand signals for certain priority levels; 8 to prevent the coupling of the output thereof of the ana FIG. 12 shows the format of a typed instruction word log to digital converter, before it is connected or gated to the computer input. This signal is sometimes referred to group stored in the computer memory; FIG. 13 is a ?ow diagram illustrating the clock rou as a “not busy" or “ready” signal. In FIG. 1, this sig tine which has been assigned priority level No. 1; 75 nal is assumed to be present on a line 14 extending from

3,221,309

5

6

the scanner 4. For similar reasons, the output device such as the typewriter 10 is frequently provided with means for signaling when the output device is busy or not busy, so that the computer 8 may utilize the output device when it is ready to be utilized and not at other times. In FIG. 1, this “not busy” signal is assumed to be fed from the

for registering the presence of C bit demand signals as “C bit markers" so that, when a shared program routine is activated, the program routine can select by a condi

tional transfer program step particular program sub-rou tine or sub-routines which correspond to the C bit de

mand signal or demand signals which activated the shared program routine. The aforementioned register to be called the interrupt register also stores information as “A bit markers“ on interrupt demand signal input terminals 18-1-18-15 which receive momentary or persisting inter rupt demand signals. There are ?fteen C bit marker po sitions C1 through C15 in the interrupt register for the aforesaid ?fteen possible C bit demand signals and ?fteeen A bit marker positions Al through A15 for the aforesaid

typewriter 10 on a line 16. In accordance with one aspect of the present invention,

instead of connecting the “not busy” or “ready” lines 14 and 16 associated with the scanner 4 and output de vices directly to the computer, these lines are connected to interrupt demand terminals 18-2 and 18-6 of an inter

rupt control and register means generally indicated by reference numeral 18. These “ready” signals along with other demand signals to be described are utilized to ini

tiate respective program routines stored in the computer memory which are assigned different priority levels. Later on in the speci?cation, an examplary detailed description will be given of a simpli?ed scanning program routine

15

initiated by the “ready” signal from the scanner 4 to , illustrate the general manner in which the “ready” or “not

busy” signals are handled. The exemplary monitoring system is one which is capable of handling demand sig

fifteen possible interrupt demand signals. The numbers 1 through 15 following the “A” refer to markers for prior ity levels 1 through 15. The interrupt demand inputs of the interrupt control and register means 18 designated by reference numerals 18-1, 18-2, 18-5 and 18-6 are respectively connected to circuits which will record A bit markers for priority levels Nos. 1, 2, 5 and 6 respectively.

The priority interrupt demand signals may be simulta neously present on the interrupt signal input terminals

nals for ?fteen different levels of priority. The program routine initiated by the “ready” signal of the scanner 4 will

18-], 18-2-18-n. The computer 8 cannot respond to all of the demand signals at the same time since it is capa—

be assigned the second highest priority level No. 2. In the exemplary application of the invention to be de scribed, the computer 8 is to respond to periodic timing signals generated by a timer 20 which, for example, are to

ble of carrying out only one program step at a time. In order to utilize the various input signals to the device most efficiently, the computer 8 should respond to the be counted and stored in the computer memory, and at the 30 interrupt demand signals in order of the importance or priority of the program routines which they activate. If appropriate time will initiate a program routine which pre pares the scanned data for readout to the typewriter 10. the computer 8 is carrying out a given program routine assigned a given priority level which is lower than the These timing signals could, of course, be utilized for various other purposes also. The timer 20 has an out priority level of any other demanded routine, the cur put line 20' connected to an interrupt demand input 18-1 rent routine should be interrupted so that the higher prior of the interrupt control and register means 18 which signal ity level routines called for can be carried out ?rst. To will initiate operation of a program routine stored in the this end, the interrupt control and register means 18 has computer memory which handles this timing signal in a stored therein information as R bit markers which in desired manner. This program routine must of neces dicate the priority level of program routines in progress

sity be given the highest priority level No. 1. A number of manual demand switches generally indi~ cated by reference numeral 22 in FIG. 1 are provided to initiate certain operations of the computer 8, such as pre paring and feeding data stored in the computer memory to the typewriter 10, changing alarm set points, etc. In the exemplary form of the invention to be described these switches respectively initiate simpli?ed program routines which prepare all the data values stored in the computer memory for readout to the typewrtier 10 and to select and

prepare the highest data value stored in the computer memory for readout to an output display unit 10'. Lines 24 and 24' extend from these manual switches to inputs 18a and 18b of the interrupt control and register means 18. It will be assumed that these switches will initiate operation of a single shared program routine stored in computer memory assigned priority level No. 5. This program routine will have separate subroutines each for carrying out one of the switch operations referred to, if

the associated switch is momentarily operated. The sig

40

and also of program routine or routines which have been

interrupted and not yet completed.

The R bit marker

for priority level No. 1 is referred to as the R1 bit marker, the R bit marker for priority level No. 2 is referred to as the R2 priority bit marker and the R bit marker for the remaining levels are respectively referred to as the R3, R4 . . . R15 markers.

These markers are reset, that

is removed, when their routines are completed. The in terrupt register and control means also stores C1 through C15 and B1 through B15 bit markers which respective ly indicate the C bit demand signals which have not yet effected a program interrupt operation and the presence of successive or persistent interrupt demand signals in conjunction with the associated R bit markers. Interrupt and lock-out operations are controlled by these markers in a manner to be described later on in this speci?cation.

In accordance with still another aspect of the present invention, the interrupt register and control means 18 control the energization of R bit indicator lamps 19-1 through 19-15 to indicate the presence of program rou tines which have been activated but which are not yet

nals generated by the manual switches 22 are sometimes referred to as C bit demand signals. In the example of the 60 complcted. invention to be described, up to ?fteen different C bit de In addition to the various program routines which are mand signals can be grouped into various combinations. operated directly by the interrupt demand signals on the The drawings show three signals per group, each group terminals 18-1, 18-2, etc., other program routines are sharing one of ?ve possible priority levels. However, by set up which are initiated by signals generated within the adding additional circuits or chanels to the circuit to be computer 8, which signals are referred to as pseudo in described, all the C bit demand signals could share one or terrupt demand signals. The pseudo interrupt-responsive more routines. Only the operation of two C bit signaling routines are assigned distinctive priority levels. These switches sharing one priority level will be described in priority interrupt signals effectively establish links be detail since this is sufficient to illustrate this aspect of the tween various program routines and are handled by the invention. The operation of any one C bit signaling interrupt control and register means 18 in the same way means in each group is effective to generate an interrupt as are the other interrupt demand signals fed to the ter demand signal on a line 25 extending from the interrupt minals 18-1, 18-2, etc. The provision of pseudo inter control and register means 18 and re-entering the same at rupt signals establishes substantial simpli?cation and ?ex an interrupt demand input 18-5. The interrupt control ibility in programing. For example, routines can be set up which are used in common by other routines and to and register means 18 includes a register to be described

3,221,309

7

8

safeguard various intermediate results obtained by the

because C bit demand signals are not effective to set

corresponding A bit markers until the C bit demand sig nals disappear. If the C bit demand signals resulted in A bit markers during their occurrence, the persistence of one C bit signal could prevent operation of the shared routine by the other associated C bit demand signal. The absence of lockout of a C bit initiated routine is prevented operation have been assigned priority levels Nos. 4 and also by other features of the invention to be explained 5. The program routine which has been assigned priority later on in the speci?cation. level No. 5 is the one operated by the C bit manual In accordance with still another aspect of the present switches 22. 10 invention, the disappearance and re—establishment of an When the computer 8 is idling, that is, when no inter interrupt demand signal other than a C bit interrupt rupt demand signals are present, the computer will auto demand signal during the activation of a program routine matically carry out some basic routine assigned the low will set a corresponding B bit marker instead of an A bit est priority level. No interrupt demand signal is neces marker which, upon completion of the routine, will set sary to enter this routine and no A, R, C or B bit markers another A bit marker to eifect another interrupt operation. are associated with this routine. Table II summarizes the various combinations of A, B Tables I and IA illustrate various program routines and R bit markers to which the monitoring system of the which will be referred to in describing the operation of invention responds and the meaning of these combina the present invention, the nature of the signals which initiate these routines, and the broad functions carried out tions. PART II—SPECIFIC DESCRIPTION thereby. In accordance with still another aspect of the present in (a) Patchboard 30 vention, when an interrupt demand signal persists after the program routine demanded by it has been completed, Although the interrupt control and register means indi the routine is “locked out” and cannot be re-activated cated by box 18 in FIG. I may take a variety of forms, until the interrupt demand signal disappears and is re and could even be partially, at least, incorporated in the established again. The presence of a B bit marker and computer itself, it is preferred that it have the features the absence of a corresponding A and R bit marker will illustrated in the circuit diagram of FIGS. 3 and 3A. To cause a lockout operation of the routine involved. (Lock Table II out of C bit shared routine is not permitted for reasons 30 to be explained.) Whenever a routine is completed, if an A B R interrupt demand is still present, the associated A bit 0 0 0 No demand, level not active.

common routine, the shared routine is given a higher priority level than any of the routines which demand its operation. In the exemplary form of the invention to be described, a common shared routine has been assigned priority level No. 3 and the routines which demand its

marker involved is removed and a B bit marker is set

1

0

0

Demand marked, level not active.

which prevents the demand signal involved from effecting a subsequent interrupt operation. When the demand 35 signal involved disappears, the associated B bit marker is automatically removed to permit an interrupt opera-

1 0 0 0

0 0 l l

1 1 1 0

Level activated, demand signal persists. Level activated, demand signal removed. Level activated, second demand marked. Activity completed, demand signal persists.

tion when the interrupt demand signal is later re-estab-

1

1

0

Cannot occur.

lished.

1

1

1

Cannot occur.

Table 1 Interrupt demand signals

Priority level

Functions

(1) Time responsive routine ___________________ __

(2) Multiplexer input routine __________________ t,

External demand signal (‘very 15 seconds ..... __

Demanded by signal that multiplexer is not busy.

(3) Binary to decimal conversion routine ______ .. ‘ t _ l ,

[(1) Pseudo interrupt from level 4 _______ t.

3(2) Pseudo interrupt from level 5,

Counts time pulses. (i) Reads a multiplexer input. (‘3) Processes and stores data. (3) (‘omits nuinln-r olreadings. , r‘onvt‘rts binary numbers to decimal form for

output.

(1) Pseudo interrupt. from level 1 im 3 l1 1ur_..' \l‘roecsscs stored data for out iut ever ' hour or

(4) Log dd“ Prcpdmuon routine ------------- " i9)‘ l]St‘ll(l1O]i]Jbt’l‘l'Ll[ll. from level 5 if uxturliully I when dmmmdm],

l

y

1 einnm or .

I

G hits produced liyinanuul switches:

(5) Operators‘ rvriuvslswlmlw ---------------- ~

Examines C‘ hits.

(7, P11011111“ 10s .................. ..

L2=l4 ind and convert largest value (7) Printer output routinohwt ________________ _. Pseudo interrupt from level ~i___..

minim.

ll

02,

highest value.

ll‘ C1, then transfers to log than

Dprl'onpg Search

[or

..

Output routine to output device it] (Typewriter).

(8) Visual display output routine ______________ __

Pseudo interrupt from level 5_ ________________ ,_

Output routine to output device 10’ (Visual

(6). (9) through (15) ___________________________ _.

Not used Nonc____

Computer idles when no interrupt. is demanded.

(16) Basic routine _____________________________ ..

display).

Table IA Priority level

Programmed demands for ulhor levels

60

aid in understanding the circuitry there shown, a detailed box diagram of the interrupt control and register means 18 is shown in FIG. 2 which indicates the functions of

5 minutes.

various sections of the circuit, the portions represented by the boxes in FIG. 2 being indicated by dashed boxes in FIGS. 3, 3A, 3B, 3C and 3D. Also, the interconnec

every hour.

tion between the interrupt control and register means 18

(1) Time responsive routino__.. (1) Initiates multiplexer busy every (2) Causes pseudo interrupt to level 4

(2) Multiplexer input routine.. If number of readings has not reached stored limit, than initiates inulti 65 and the Elliott 803 Computer 8 are shown by identically designated connecting points in FIGS. 3, 3A, 3B, 3C and plcxor busy. Otherwise exits, Lock (3) Binary to decimal conversion routine.

(4) Log data preparation routine.

ing out levol 2. None. ‘

3D, and FIGS. 5, 5A and 5B showing only a part of the Elliott Computer disclosed in said “Handbook for the

Causes pseudo interrupt to level 3 National—Elliott 803 Computer." pseudo interrupt to level 7 for output. The input circuit of the interrupt register and control [5) Operators’ requests routiiio_ (1) Causes pseudo interrupt to level 4 ll (11 hit is present. 70 means 18 includes a patchboard 30 (FIG. 3). The (2) Causes pseudo interrupt to level 3 for conversion. 'l‘hen pseudo inter patchboard 30 has a left hand column of terminals to rupt to level 8 for output.

which the interrupt demand signaling means are con nected, and a right hand column of terminals which may

be permanently wired to various portions of the circuitry For convenience to the operator in

The problem of lockout is avoided in part in the case of routines demanded by C bit interrupt demand signals 75 to be described.