Charan Kumar. A

Charan Kumar. A Flat No: 569, Block B, Pocket 11, DDA Flats, Jasola Vihar, New Delhi-25.

E-Mail ID: [email protected] Phone: +91-9711968236

CAREER OBJECTIVE: To seek a challenging career and growth oriented position in VLSI Industry and working on challenging projects in line with my skills and abilities, enabling professional growth while being flexible, innovative and enduring.

EXPERIENCE: • • • • •

Total 3 years of experience in VLSI Industry. Working as Consultant - VLSI Design in TranSwitch India Pvt. Ltd., New Delhi from July 2009 to till date Worked as M.T.S. in TranSwitch India Pvt. Ltd., New Delhi from April 2007 to December 2008 Worked as Assistant Engineer in Silicon Interfaces (P) Ltd., Mumbai from May 2006 to April 2007 Worked as lecturer in RGMCET, Nandyal, Andhra Pradesh from July 2003 to November 2004

ACADEMICS: • •

M.Tech. in VLSI System Design from VNR Vignana Jyothi College of Engineering And Technology, Hyderabad affiliated to JNTU, Hyderabad, A.P. with 70% in 2007 B.Tech. in Electronics and Instrumentation Engineering from Rajiv Gandhi Memorial College of Engineering And Technology, Nandyal affiliated to JNTU, Hyderabad, A.P. with 65% in 2003

TECHNICAL SKILLS: • • • • • -

Operating Systems Modeling Languages Verification Languages Scripting Languages Simulator Tools

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Linux, Windows Verilog HDL, VHDL System Verilog, Verilog HDL PERL ModelSim, Synopsys VCS

PERSONAL DETAILS: • • •

Date of Birth Languages Known Marital Status

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15-07-1981 English, Hindi, Telugu Married

PROJECT #1: GPIO: (Nov 2009 – till date) Involved in GPIO testing. Some of I/O’s are control pins ands some are status pins. These I/O’s will be mapped to some registers in RTL. • VMM RAL based methodology • Development of local bus VIP • For verifying control pins first corresponding fields/registers will be written using RAL, then I/O’s will be sampled and compared with expected values • For verifying status pins first I/O’s will be updated, then corresponding fields/registers will be read using RAL and compared with expected values

PROJECT #2: 4Kb 1-Wire EEPROM: (July 2009 – Oct 2009) Involved in 4Kb 1-Wire functional verification. The DS2433 4Kb 1-Wire EEPROM identifies and stores relevant information about the product to which it is associated. This lot or product specific information can be accessed with minimal interface, for example a single port pin of a microcontroller. Data is transferred serially via the 1Wire protocol which requires only a single data lead and a ground return. •

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Made Verification Strategy, Test plan and Verification environment o SV based VMM methodology o Including Drivers, Monitors, Score board, Interfaces, Coverage and Assertions Development of OW Stimulus Generator VIP which follows 1-Wire write/read protocol Development of AHBMlite VIP which is subset of amba AHB bus master Development of OW Slave VIP which monitors events from 1-Wire Slave and does score boarding Development of Client VIP for collecting data from Buffer Manager Integration with RTL and other verification components Running simulation and debugging RTL

PROJECT #3: Buffer Manager: (May 2008 – Dec 2008) Involved in Buffer Manager functional verification. Core of BM is the Queuing/ Dequeuing Engine “BM_CORE”. Multicast is implemented as a co-processor function around the Queueing Engine. Device Specific Functions and Congestion Query Interfaces are implemented in Ingress Adaptor Block (INGA). • • • • • •

Made Verification Strategy, Test plan and Verification environment o SV based VMM methodology o Including Drivers, Monitors, Score board, Interfaces and Assertions Development of Fragment Generator VIP for driving data Development of Buffer Manager Agent Behavioral Model (which is a firmware block) for driving data/control to Buffer Manager. Development of Client VIP for collecting data from Buffer Manager Integration with RTL and other verification components Running simulation and debugging RTL

PROJECT #4: PCM-Subsystem: (April 2007 to May 2008) • • • • •

Made Verification Strategy, Test plan and Verification environment Development of Drivers, Monitors, Score board, Interfaces etc. Integration with RTL and other SV verification components Developed test cases using MIPS BFM routines Running simulation and debugging RTL

PROJECT #5: Bluetooth Baseband Controller: (May 2006 to April 2007) •

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Development of RTL modules Access Code Generator, Access Code Correlator, FEC Generator/ Checker, CRC Generator/ Checker, HEC Generator/ Checker, Payload Header Generator/ Decoder, Packet Header Generator/ Decoder using Verilog HDL Top module integration of RTL Involved in planning Test Strategy, Test Benches and Test Cases Implementation of Directed and Random test cases using Verilog HDL for Baseband Controller (System level), Access Code Generator, Access Code Correlator, FEC Generator/ Checker, CRC Generator/ Checker, HEC Generator/

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Checker, Payload Header Generator/ Decoder, Packet Header Generator/ Decoder Running simulation and debugging RTL (Charan Kumar. A)

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