Atari 800 Hardware Manual, Part2

There are a lotal of four players and four nlsslles. The fout nisstles n0aybe grouped together and used as a 5rh player, These objects are posltloned horlzontally by 8 horizonral posltlon regtslers ([PoS (X)). These reglsrers nay be reloaded at any rlne by rhe processor, allowlng an object to be repllcated nany tiioes across a horizontal TV 1ine. The shape of a player-nlsslle is deterElned by lhe data tn lts graphics reglster (GMF (X)). Players have independent 8 blt graphtcs reglsters. The four lllsslles have 2 blt regtsters (located wlthln olre address). These reglsters oay also be reloaded at afly ttne by the processor, although they ale usually changed during horlzontal bLank tlme. The data ln each giaphics reglster is placed on the display rhenever the horizontal sync couflter equaLs the corresponding horlzonta1 posltion tegister. The same data \1111 be displayed every line unless the graphlc reglsters are reloaded vrith Ire data. The player-ntssile graphlc registers rnay be reloaded by the mlcloprocessor (CRAF (X)), or arlonattcally fron nenory with dlrect meDory access (Dl4A) (see figure II.3). The prograr0ner lrusr place rhe objecr graphics ln Demory, I1'rlte the player-miss1le base address (PMBASE), and enable player-Eissile DI'A (DMACTL, GRACTL). The transfer of object graphlcs from rneuory to dlsplay ls then fully autornaric. PMBASEspeciftes the nost slgnificanr byte (MSB) of the address of the player-nissile graphics. The locatlon of rhe graphics for each oblect is deternined by addtng an offset to PMBASE*256 (decimal). The bytes betrseen the base address aod the ntsslle dara are not used by Antic, so they are available to rhe progranner. Only the five nost stgnificant bits oI PMBASEare used lrirh strgle-line resolutlon and the slx nost stgnlftcant blts are useil wlth two-line resolutior. This !0eans thar the location of the graphlcs 1n nenory 1s restllcted !o certaln page boundartes. Two-llne reso-Lution neans that each byte of data ls repealed for lqlo Ilnes. (see DI.{ACTL,blt 4). 540 (decinal) bytes (5X128) are requlred for rwo-ltne resolutlon and l28O byres (5x256) tor one-tine resoiur'ion, Each byte tn rhe player graphics area represenls elght ptxels whtch are to be displayed on the correspondtng llne(s) of rhe TV screen. A I indlcates that the player's color-lun ts to be dtsplayed in that ptxel. The graphics nay be anyrhtng, not Just rectangles like the ones in ftgure II.3. The player graphlcs may f111 the enttre hetght of rhe screen or they may be only a couple of lines high if the rest of the dlsplay dara ts al1 0's. Each byte 1n rhe rolssile dlsplay also represenrs etgi.rt plxels, trro pixels for each missile. Each ptxel nay be 1, 2, or 4 color clocks, and is deternined by the SIZE registers.

Plavfleld: Playfle1d ts always generaled by DMA. There axe four piayfields, each ldenrtfled by its own color-1um reglster and colllstott detection. Playfleld ls generated by lwo dlfferen! DMA technioues: neloory nap and character. Both methods provtde llsts of insE;ctlons 1n menory, independent of the player-r0issile generatlon.

player-Mlsslle Sase Address (PMBASE)= ),ISBof address. Resolutlon ls controlled by bit 4 of DI4ACTL, (hex) PMBASE*100 A.DDRESS Tvo-l1ne resolutlon (hex)

+180

OFFSET One-line resolutlon (hex)

+300

2

Mlss lle Nunber

I

TV SCREEN .21

M

+200

i-T--

I

r42 It l l t MO

I'

M3

r l I Pl

|.'i MI

I

r l t l

+600

t l |

I

|

l t

+700 P3

+400

; i

P2

rP3t

P2

+380

i i

i

I

+400 PI

f300

P0l

+400 PO

+280

I

t l l

I

l

Horlzonral Dosirlon ior each objec! 1s s e t lndependently by 8 horlzontal positlon regasrers.

+800

E a c h s e c t l o n o f m e m o r yn a p s d l r e c t l y onlo total height of TV screen. Object vertical posltion is deternined only by lts Iocatlon In lts section of deDory. one byre of oenory equals I or 2 television lines vertlcally,

Player-Mtssile Ver!1ca1 screen

Figure II.2

P L A Y E R - M I S S I L E

II.6

D M A

Unl1ke players and Elssiles, there are oo horlzontal posltlon regtsrers for playfleld. Each player can only have one byte of display per llne. Playfteld, on lhe othet hand, nay requlre up to 48 bytes per line because 1t can fll1 the entire wldth of the screen. T'here are three dlfferent playfield lrldths: narrow (128 color clocks), standard (160 color clocks), and wide (192 coLor clocks), The ddth 1s selected by stortng lnto DMACTL. The advantage of a rarrolrer nldlh ls that less R.A.lills reql.rlred and fener nachine cycles are stolen for DMA. The 0S graphlcs modes use the standald screen wldth.

g!9If3I-!19!: The dlsplay list is a sequence of display instructlons stored fir rnemory. These lnstructlons are eithe! one (1) byte or rhree (3) bytes 1ong. The dlsplay llst can be considered a dlsplay progran, and the Dlsplav Llst Counter that fetches lhese lnstluctlors can be thought of as (10 bit counter plus 6 bit base reglster.) a dlsplay progran counler. The dlsplay 1lst counter can be inirlalized by wrirtng ro DLISTIT and (or OS shadow registers SDLSTEard SDLSTL). once tnltlaltzed DIISTL. thls counler value ls used to address the dlsplay llst, fetch the lnstruc!ton, dlsplay one (l) to slxteen (16) lines of data on lhe TV screen, lncrenent the Dlsplay l,1st CounLei, fetch the next dlsplay lnstruction, and so on &.ltonatlcally irlthout Elcroprocessor control (see DLISTI and DIISTII). DLISTI and DLISTH should be aLtered only during vertlcal blank or when DMA 1s disabled (see DI,IACTL). Each lnstructlon deftnes the type (alpha character or nemory map) and (s1ze of blts on screen) and the locatlon of data ln nerory the resolutlon to be dlsplayed for a group (I to 16) of l1nes. Each group of lines ts ca11ed a dlsplay b1ock. TITE DISPI-AY I-IST CANNOTCROSSA lK BYTE MEMORYBOIINDARYUNLESS A JUMP INSTRUCTION IS USED.

DI,ISTI,

Flxed (6 btrs)

counter ( 1 0 b l t s ) DISPLAYLIST COUNTER

tr.7

Dlsplav opcode only,

Inslructlon Fornat: Each lnstruction conslsts of either or of an opcode followed by tiro (2) bytes of operadd.

lopcodel ------Slngle

Byte Display

an

Instructlon

-.t

l6'..d.-l \ l o p e r a n d| ) - - - - T r l p l e

-_-t

EyLe DIspIdy Instructlon

lOperand I.,

and placed ln the leqlggllgg The opcode ls al{ays fetched flrst (1 o! 3 bytes) Reelster. This opcode deflnes the type of lnslructlon and wll1 cause t\ro 'Iore bytes to be fetched if needed. If fetched, be placed ln lhe l4gggTI-.gSeg-9993!CI, these next rwo (2) bytes rrill Dlsplay I-1st ts a Jump). or ln the Counter (if the instructlon

Reglster (IR)r This register is loaded wlth the Dlsplay Instructton opcode of the current dtsplay 1lst lnstructlon. It cannot be accessed by the prograomer. There axe three bastc lypes oi display lts! dlrectly inslruc!1ons: blank, ju!0p, and dlsplay. Blank ( t-byte)

6lD5lD4 This lnslnrctlon is used to create dlsplay (blackground color). D7 t5 - D4 D3-D0

(3-bytes )

I to 8 blank llnes

on the

- display llsr InsLrucclon inEerrupt I 0-7 = r-8 blank lines = blank 0

D 7 l D 6 lX l X l 0 l 0 l 0 Thls lnslructlon is used to reload the Dlsplay List Counter. The next two bytes speclfy lhe address to be loaded (LsB first). D7 D6 D5-D4 D3_D0

I = d t s p l a y . I . L s cl n s c r u c t l o n i n t e r r u p t 0 = junp (creates one blank ltne on dlsplay) "_i' _:t.I end of nexl vertlcal X = don't care I = junp

Dlsplay (1 or 3 bytes)

blank

D 2 I D lI D O Thls lnstructlon display block.

specifles

D7

I = dlsplay list

n6

n=l

D5 D4 D3-D0

the type of dlsplay

for

the next

inEtructlon inteErupt

hvts.i^cfr,r.rlon

I - 3 b y L e I n s c r u c c l o n ( r e l o a d M e m o r ys c a n C o u n t e r uslng address ln next lwo bytes, LSB ftrst). = verttcal scroll enable I scroll enable I horlzontal = (memory or character map node 2-F dlsplay pages). following see II.8

.rr

x

F H

ts.o6
r @ 6 < 1 4 ( ) a F r N.o6
;

Fco6
Fco6
6 t s @ o < F O O t s l

t t l --! -----1

| I

| I I

,

Btt 7 of a dtsplay 1lst tnstructlon can be set to create a dlsplay list tnterrupt 1f btt 7 of NMIEN 1s set. The dlsplay 11s! lnternrpt coile can change the colors or graphics durtng the nlddle of the TV dlsptay. The lype of lnterrlpt ls derernlned by checklng NMIST. NMIRES clears NMIST, The current 0S will vecror through VDSLST(Itex 200 and 2Ol) to lhe user's dlsplay 1lst lnterrupt rourine. See the OS nanual for proarau.olng detatls. Blts 5 and 4 of a dlsplsy type of dtsplay llst inshuctlons are used to enable vertlcal and horlzoflta1 scro111[g. The amount of scro1llng depends on the values ln the VSCRoI and I{SCRO],reglsters (to be descrtbed later).

Meoorv Scan Counter! Thls counter is not dlrecrly accesslble by the progtaEner. It 1s loaded wlth the value in rhe last 2 bytes of a 3 byre (non-Junp) 1Tlstruction. Thls counter pohts to the locarlon (address) ln mernoryof data ro be directly displayed (Eemory nap dtsplay) or ro the locatlon of characrei rane strlngs to be tndtrectly displayed (chalacter dlsplay). A single byEe lnstructlon does not reload thts counter. Thls lnp11es a contimratlon In rremory of data to be dlsplayed frorn that displayed by the previous instructlon. Stnce thls counter really conslsts of 4 btts of reglster and 12 of actual counter, a conttnuous menory block cannot cross 4K bvte rnenorv boulldarles. unless the counter ls reposltloned wlth a 3 byte Load Meinory Scan Counter instrucllon. l,lSB thlrd hwrc

byte

of 3 byte

lnorh!.r

t

LSB Second byte of 3 byte lltstrucllon

l^n

t

t

l

1 1 0

t

t

t

15l 14l 13l r2 Flxed (4 btts)

l

t

t

2

t

t

l

3 ' 2 t 1

Counter ( l2 bits)

Menorv Map Dlsplav Instructlons: Data 1n nenory (addressed by the Memory Scan Counter) is dlsplayed dtrectly $hen executlng a nenory (btt) nap dlspfay lnstruction. As data is betng displayed 1t ls also stored 1n a shlft reglster so that it can be redlsplayed for as nany TV 1lnes as required bY the lnslructlon.

1 r .l 0

Menory Scan Counter Addresses each byte

Mernory one l1ne worth of rdenory 1s loaded tnto the shlft reglster

Shlft

reglster

data 1s dlsplayed

for

four Tv scan 11nes ln thls

exarnple.

In Instructlon Regtster (IR) dtsplay nodes 8 through tr', one or two blts of nemory are used to spectfy lrhal 1s to be dlsplayed on each plxel of the screen. Plxel slzes range froE l/2 clock by I TV llne to 4 cLocks by 8 TV ltnes. The 0S and BASIC support nost of these grephlcs nodes (BASIC GRAPITICS comand). Tvo nodes, C and E, are not supporled by the OS. Ttese nodes have rectanguLat plxels, lrhlch are approxlmately tlrlce as wide as they are hlgh, In IR Eode F, only one color (CoIPI2) can be dlsplayed. T\ro dlfferent luElnances are avatlable. If a blt 1s a zero. then the lunlnance of the correspoodlng plxel cones fron COLPI'2. If the btt 1s a one, them the lunlnance ts deterntned by the contents of CoLPFI (abbrevlated to Pf'l). In lR modes 9,8, and C, two different colors can be displayed. A zero lndlcales background color and a one hdlcates ?f0 color. T1le dlfference between the varlous modes 1s ln the slze of the plxels. In IR modes 8,A,D, and E, two btts are used to speclfy the color of each ptxel, This al1ows four dlfferent colors ro be dlsplayed. l{olrever, only four plxels can be packed llrto each byte, lnstead of elght aB in the prevlous Ecdes. The bi! asslgnnents are shoqrnbelor.

SHIFT RECISTER

7

6 t 5 4 1 3 2 t t

0 | 7

6 t 5 4

2 t t

0

2 blts foro one plxel

II. I1

l4eoorv }lap Dlsplay

oS I lcolors Plxels per and l1nst. I per srd. BASICIRes. I uode odeslHEx | | Line | | I 40

ltlodes

I Blt I lBytes Iscen lColor I per Btts lvalueslcotor I lLlnes I clocks I I Rec. lstd. I per I per lper I tn I ritre lPtxel lPlxel lPlxellPixel lselect | BAK | 100 | | I PFO OI l0 8 1 4

I

10

PT'I

101 lr0

l?30 lPrl

ro | 4 I

s

l A l

l

4

t

l 8 0

l

I 160

I

2

I 160

320

t

t

BAK

I

?r0

00

BAK PTO

I 0l I r0

?r1

0l 10

I

t

0

40

t

l

rt. t2

I Prl IGIIM)

Character Dlsplav Instructlonst The flrst step 1n ushg the character map dode 1s to cxeate a character set ln neEory (or the bu1lt-tn OS character set at hex E000 nay be used). The character set contalns elgh! bytes of !g!g for the graphlcs for each character. The neantng of the data depends on the hode. The charecter set can contaln 64 or 128 characters, also depending on the oode. The USB (l,losr Slgntftcant !yte) of rhe address of the character set ls stored ln CHBASE(or the OS Shadon CHBAS). Only the most slgntftcant s1x or seven blts of CHBASare used (see CIIBASE descrlptlon ln sectlo[ III). The other one or two blts and the LSB of the addless are assuued to be zero, so lhe character set fitst start aE an acceptable page boundary. Tte dext step ls to set up the dtsplay 11st for the destred node. Then the actual dtsplay 1s set up. Thls constsrs of a strlflg of chatacter Each nane takes one byte. The last 6 or 7 bits of the lgggg or codes. nene selects a character. For a 64 charactet set, the naEe would range froE 0 through 63 (decloal). For a 128 characrer ser, rhe range \rould be 0 through 127 (declnal). The upper one or rwo blts of rhe nane byle are used to speclfy the color or orher speclal tnfornatlon, dependtng on the Character nanes (codes) are fetched by the neroory scan counter, and are placed ln a shtf! reglster. On any glven ltne of dlsplay the shifr reglster rotates, changing only the nane portlon of the character address, as shol'n belon. After a full 1lne of character data has been dlsplayed the line counter v111 lncrenent. The next l1ne agaln addresses all characrers by na.oe for lhat ftne rnrmber. In 20 character f'er ltne modes the seven nost slgrlflcant birs of CIBASE are used. Th{s requlres that the charactet set !o statt upon a 512 byte Eenory boundary. The set Inlst conratn 64 charcters, 8 bytes each, glvlng a rotal of 512 bytes for the The 40 character per ltne aodes use the slx most slgnlficant blts of CEBASE,forclng the character set to start on a lK byte rnemory boundary. The aet rrust have 128 charactels of 8 bytes each. Thls gives a total of 1024 bytes for the set.

I ltex lCode

Graphlcs Mode

I chars.

Nunber of

laytes

lNunbe.

L tne

f

4

lnytes l l n Char Set

l

I28

II.I3

Character Dlsplay (20 Characrer per llne

Internal codes for mode exarnple)

Codes (naines) Stored ln Shlft Register

shlft Resls!er Color Reglster Select

Addr:ess portlon Character nane

of

Llne

Character Data Address

Char:acter Set 1n llemory

Addresses data in

and displays TV

on the

Color assigned by color reglsEer sefected

r1.14

0 I TV 2 Scan 3 Lines 4 5 6 7

There are slx charcter inap modes, IR rnodes 2 through 7. Modes 2,6 and 7 are supported by the OS and BASIC (GRAPHICS0,f and 2). In IR dodes 6 and 7, the upper two bits of each character Iraoe selec! one of four playfleld colors, For each 3e!g bit that contains a one, tfre selected playfleld color is dlsplayed. For each zero data btr, the background color ts dtsplayed. The four characler colors plus the background color glves a total of flve dlfferent colors. the loode 6 characters are elght lines htgh and the dode 7 characters are slxteen lines htgh (each data byte ls dlsplayed for two ltnes). In IR nodes 4 and 5, each character ls only four plxels i{de lnstead of elght (as ln the olher nodes). Two btts per pixel of data are used to select one of three p1ayf1eld colors, or background. Seven eqEg bits are used to select lhe character. If the most signlftcant nane blt ls a zero the[ data of 10 (binary) selects P]I. If the nane blt 7 1s one, rhen data blts of l0 select PF2. Thls nakes it possible to dlsplay l\no chalaclers wlth dlfferert colors, uslng the same data but differenr nane bytes. .-

\-

In IR roodes 2 and 3, each plxel is half of a color clock tn width. This makes lc posslble to have forty etght-pixe1-wtde characters in a standard \ddth 11ne. These nodes are slnllar to r0enory loode F h that two lur0inances can be dlsplayed, but only one color 1s available a! a tllle. In IR mode 3, each character ls l0 Unes high. This nakes lt posslble to deflne loner case characters w_ith descender€. Tlle las! fourlh of the characte! set (naEe blts 5 and 6 equal to one) is lowered. The hardware takes the flrs! !!r0 dala bytes and noves then to the botron of the characte!, displaylng two blank l1nes at the rop of the character (see next page). In IR oodes 2 and 3. blt 7 of the characler narne ls uaed for inverse If vldeo or blanklng. This is controlled by CHACTL(character co$tro1). blt 2 of CHACTLls a one then all of the characlers will be dlsplayed upslde dolrn, reeardless of node, If CEACTLbil I is set, lhen each be displayed in inverse character \.rhich has blt 7 of 1ts nane set l{lll blt 0 is set, then vtdeo (the luBlnances will be reversed). If CHACTIeach character whlch has blt 7 set w'l1l be btanked (on1y background wil be dlsplayed). Characters can be blinked on and off by settlng nane bil 7 to I and loggltng CEACTI-bit 0. Inverse vldeo and blank apply only to IR modes 2 ard 3. If both inverse vldeo and blank are set then the character w111 appear as an lnverse vldeo blank character (solid sqrare).

register are Delectlonr 60 bils of colllslon Ilardware collislon provlded to delect and store overlap (hits) belreen players, misslles and playfleld. These collislons can be read by the Dicroprocessol fton D00I. There are no btts for nisslle to nlssile addresses D000 thlough co11islons. 16 16 16 12

bits btts blts bits

for for for for

ulssile to Playfield Player to Playfield }Ilssile to PlaYer Player to Player (P0 io PO allr'ays leads as zelo,

e!c.)

and lhe l/2 clock chalacter The l/2 clock lleDory nap node (1R code llll) (IR type 2 coLltsions and w111 node codes 0011 and 0010) are both playfleld colltsion registers. be slored in btl 2 of the playfietd

T1.15

IR l,lode 3-Upper and l,ower Case

Upper Case

Data

Act\ra1 Dlsplay

E II.I6

Map Displav

Chalacter

Modes

I os I I l c h a r s . l s c a nl c o l o r l D a t a l c o l o r I B i t I I and lrnst.loolors I per lllneslclockslBtrs lselect lvalueslcolor Ista. lper lper lper lattsrnl 1Il lRec. l B A s r c l R e lsp. e r lModeslttEx I Mode lLine

r

o

t

r

r

2

r

I4

4

lchar.l?txel lPlxell Naroe lDara lselect

t

0

l

8

l

t

:

l

l

t

-

t

|

o

l r

l

I PF2

l

l P r l 0 I

lB{t 7

01 l0 1I

?FO PTI PF2

lBlt 7

11

PF3

lBtt 7

00 01 l0 ll

BAK PFO PFI PF2

II

PF3

l ' o I I

l = 0

I I

lBit 7

0 00 OI IO

I I I

! o

|

|

|

|

|

|

rr.17

I PFT

|

00 0I 10 1l

BAK PFO PT'I PF2 PF3 BAK

Pr'0 I

I

?FI PE2 L Pr'3

Vertlcal and llorlzontal Flne Scrolllna: ?layfleld objects are dlfflcult to Eove srnoothly. Me.oory nap playfield can be rnoved by rewrttlog secrlons of nenory. llowever, thls 1s extreEely tlne-consunlng if large secrlons of the screen rfils! be noved snoothly. Character playfleld oblects can be 6oved easlly ln a jerky fashlon by chaoglng the nenory scan counter. Ilorever, thls results 1n a large posltlon junp fro.n one character posttion to another, not a smooth Dotlon. For thls teason hardnare reglsters (VSCRoLand HSCROI,)and counters are provtded ro a1low snooth horlzonlal or vertlcal notlon, up to one character wldth horlzonrally and up to one character helgh! vertlcally. After this ouch snooth xnotion has been done by lrrcreaslng the value in these reglsters, nenory 1s reErltten or the nenory scan counter ts nodlfled and sDooth .0otlon 1s resuned for another characrer distance,

Vertlcal ScrolllnA: A zone of playfleld on the screen can be scrolled upward by uslng VSCRoLand bir 5 of rhe dtsplay llst lnslructlon, The dtsplay blocks at the upper and lower boundarles of rhe zo[e Eu6t have a varlable verElcal slze. In particular, the flrst dlsplay block rrithln lhat zone trlist be shortened froid the top, and the last dtsplay block ftrst be ehortened fron the botton (t.e. not all of the top and botton blocks dll be dlsplayed). The vertlcal dinenston of each dtsplay block 1s controlled by a 4 btt counter wlthtn the ANTIC, called the 'De1ta Counter' (DCTR), Wlrhour vertlcal scro1l1ng, lt starts at 0 on the firsr line, and counts up to a standard va1ue, detelnlned by the current dlsplay lnsrruction. (Ex: for upper and lolrer case text display, the end value is 9. Ior 5 color character dlsplays, it 1s 7 or 15,) If btt 5 of the lnstructlon renalns unchanged between consecutlve display blocks, then lhe second block 1s displayed 1n the normal fashlon. If blt 5 of the lnstructlon goes fror0 I to 0 between two consecutlve display blocks, the second block \'111 start tu{th Delta = 0, as usual, but r'llf coun! up until delta=VSCROL, lnstesd of lhe standard value. Ihls shortens that dtsplay block fron the botton. To deftne a vertlcally scrolled zone, the most dlrect melhod ls to sel blt 5 to I ln the first dtsplay instnrctlon for that zone, and 1n all consecutlve blocks but the lasr one. If rhe VSCROLregisrer is no! reFrlttren on the f1y, thls results ln a rotal scrolled zone that has a conslan! IujDber of 11nes (provtded that the VSCROTvalue does not exceed the standard lndlvidual block stze). If N 1s lhe standard block size, che rop block will be N-VSCROLl1nes (N > VSCROI ), and the lasr block wtll be VSCROL + I 11nes: (N-VSCROL)+ (VSCROL+ 1) = 111. Shown on the followtng page 1s an exanple of a scrolled zone, top block, for 8 VSCROIvaluesforN=8. Horlzonlal

scrolllns

is descrlbed under HSCROLln sectton

II. T8

IIt,

o I

2

2 5

I

T1 l i

3 5

7 7

1 -l I

2

-t

I

-,

z

I

I

z

2

l

7

J I

z

2

5

3

5 7

7

I

- 2

fz

I 1 3

z 3

5

T

5

I

I

2

3

5 7 I

I

F

2 3

2 3

2 J 4 5

5

S+np19 Dlsplav Llst Exanpte: BASIC starls out in os graphlcs . _ . node O whlch dlsplays 40 characters across by 24 ro\rs, Thls 1s IR node 2 nlth a slandard screen ntdth. OS sets up the allsplay lts! near the top of .The R-Al1nlth room for the character nanes at the top of UU. On a 32 K_byte nachtne, the dlsplay l1st would start at hex 7CiO. The flext three bytes are hex 70's !o create 24 blank 1i[e6. The next byte 1s a hex 42, The 4 teUs the hardware to reload the Bernory scan cou;ter wlth the follor,lng address (7C40). Thts ls rhe aildress of ih. d.t. to be dlsptayed. The 2 te1ls the hardware to dlsplay one line of IR noale 2 characters. The next 23 bytes specify 23 nore ltnes of rooile 2 characters. Eex 4t is rhe code for Junplng and walttng until the end of the nex! verllcat btank, The address to Junp to ts 7C20, rhe start of the alisplay llst. The flext 960 bytes are the 11st of characlers to be dlsplayed, 40 bytes per l1ne. The oS lErst set up the dlsplay 1lsr pornter (oirsiu ;nd DLISTL) to the atattlng address of the dlsplay 11st (7C20). It also sets CIBASE to the MSB of the address of rhe character ser (EO). Thls ls a slEple exardple because orlly one node ls used and the roenory scan counter 1s only loaded at one point. It ls posslble to have different n o d e s o n d t f f e r e n t l t n e s , c h a n g e c h i r a c r e r e e t s and colors, etc., as shor,rn 10 the example tn Sectlon IV.

II.19

2 J

7

5

I

z

'7

5

l

5 5

5

t:

T

7

0S Mode 0 Dtsplav Ltst Ad.i raee

ahav\

(40 chars x 24 1lnes) (hex)

Data

70'\ 7 0 1 24 blatrk l1nes 70) 4 2 ) reload meroory acan counter r.Ith 4 0 I IR roode 2

7C20

7C)

i)

; l

t

' . ( 23 nore IR mode 2 tnstructions

2

l

i -))

4l

20 1

Junp back to 7C20 and walt for end of vertlcal

b1ank.

1C)

l

7C40

)

960 bytes of dtsplay (character naoes)

data

cvcle countlns: As explatned prevtously, the ATARI 800 5502 ndcroprocessor runs at a rate of 114 machine cycles per Tv ltne (1.79 MHZ). There ate 262 Ilnes per TV frane and 60 frames per second on the NTSC (tls) Bysren. (The PAL (Europeor) systen ls dtfferent. See the sectlon on NTSCvs. ?AL.) 1n length to 2 color clocks. There Each nachlne cycle ls equlvalert are 228 color clocks on a TV 1lne. The highest resolutlon graphtcs nodes have a ptxel slze of Il2 color clock by I TV Une. Ilorlzontal blank takes Thls 1s !,'hen the bean returns to the left edge of the 40 nachlne cycles. A walt for Sync screen 1! preparatlon for dtsplaytng the next TV 1lne. (WSYNC)lnstructlon stops the 6502. The processor ts restarled exactly 7 uachlne cycles betore the beglnnlng of the next Tv 11ne. lhe prograo can for thus change graphlcs or colors durlng horlzontal blallk lfl preparatlon the next 1ine, The ANTIC chlp steaLs cycles fron the 6502 tr order to do memory xefresh and fetch graphtcs data ehen needed. The general rule to r:emenber one Dachine cyc1e. If a ls that each byte fetched fron nernory re$lres extends over several llnes then the data dlsplay Ilst BeEory nap inslruction only fetched on the flrst 1lne. MeEory refresh takes 9 cycles out of ls graphlcs mode. Menory every l1ne, unless pre-enpted by a htgh-resolutlon refresh conllnuea durtng vertlcal b1ank. Bode l,rsstle Dl4A takes one cycle per l1ne ln the one-1lne resolutlon node. l,Ilsslle and one cycle every'other 11ne ln the tlro 1lne resolution dolng playex DMA. l{owever, lf player DMA ts DMA can be enabled rlthou! enabled lhen olsslle DMAn111 also be done (see Dl4AcTL, GMCTL blls). dependlng on the Player DMA iequlres 4 cycles every one or tlro llnes, resolution used. II.20

7C40,

Each fetch of a dtsplay ltst byte takes one cycle, are required for a three byte tnstructlon.

so three cycles

Player/mlsslle and display list lnstructton fetch DMA take place during horlzontal b1ank, tf they are required for the next llne. In nemory nap modes, the graphlcs dara ls fetched as needed rhroughout the first l1ne of the display hst instruc!1on, lhen saved by ANTIC for use ln succeedlng l1nes, In character nodes, the character codes are fetched durlng the first ltne of each ron of characters, along rrtth the graphics data needed for that llne. Or the next ltnes, only ihe graphlcs dala iB fetched, slnce ANTIC renembers the character codes. In lhe 40 x 24 character rdode, &{th a standard screen wtdth. nost of the cycles durlng the top ltne of each row of chalacrers ale requrleal to fetch the character codes and data, so rhere ls only rlne for one oenory refresh cycle lnstead of the usual [1ne. ]-ess DltA ts requlred wlth a narro, screen wldth so two Denory refresh cycles I'ould occur in thls case. The menory refresh ls done fast enough !o nake up for the lost cycLes tn the hlgh resolutlon rnodes. Once rnenory refresh slarts or a 1lne, lt occurs every four cyclea unless pre-enpted by Dl4A, A11 lntelrupts reach the 6502 near rhe end of horizontal btank. Wlth standard o! narrow screen lrldths, refresh DMA starts after the end of horlzontal b1ank. The time at which ANIIC does cycle stealing ls deterndnlstlc, but depends on the graphics node, screen {1dth and nhether or not horlzontal scrolling 1s enabled. Horizontal scrolling reqrtres extra graphtcs data: see I{SCRoL. ANTIC does horlzontal scrolllng of an even rllnber of color clocks by delaylng the tlne at which 1t DMA'S the data. To do an odd nunber of color clocks (which lnvolves half of a nachtne cycle), ANTIC has a one color clock inlernal delay. Theoretlcally, it ls possible to write a program vhlch changes graphlcs or colors rron the flyi, t.e. during the nlddle of a TV llne. Iiowever, I'lth all the DMA going on, rhe cycle counting gets to be qulte conpltcateal, ard ls beyond the scope of thls roanual. There are a mlnber of delays assoclated with the display of graphtcs. These occur in the ANTIC and the CTIA, The ANTIC sends data to the CITA which adds in lhe color infornatlon. Thus the rlnlng for changing colors on the fly is dlfferenr fron that for changtng graphlcs on the f1y.

II.2I

Itortzontal

Blank DUA Tlntne

When DMA ts enabled, cycles are slolen at the tiEes shown belol'. End of Horlzontal BIank_____J Lprevrous+l ll,lne | | 20 nachtne cycles (40 color clocks)

-_

.r - v^ tr e r-r e s n

I,ISYNC

cycres. char, and graphlcs dara DMA (depends on orr.hl.

m-,{ c )

Interrupt Address DMA (3-byte dlsplay llst lnstrucrion) Player Dlsplay 1ls t lnstruction fetch DMA Mlsslle Dl,{A

fhis exar0ple uses the 40 char:acter by 24 l1ne Cycle Countlnq Exanple: dlsplay l1st given on page II.24. This dlsplay lisr 1s 32 byres long so dlsplay list DI,IAtakes 32 nachlne cycles. It takes 960 cycles to Dl'lA rhe characters and 8*960 to DMA the characrer da!a. The refresh DMA takes 9 cycles for each of 262 1ines, except for the 24 tines wnere the characters are read, where only I refresh cycle occurs.

DMA descrlptlon dtsptay llst chalac!ers character data refresh !ota1

Machine

cvcles

32 40x24 = 960 950x8 =7680 262xe-24x8 =!!!! 1 0 8 38

Thus tbe total DMA per frane ls 10838 nachine cycles. one fraroe 1s 262 llr\8 with 114 machlne cycles per ltne for a total of 29868 nachtne cycles per fraDe. Thus 362 of each frarne is required for DMA tn 0S graphlcs node 0.

NTSCvs. ?Al, Svstens: There axe tr^roverslons of the ATARI 800: the NTSC (Untted States T,V. slandard) and PAI- (one of the European T.V. standards). The PAL systeu has been destgned so that mosl programs wlll lun wlthout belng modlfled. Ilowever, sone dlfferences nay be notlceable. There 1s a hardtrare reglscer (PAL) vhich a progran can read to deternlne which type of system lt Is runnins on and adjult;ccordlngly.

..__ -

The PAL T.V. has a slo\rer frame rate (50 Hz. instead of 60 t{2.) so gaues lflll pAL has roore T.V. be slot'er irnless an adlustneflt is oade. 1lnes per frax0e (312 lnstead of 262r. T\e Arart 800 harilr,rare cordpensates fot thts by adding extra 11nes at the beglnnlng of vertlcal blank. Display llsts do not have to be altered. llor,rever, thelr actual vertlcal heisht \1111 be shorter. PAL ATARI 800 colors are simtlar to NTSCbecause of a hardware nodlflcetlon.

B.

POIGY

Audlol Ttere are 4 seni-tndependent audlo channels, each lrith its o\rn frequency, nolse, arld volune control. Each has an 8 b1t "dlvtde by Ni, frequency dlvider, controlled by an 8 blt regtster (AUDFX). (See andlo-serlal port block dlagran.) Each channel also has an 8 btt conrrol regtster (AUDCX) \rhlch selects the tlolse (poly counler) conrent, and the volune. Irequetcy Dlvlders: A11 4 frequency dlvlders can be clocked slmrltaneously fron 54 KHZ or 15 KHZ. (AUDCTLbtt O). Ire$ency dividers I and 3 can alternately be clocked from 1.79 MHZ (AUDCTLbits 6 and 5). Dlvlders 2 and 4 can alternately be clocked \di!h the output of dividers I and 3 (AUDCTL blts 4 and 3). Thls a11on6 rhe followlng oprlons: 4 channels of 8 bits resolutlon, 2 chanrels of 16 btt resolutlon, or I channel of 16 btt and 2 channels of 8 blt.

Poly Nolse Cou[ters: There ale 3 polynoEial counters (17 b1t, 5 btt and 4 blt) used !o generate random nolse. The 17 btt poly counter can be reduced to 9 bils (AUDCTLblr 7), These counlers are ;11 clocked by 1.79 MEZ. Thel! outputs, however, can be sampled tndependently by the four audlo chamels at a rate detelnlned by each channel,s frequency dlvlder. Thus eech channel appears ro contatn separate poly counters (3 types) clocked at lts olrn frequency. Thls poly counter noise saopllng is controlled by blts 5,6 and 7 of each A1IDCXregtster. Because the poly counters are senpled by the 'rdlvtde by N[ frequeocy dtvldet, lhe output obvlously cannot change faster than the saopllng !ate. IIr these nodes (poly noise outputted) the dlvlders are therefore acting asirlow pass,'filrer clocks, allo\rlng only the low freqrency noise to pass. The output of the notse control circult descrtbed above conststs of pure tones (sqrare rrave type), or polynonlal counter noise at a rnaxlurE frequency set by the ridtvide by Nri countet (1o\r pass clock). This output can be routed through a high pass ftller 1f desired (ALIDCTLblts 1 and

rr.23

Audio Nolse tr1lters:

trreqrelrcy Notse Frequency Any chanflel

nolse

output

(vtthout

htgh pass fllter)

voL chennel - b y N

fctaonet t

,)

o' " lL-

I v

f!equency Chendef I output

(wLth high pass f11ter)

,J

channel ;\ (or3& -bvN

Freqtrency Chamel

2 output

(!?-lth blgh pass filter)

Clock

Elah Pass Fllters: The htgh pass filter conststs of a "D'r fllp flop attd an elcluslve-OR Gate. Ihe noise control clrcult outpu! ls sanpled by thls fltp flop dt a rate set by the "Aigh Pass" c1ock. The input and output of the lllp Flop pass through the excluslve-oR Gate. If the fllp flop lnput ls changing mrch faster than the clock rate, the stgnal !1111 pas8 easlly through the excluslve-OR Gate. l{owever, lf lt is Lower tha[ the clock ra!e, the f11p flop outpul w111 tend to foUow the loput and the two excluslve-oR (ll or 00) gtvtng very 11!t1e drtput. Gate lnputs lll1l nostly be tdenttcal Thls glves the effect of a crude hlgh pass fllter, passhg nolse whose olnftolid frequency 1s set by the htgh pas8 clock rate. Only channels I and 2 have such a htgh pass ftlter, The hlgh pass clock fo! chatlnel I cones fro.n the chanfle] 3 dlvlder. The hlgh pass clock for channel 2 cones froo the channel 4 dlvider. Thls filter 1s lncluded ooly if bit I or 2 of AIIDCTL ls true.

A volune control clrcult ls placed at the output of J9Jtg9_994!gf: each chennel. Thls ts a crude 4 blt dlgltal to analog coDverter that allons selectlon of one of 16 possible oltput current 1evels for a loglc true audlo lnFrt. A loglc zero audlo ltlput !o thls volune clrcul! al\rays glves an open clrcult (zero current) outputt The volulle selecllon 16 codtrolled by bits 0 thru 3 of AUDCX. "voluxoe control on1y" node can be lnvoked by forcing thls clrcult's arrdlo input true l.lth blt 4 of ALTDCX. In thla mode the dlvldels, nolse counters, aod fllter clrcults are all dlscoonected fron lhe chaIlnel outpu!. Olrly the volune control blts (0 to 8 of AUDCX) determlne the channel output current. The ardlo output of any chennel can be conpletely turned off by wrltlng zero to the volude control blts of AUDCX. A11 ones slves rnaxfid]n volur0e.

c.

SERIA]- PORT

The serlal port coflslsts of a serlal data output (transolsslon) 1lne, a ser1a1 data lnput (recetver) 1tne, a serial output clock 1lne, a bl-directlonal serlal data clock 1lne, arld other rolscellaneous control lines descrlbed ln the operatlng Systen Manual. Data ls transDltted and recelved as 8 btts of serlal data preceded by a logic zero start bit, and succeeded by a logtc true stop btt. to lhe baud Irput and outpu! clocks are g$g! (blt) ra!e, not 16 tines baud rate. Transnltted data changes qrhe[ the oulput clock goea true. Recelved data ls sanpled rhen the lnpu! clock goes

Ttre transElsslon sequence beglns lrtlen the processor Sg4e1_9.g!!g9: (sERoUT)(see peralle1 \alrltes 8 blts of dara into rhe serial output register audto and sertal port block diagran). vhen any previous data byte trensnisston 1s flnlshed new data from the hardware a'111 artonatically transfer (SERoUT) to the oltput shlft reglster, processor lnterrupt the to lndicate (SERoUT) (ready next byte of an empty reglster to be reloaded wtlh the ltrlth data), and auto!0attcally serlally lhe shlft reglster contenls transnl! processor and start-stop b1!s attached. If the responds to lhe interrupt, reloads SERoUTbefore the shlft reglster 1s conpletely transnltted, the serlal transnlssion w111 be soooth and contlnuous.

r1.25

Output data ts nornally transnitted as loglc leveLs (t4v=lrue ov=Fatse). Data can also be transmirred as two lone lnforDatlon. Thls rdode ls selected by bit 3 of SKCTI-. In rhls node andlo chanoel I 1s transroitled 1n place of channel 2 mlst be loglc true, and audlo channel 2 1r place of togic zero. the lower tone of the tone Pair. The processor can force the data outpu! ltre to zero (or to audlo channel 2, lf 1n two rone node) by settlng btt 7 of sKcTL. Thls 1s requlred lo force a break (I0 zeros) code tlansolsslon.

Serial Output Clock: The serial output data always changes when the serlal output clock goes true. Tte clock then returns to zero 1n the cente! of the output dara blr tlne. The baud (bil) rale of the data and clock i3 deternined by audlo channel 4 audio channel 2, or by the lnput cLock' dependtng on the serlal dode selected by btts 4, 5, and 6 of SKCTL. (see charl at end of thls

sequence beglns vhen the hard\rare has The recelvlng SSJjg!_!.!!g.!.: This received a conplete 8 blt serlal data i^rord plus start and stop blts. data ls autoroatically transferred !o the 8 bit paraLlel input teglster (SERIN), and the processor ls lnterrupted to indlcate an input data byle and ready to read ln SERIN. The processor nust respond to thls lnterrupt' read SERIN, before the next lnput dala vord receplion is coaplete, olherwise an input data nill occur. This over-run wtll be tndtcated by btt 5 of SKSTAT(if bit 5 of IRQST is not RESET (true) before next lnput conplete) ' and neans input data has been lost. Thls blt should be lested whenever SERIN ls read. Blt 7 of SKSTATshould also be rested to detec! frame errors caused by extra (or nlsstng) data bits.

Direct Serlal Input: The serial data lnput line can be read directly by readtng by the rnlcroprocessor 1f deslred, ignoring lhe shlft reglster, b1I 4 of SKSTAT.

Bt-Direclional Clock: This clock ltne is used lo elther recelve a or recelved clock fron an external clock source for clocking iransnitted the dala, or is used to supply a clock lo e).texnal devlces indlcatlng transnit or receptlon rate. This clock llne d1lectlon is deternined by the serial rnode selected by bils 4, 5, and 6 of SKCTL. (See node chart at the end of this section.) Transaitted dala changes on the rislng edge of edge of thts clock. Recelved data 1s sadpled on the lfalling thls clock. Asvnchronous Serlal Input: Unclocked serial dala (at an approxlllately known (+5%) rate) can be received 1n the asynchronots modes. The recelve (input) shift reglster is clocked by audio channel 4. channeLs 3 and 4 should be used togelher (AUDCTLbit 3 = l) for lncreased resolutton. In asynchronous nodes, channels 3 and 4 are teset by each start blt at the beglnning of each serial data byte. This allows the serial dala rale to be sl lghtly different from the rate set by channels I and 4.

Serlal Mode Control: Thete ate 6 useful rnodes ( o f t h e p o s s i b l e 8 ) cortrolled by bits 4, 5, and 6 of SKCTL. These are described on the next page. Note that two lone output (bit 3 of SKCTL) Eay be used 1n any of these . nodes except for the bortoE pair. Thts is because channel 2 is cne output lransntt rate and 1s therefore nor available for one Note that

the output clock rate

is tdentlcal

!o lhe outpur dara rare.

Mode Control Force Break

p 7l p 6l p sL D 4 l D 3l D 2l D rI D O

S(CTL REGISTER Pot scan and keyboard

CTRL

Two Tone Control Mode Control

o"t I

Q"t I D4 R a t

Blrs

A-asynchronous

r n l

B1-Dir

c1o

trrans. & R.".in; ;;i;;-;;ali linput I chan l 4 I lnput

lext I

t

l

l c h a nI

4 4

cr{4 |

CII4

cI{4

1 4 l4 lr lcn4 | cH4 lcran I ctran 1 2 | 2

CH4

Chan

Input

ft'o lone (bit3)

lTrans. & Recetve lChan. 4. chan. Direc clonal clock ttne.

b

v

Chan 4

R a t e S e t by Chan. 4 lTrars. Rate by External lRecelve C1ock.

lTrans. rate set by chan. lRecleve rate se! by chan. 4 out on B1-Dlrect. CIo lTrans. Rate set by Chan. (chan 3&4) lceive async. lClock nor used (Tri-srare

not useable ln these nodes 11,27

l

on 81- I

lNot UsefuI

0rrI

Chan 2

Trans. rale set by external Receive asynch. (ch. 4) lcfock,

Not Useful

lnpu t

Chan 2

Also lnrernal lexternal clock. lock phase reser to zero.

2. ReBi-Dir.

D.

INTERRUPTSYSTEU

There are t\ro baslc types of lnterrupts deflned on the r0lcroprocessori NMl (non naskable lnterrupt) It is recoomended and IRQ (lnterrupt request). rhar a rhorough understanding of these inter.rpt types be acqulxed by reading all chapters concernlng lnterrupls in the 6502 microprocessor progranmi ng and hardware manuals. In this systern NMI interrupls IRQ lnterrupts are used for serlal tlners, and keyboard inputs.

are used for video dlsplay and reset. porl com'rnlcatlon, peripheral devlces,

NMI Interrupts.: Even though NMI lnterrupts are "unrnaskable" on lhe nicrptocessor, this systeE has interrupt enabLe (:nask) bits for NHI (Blts 6 and 7 of NMIEN) t{hen lhe€e blts are zero NMI lnterrupts function. are dlsabled (nasked) and prevented fro![ causlng a xoicroprocessor NUI (see NMIEN reglster descrlptlon) interrupt. The 3 types of NMI lnterlupts

1.

(ftrrlng dlsplay ttrtre any dlsplay D7 - lnstruction lnterrupt lnstructlon wlth blt 7=1 w111 cause thls lnterlupt to occur (if enabled) at lhe star! of the last video line dtsplayed by that instructlon. )

2.

(lnterrupt D6 - Vertical Blank Interrupt occurs (if enabled) at rhe beginning of the vertical blank rime interval.)

3,

(pushtng rhe SYSTEMRESETbutton lfi11 D5 = Reset Butron Interrupt cause thls interruDt to occur,)

rtrlIl cause the processor lo Jurnp to lhe Slnce any of these lnterrupls same NMI address, lhe syslen also has NMI status blts rrtich nay be exantned Blts by the processor to deterrnlne whlch source caused the NMI lnterrupt, (see functlon descrtptlon). 5, 6, and 7 of NMIST serve this NI1IST register These status blts are set by the correspondlng lnterrupt funcllon (even tf fron processor by the loterrupt 1s Easked the NMIEN). The status bits toay be reset logether by wriling to the address NMIRES. Tno of the lntelnrpt enabLe blts (blts 6 and 7 of NMIEN) are cleared autornatlcally durlng sysren po!/er turr oo and therefore these NMI internrpts aie inilially dlsabled (nasked), preventing any pover turn on servlce routlne fron being lnte.rupted before proper lnltiallzatlorl of reglsters and polnlers.* They can then be enabled by the processor nheneve! deslred, by wrltlng lnro blts 6 and 7 of NMIEN. Except for the reset button lnterrupt, they can also be dlsabled by the processor by writing a zero lnlo bits 6 or 7 or NMIEN. The reset button cannot be dlsabledj allowing an unstoppable escape from any posslble "hangup" conditlon. These NMI lnterrupt functlons are each separaled ln tlne (to prevent ovetlaps) and converted to pulses by the systeo hardware, in order to supply N M Tt r a n s l r l o n s r e q u i r e d b y t h e n t c r o p r o c e s s o r I o g t c ,

* - NOTE: Blt 5 1s never dtsabled and therefore the Reset Button should not be pressed durlng pover turn on.

r1.28

IRQ Tnterrupts: IRQ lnterrupts are a1l "naskabte,' together by one blt _ of rhe sratus teglster on the mictoprocessor. This blt is se! ro the dtsable condltton autonatlcally by power turn on !o prevent tnlerrupt of power Eurn on service rortines.*r. In addltlon to thts processor IRQ mask bit, there are separate systenr IRQ lnrerrupt enable blts for each IRQ lnterrupr functton (blts 0 thrll 7 of IRQEN). These btts are not tnltlalized by porrer turn on, and rorsr be inttlalized by rhe progran befoie-enabling the processot IRQ. The I rypes of tRQ tnterrupts are: D7 = BREAKKXy (depression of rhe br€ak kev) D b = O T H E RK e y { d e p r e s s i o n o f a n y o t h e r k e i ) D5 = SERIAL INPUT RXADy (Byte of serial data has been recelved and is ready !o be read by the processor tn SERIN leglsrer). D4 = SERIAL OUTPUTNEEDED(Byte of serial data is being rransnlrrect and SERoUTis ready to be lrritten to agatn by the processor). D3 = TR-ANSMISSION FINTSEED(serlal data transnission 1s flnlshed, Ourput shift register is enpry). D2 = TIMER #4 (audio dlvider /14 has counred dol''n to zero) Dl = TIMf,R /12 (audto divider 12 has counted dol',n to zero) D 0 = T t M f , R/ i t ( a u d i o d i v i d e r 4 t h a s c o u n r e d d o & n t o z e r o ) In addition ro the above IRQ inrerrupts (enabled by blrs 0 through 7 of IRQENand ldenrtfied by stalus btls O rhru 7 of IRQST) ih"re u.. cwo *o.e syslen IRQ lnterruprs lrhlch are generated over the serlal bus proceed and Interrupr lines. D7 D0 D7 D0

of of of of

?ACTL = PACTL = P B C - L?BCTL =

peripheral pertpheral Dertpherat peripheral

"A" tnte(rupt 'tA" tnrerruDt ',S', internrpt ',B" lnrerrupr

status enable srarus enabte

bit blt bit blr

These last tvo interruprs g!9 auronatically dtsabled by powet Eurn on, . and thelr starus blts are reset by readtng fron porr e reglster and port B (See PORTA,PACTL, P0RTB, and PBCTLRegister descrlptions,) register. The IRQEN reglster, like rhe NMIEN regtsrer, enables lnterruprs when lts birs are I (logic rrue). The IRQST horever (unllke rhe NMIST) has inlerrupt status bits thar are normally logic rrue, and go !o zero ro lndicale an interrupr reqresr, The IRQST status bits ar; reEurned to logic true only by llrlring a zero into rhe corresponding rRQENblr. This I't1l dlsable the interrrlrpr and simrltaneously set the intetrupt sratus bi! to one, Bit 3 of IRQST ls nor a tatch and does nor ger rese! by interrupr disable. It is zero "hen rhe serlat out rs empty (our ftnt;hed) and true \rhen it is not.

*x - NoTE: An NMI also disables

the I bit.

II.29

INTERRUPT SI]MMARY

NAME

TUNCTIONS

ENAB]-E

I NMI

NMIST Address (Bits 6 rhru 7) (Blrs 5 thru 7) NMIRES NorEally Zeio NornaUy Zero (Resets all NMI (Dtsabled) | (no lnlerruot) lstatus toeether)

I ulsPray llnstructlon

INTERRUPTS IJ9!9:

g]3gL

lReset Button

I

|

I D0 of PACTL lNormally Zero | (Dlsabled)

I D7 of PACTL lNorrnally zero l(no interrupt)

I Reset by I Reading PoRT A | Restster

I D0 of ?BCTL lNornally Zero | (Disabled)

I D7 of PBCTL lNornalLy zero l(no lnterruDt)

|

(Dlsabled) 't

Tlners

E.

Noroally True (no interrupl)

Correspondlng Bit of IRQEN | (except Blt 3)*

.P.g.!!e

Perlpheral B

Reset (to rme)

IRQEN rRQST (Blts 0 rhru 7) (Bits 0 thru 7)

KEYS Serlal

IRQ INTERRU?TS Perlpheral A

STATUS RESEl

STATUS

I

Reading PoRT B Resister

CONTRO1LERS

A varlety of controllers can be plugged into the four jacks on the paddle (pot), twelve-key front of the console. Thts includes joysttcks, keyboard, and ltght pen (when avallable). T h e c o n t r o t L e r p o r t s a r e r e a d L h r o u g h t h e P O R T Aa r d P O R T Br e g i s e r s and the PoT a{d mIG regtsters. The OS reads these registers doring vertlcal blank and slores lnto its own RAM locatlons. These are STIC(, PADD1othrough PADDLT, PTRIG'S and STRIG'S. The OS sets up PORTAAND PoRTBfor inpur. Thts is done by settlng PACTI-or PORTB(Port Control) blr 2 ro a 0 (to seleci the dlrectlon control register), then lJrlrlng all 0's to the destred port. PACTL (PBCTL) b1r 21s then changed back to a I, allo$.'1ng the progrard to read fron the porl. The ports can aLso be set up for outpu! by \rrirlng 1's instead of 0's whtle the direcrion control mode is selected.

left

The joysttcks have four .I9J9!f9E9: (L), back (B) and foruard (F).

s\rltches,

one each for

righl

(R),

These swltches are read thlough PORTAand PORTB.A fifrh swltch is actlvated by presslng the red t!1gger button. The trigger buttons are read fron TRIC0 through TRIG3. A value of 0 indicates that a button has been pressed and a I indicares rhat it has not been pressed.

II.30

The IRIG reglsters are trorroally read directLy, bul they can be used a zero to btt 2 of GItAcTl- dlsables the latches ln a latcheil oode. wrltlng If a joy_ and sets them to 1. Wrltlng a I to bit 2 enables the latches' is I of GMCTL Ithlle bit 2 button ls pushed al any ttne stlck trlgger qay. A that Progran can the latch value r'l1L change to zero and stay joystlck have ever been buttons trlgge! use th13 to deterrdne whether the pressed durlng a certain perlod of tiEe. The paildles cone ln palrs, so elght paddles can-be connected ?addles: jacks. The paddles are read bv storlng lnto PoTGO' then to th;=;I The values range fron 0 readlng lhe tOT registers at least 228 llnes later. (Paddle turned counter-clockrlse) (wrth;he paddle turned Lo the rlght) lo 228 charge up the capacllor The value lnallcates how dany TV llnes 1l takes to Turnlng lhe knob to Lhe righl rhlch ls the serles \.ith the potentioneter. the l\rnlng lo\.ers the reslstance, so the capacitor charges up qllckly' The charging tlme' and the lncreases the reslstance knob to the lef! are used to discharge lhe capacltors so !ha! a capacltor ilunp translstors nev readlng can be rnode. The POTCOcommand clears the counters and lurns The ALLPOT to allow the capacitors to charge up' off the du;p translstols has charged reglster contalns ofle blt for each paddle. l]hen the capacltor and the to zero up to lhe threshold value the AJ,LPOTblt changes fron one (Serial Port Blt 2 of SKCTL tOt reglster conlains the corlect readings. Cootrol) enables fast pot scan. In thls node, lt takes only lwo scan llnes Btt to the maxllffln 1eve1 lnstead of 228 lines' to charge up the capacltors to I to start Then Bit 2 is set set !o O lo durop lhe capacitors. 21s flrst as the nornal scan t0ode' accurale pol is not as scan The fas! scan' the pot -2 Btt of SKCTLrfirst be set to O to use nornal scan mode' 0ther\tlse' the wlll flever dunP. Note !ha! soue paddles have a range srnallel capacltors The left and rlght paddle rh;d O to 228 due to illfferences ln the pots. trlggers for each paalille palr are read fron the left and right bits for the (PORTAor PORTB). correspondhg joystlck has a lwelve-key pad Each keyboard controller Kevboard Co[trol1ers: slep tn using the pott. The flrst controller and pLugs lnlo a joystlck to output and port dlrectlon the ron by settlng select a teytoara ts to iThlch selects lhe reglster or ?ORTB tn the PORTA the blt . 0 to tn itrng have l's should (see rots The other III). SECTION PORTA, deslred low (see registers and TRIG lhe POT lhrough are read Colur0ns wrltten !o then. Appendlx fl of the BASIC controlLer PORTPlNoIn ahart ln sectlon rll). The reads the controllers' plograro uhich a Baslc Reference Manual contalns pots for plns as the sane the keyboard use of the and seconil colunns flrst so they are read by readlng the PoT (or PADDI-) lhe padtlle conlro1lers, Whe[ a bultofl is prished' the pot line is grounded' so lhe po! reglsters. Level and lhe reading ls 228 never charge up !o lhe threshold capacltors (tire rnaxiurn). When the button 1n lhe selected lolr and coluEn is not pushed sBall reslstor' the capacltor ls connected to +5V through a relatively (thls readlng 1s not Since the rnay vary). 2 glvlng a POT value of about only a 2 Une wait 1s 3o that be used, pot mode can scan the fast crltlcal, The POT reglster' reading the rol' and reqrired between selectlng the (declnar)' l0 wlth POT readlog the co;ventton has beefl adopled of cor0parlng The thtrd greater lhan 10 then the bullon has been pressed' If ls lt just ltke a so i! \torks ltne, colunn ls read through lhe loysttck trigger ( 0 = b u t ! o n . ls pressed, I=not Pressed) loysrick trlgger

II.31

'

Llahr PerI: A llght pen ts a device rhat can as lt sweeps across the TV screen. It 1s irsed to on the TV display. Appltcatlons hclude selecting l1nes. Tte ATARI 400/800 hardware was deslgned so pfugged lnto any of the joystlck controller porte III).

detect the electron beaD polnt dlrectly at an irnage memr ltens and drawlng that a light pen can be (see ena if sectron

m:" any one of the joystick rrlgger lines (pln 6) rs pul1ed 1or, the .--ANTIC chlp takes rhe current VCOI]NTvalue and st;res tt in PENV. The horlzofltal color clock value (0-227 declnal) is storect 1n pENt{. The teast slgnificant blt ls inaccurate and should be lgnored. Slnce there are a nuober of delays lnvotved 1n dtsplaytng the alata and changing the ltghr per! register, eech systeE mrst be cal brated. Softr"rare irhtch uses the l1ght pen should contaln a user-tBteractlve caltblatlon routlne. For exanple, the user could pol[t the Ught pen at a crosshalt tn the center of-the screen and the progran could coruFnrrethe requtreil horlzontal offset. PENHwt1l wrap around fton 227 ro O near the rlght halld edge of a statdard width dlsplay because of lhe delay. fhe pen rd11 not l'ork lf 1t 1s polnted at a black area of the screen, slnce the elecrron besn is turneal oif. It ls a good ldea to read t\ro (or nore) values anal average then, slnce the user rsll1 probably not hold the pen perfecrty sready.

TI.32

I1I.

HAR)WAREREOISTERS

Thls sectlon shadow reglsters.

1lsts

the hardware registers

In the fo1lo\"dng descrtptions,

tme

and operatlng

ahrays refers

to a btt

Systen (OS)

\'rhose value

1s l.

A.

PAL (D014)

Not U s

B.

d

I D3 | D2 | DI lNor l l l l u s e d

D3

D2

D]

I

I

I

NTSC (US TV)

0

0

0

PAI- (European TV)

Thls byte the progran ls

\--

e

can be read by a prograrn to deternlne runnlng ofl.

edlch

lype of systeE

INTERRIJPTCONTROL

NMIEN (Non Maskable Interrupt to the NMI lnlerrupt enable blts. 0 = dlsabled I - enab led

I

tnable)(D408):

Thls address wrltes

data

(dasked)

Nor Used

D7

Dtsplay l,tst Instrucllon Interrupt Enable. This blr is cleared by Power Reset, and nay be set or cleared by lhe plocessor,

D6

Vertlcal Blank lnterrupt Enable. This blt 1s cleared by Po\rer Reeet, and roay be set or cleared by lhe processor.

SYSTEMRESETBulton lnterrupt This lnterrup! ls always eflab1ed. The SYSTEI{RESET button no! be pressed alurlng power turn on. (ser ro hex 40 by os IRQ code.)

1r1.1

should

NUIST (Non Maskable Interrupr Status)(D40F)! Status Reglsrer (Read by OS NMI code).

Thls address read the NMI

0 - no intelrupt I = lnterrupt

D7

Not

I D6 D7

This btt ldenttfies an Nl,Il lnrerrup! Dlsplay List hstructton.

caused by btt

D6

Thts blt ldentlfies of vertlcal blank-

an NMI inrerrupt

caused by the beglnnl'tg

D5

This blt ldenttfles RESETbutron.

arl NMI lntetruDt

caused b\/ the SYSTn1

NMIRES (NMI Status Reqtster Reset)(D40F): Thls wrtte the Non Maskable Interrupr Status Regtster (MIST).

7 of a

address resets

Not Used

( Wrttten

by OS NMI code.)

IRQST (IRQ lnrerrupt Status)(D20E): the IRq Interrupt Status Reglster.

This address reads the dala fron

0 = Interrupt I - No Inlerrupt

D5

D4

D3

D2

D7 = 0 D6 = 0 D5 = 0 D4 = 0 D3 = 0 D2=0 Dl-0

Sreak Other Serial Serial Serlal Tiner Tlner

Key Inlerrupt Key Intertupt lnput Data Ready Tnterrupt Ortput Data Needed Interrupt Outpur (By!e) Transntssion Finlshed fnterrupt 4Interrupt 2 Inrerr:upt

Dn=n

Tlnor

I

T^ra?r,,-r

* - NoTE: Used for generation of 2 stop blts, See IRQ descrlptlon ln sectlon II (no dlrect reset on btt 3).

IAI.2

*

IROEN lqcerrupt Interrupt Enable 0 = dlsable,

\7 D6 D5 D4 D3 D2 DI DO

EnabIe

D20E): Thls address wriles

correspondtng IRQST blt

data to the IRQ

is se! ro I

Break Key Interrup! Enable other (ey Interrupt Enable Serlal Input Data Ready Inlerrupt Enable Serlal 0utput Data NeedealInterruDt Enable SerlaI 0ut TransElsslon Elnlshed interrupr Enable Tlner 4 Inrerrupt Enable Tlner 2 Interrupt Enable TlEer I Interrupt Enable

OS SIADOW: PoXMSK (hex lO) U€e AND'S and OR's to change one bit tn pOre,ISK wilhqr! . affec(ang the olhers. Store the ilesired ialue tn both IRQEN and pOruSK:

c,

TV LINE COMROL

Llne Counter

v8

17

Vertical Cqunter) (D4OB): Th{s address reads the Vertlcal nost slgDlflcanr btts).

v6

v3

\2

vl

V0

TV

V0 not read. Tlro llne resolutlon supplted.

1 "a".a "f

Thls address sets a latch rhat pu1ls down on lhe Rny llne to the Dlcroplocessor' caislnS 1t to nalr until thrs latch is autordaticafly reset by the beglnntng of horlzontal b1ank. Dlsplay fr"t i"t.r*ptr'."v U. delayed by 1]lne 1f wSyNCts used. ([sed by OS t"yt"".i .ii"t-ro"ti"..t

II1.3

D.

GRAPHICSCONTROI.

Dl.tAcTL(Dlrect Medorv Access Control) (D400): lnto the DMA Control Register.

Not Used

This address nrites

data

I

D5

D4

D5 =

I

Enable lnstruction

D4 =

I

I Llne P/!l resolutlon

D4 -

0

2 ltne

D3 =

1

Enable Player

D2 =

t

Enable Mtsslle

D1,D0 =

0

0

No Playfteld

=

0

I

DI,IA Narror Playfteld (128 Color clocks)

=

1

0

standard ?layfleld (160 color clocks)

=

I

Dl4A I Wlde ?layfteld ( 192 Color clocks)

See GRACTL. 0S Shadow:

P/M resolutlon DMA DI,IA DI'IA

o

t

n4A

SDMCTL(22F) default

GMCTL (Graphlcs Control) (D01D): craphlc Corllrol Reglster.

N

DMA

fetch

l

l

Ttls

value

hex 22

address \trites

dats

to

the

l D

Used D2 = |

(latches are Enable latches on 1'RIG0 - TR1G3 tnprts cleared and TRIG0 - TR1G3 act as normal lnputs a'hen control b1t 1s zero).

Dl = I

Enable ?1ayer DMA to Player Graphlcs Reglsters.

D0 = I

Enable Misslle

DMA to MlBslle

Graphlca Reglsters.

blts in bolh DMACTLand GRACTL. settlng DMA ls enabled by setthg DMACTI-only wtll xe'sult ln cycles betng stolen but ro displsy k{11 be eenerated.

cflAcTl (character control) (D401): Character Control Reelster. Not Used

OS SfiADO :

This address \rrltes

data

lnto

the

I

D2

DI

DO

D2

Character Vertlcal Reflect Blt. Thls blt ls sanpled at the bepinninp of each line of characters. If true l! causes the (for upstde (inverr) vertically line of characters to reflect dofir chalacters).

Dl

Character Video Inverr llae (used for 40 Character Mode only). If bit 7 of character code is true thls flag causes that character to be blue on lrhlte (lf nornal colors are white on blue).

D0

Character Blank (Blink) Flag (used o$ly). If bit 7 of charecler code lhal character !o b1ank. Blinklng setting bit 7 of the characters to changing D0 of CMCTL.

for 40 Characrer Mode ls true this flag causes characters are produced by I, then perlodlcally

CHACT (2F3)

DLISTL( Displav List Low )(D402): 1o!, byie of the Dlsplay Llsl CounEer.

This

address

writes

data

lnto

thc

data into

the

I I

0

,List \ counter lBtt (Posrtlon,

oS SHADOW: SDr,sTL (hex 230)

DLISTH (Displav List Hish) (D403): high byte of the Dlsplay List Counler.

D TI D 6 I D

D 4I D 3 I D 2

15

t2

t4

t3

TI

10

OS SHADOW: SDLSTH (}TEX231)

9

This

8

address wrltes

f?lserav \ co'lnrer lBit \?os1t1on.

in memory. These The Dlsplay l-1st ls a llst of display lnstructlons lnstructlons are addr essed by the Display List Counter, Loadtng these (See regisrers deflnes the address of the beginnlng of the Display List. sec!1ons I and Il, ) Not€: The top 6 birs are latches only and have no count capabll1ty, therefore can not cross a lK bvte nenorv boundarv unless a lunD lhe displav llst instructlon ls used.

blank or arllh DLISTL and DLISTIi should be changed only during vettlcal Bit 7 of NMIENr(rs! be set Dl4A dtsabled. Other:rlse, the screen nay ro11. lnterrupts. in order to recelve dlsplay list

Thls address writes @: The data specifies lhe nost data lnto the Character Address Base Register. slgnlflcant byte (MSB) of the address of the deslred character set (see Note lhat the last I or 2 btts are assuroedto be 0. sectlon l1), 40 characrer Modes CI{BASE

Base Address

Char Nane 20 Character

Modes

CIIBASE

12 |lt [0 Llne Counter

Char Nane

Base Address oS SHADoI,J: CHBAS (2F4)

PIfBASE(?1aver-Mlsstle Address Base Reeisler) (D407): Thls address The data l'rltes dala into lhe Player-Mlss1le Address Base Reglster. player and .0iss11e DMA dala (see spectftes the l,tSBof the address of lhe sectton II). One Llne Resofution PMBASE

Base Address

scan Player-Missile Counters

Player-Mlsstfe Select

Tl'o Llne Resolution PI{BASE

Base Address

Player-Mlsslle Select

II I.6

Player-Misstle

Scan

HSCROL(florizontal Scrolt Reelste!) (D404): This address L.rltes data lnto lhe llorlzofltal Sclol1 Reglster. Only playfteld ls scrolled, not Dlavers and Elss1les. not used

|

|

D3

|

D2

| DI

DO

0 to 15 color 'iqht

clo.k

Fhl fl c

The dtsplay ts shlfted lo the rlght by the mrnber of color clocks speclfted by IISCRoLfor each dlsplay llst lnstruction that contalns a 1 ir Its ITSCROL Flag blt (blt 4 of lnsrruction byte). When horizontal scrol1lng ls enabled, nole bytes of data are needed. (see DI,IACTL For a narro\r playfleld blts I and 0) there should be the sane nunber of bytes per llne as for standard playfleld \rlth no scrol11ng. Stun11arly, for standard playfleld use the sane mnber of bytes as for the wtde playfleld. ror wlde playfleld, there ls no change 1n the nunber of bytes and background color 1s shlfted ln.

VSCRoL (Vertlcal Scro1l Reslster) (D405): the Vertical Scroll Reslster.

not used

not used

dara lnro

I D2

8 lloe

Thls address {rrltes

display

D1

DO

Eodes

I I

16 llne

dlsplay

nodes

The dlsplay ts scrolled upward by the rnrroberof lines specified 1r the VSCRoLreglster for each display l1st lnstruction that coflta1ns a I ln 1ts VSCROLllag btt (bt! 5 of lrlslrucllon byte), The scrolled area rilf (see sectlon termlnate lrlth the flrst lnstrucllon havlng a zero tn btt 5. II for Dore detalls).

PRIoR (Prtorirv) (D0lB): Control Reglster. D7

D6

D2

This address writes

DI

data into

the Prlorltv

DO

D7-D6 = 0 D5 l4rltlple Color Player Enable. Thls blt causes the toglcal "or" function of the bits of the colors of Player 0 wlth Player I, and also of Player 2 sith Player 3. Thls perrlts overlapping the poslrlon of 2 pLayers wilh a choice of 3 colors in lhe overlapped reglon.

III. 7

D4

D3, D2, D1, & D0

Flfth Plaver Enable. This bit causes all mtsstles to assune rhe coLor of playfleld (CoLPI3). thls allovs alsstles Type 3. ro be posttloned together with a coomon color fot use as a flfth player. Prlorltv Select (}tutua1ly Exclustve). These blts select one of 4 types of prlorlty. hlgher prlorlty !,1111appear to nove tn front n'lth fol'er Drlorltv. D3=l

t

?F 0 ?F T PO P 1l i P P 2 2l P P3.J

l

Objects wtth of objects

D0=l

Pc.l

PFO PF] PF2

I l

I

a ?F2 | +3 P5 | 1P1' * rAr I

+ P5

f I

PI J

Pr I

PFo PFr

P2

l

I

i-s l"o:-

P3-,1

Pzf

P3 _l pF0 Pr'l PF2

P3,J

+ 5

P0-l PI P2

|

The use of Prlority blts tn a ',not-exclustve" mode (nore than 1 blt rrue) \rl1l result in objecrs (lrhose prtorlttes are ln confltct) turnlng B]-ACK ln lhe overlap regton. EXA],IPI,E:PRIOR code = 1010 Thrs w111 black p0 or pl lf rhey are over PlO or PFl. It will also black P2 or p3 if they are over ?F2 or PF3. In the one-color 40 character oodes, the lunlnance of a plxel in a character Is determined by col,pFt, rQaii'ili! or che priority. If a hlgher priority player or misslle overlaps the character then the color ls deterdtned by the player's color. !9:g:

OS SHADOITI: GPRIOR(26I)

C o L P F O- C 0 1 P F 3( P l a v f i e l d C o l o r ) ( D 0 1 6 . p o l 7 . D 0 1 8 . D 0 t 9 ) : T h e s e addtesses $.rlte data to the Playfield Color-t-ur0 Reglsters,

D 6I D 5 I D (see CoLBK for b l t

2 t D l t D 0 asslgnnent)

OS SHADOWS: COLORO- 3 ( 2 C 4 - 2 C 7 )

III.8

Co],BK (Backeround Color)(D01A): Background Color-Lum Reglster.

This address wrltes

data ro rhe

Co

D7

D6

D5

D4

D3

D2

X

x

x

x

0 0

0 0 ETC. I

0 0 0 0 0 0 0

-

0 0 0 0 1 I 1

0 0 r 1 0 0 1

0 1 0 1 0 1 0

0

r

1

t

1 I 1 l 1 l I

0 0 0 0 1 l 1

0 0 r r 0 0 l

0 l 0 1 0 1 0

l

l

l

l

DI

Not Used

0 I

Zero Lunlnance (black)

I

Max.

Luninance (white)

Grey Gold Red-Orange Purple Purple-Blue Blue Bfue 1-igh!-Blue Tu r quoise Green-Blue Ye11ow-creen Orange-Green Llght-Orange

OS SHADOI.I:CoLORa(2C8)

E.

PLAYERSAND MISSII,ES DMACTL, GRACTL, PMBASEand PRIOR also

.-

affecr

players

and nissl1es,

C o L P M o- C O L P M 3( P l a v e r - M i s s i l e C o l o r ) ( D 0 1 2 , D 0 1 3 , p 0 1 4 , p 0 l 5 ) : These addresses rr.rlte to the Player-Mlssile Color-Lun Registers. Missiles have the salle color-lun as thelr player unless rnissiles are used as a 5th player (see bit 4 of PRIoR). A 5th player missile gets irs color frorn CoLPI3.

D

D3 D2 D1 (see CoLBK for bit assignnents)

DO

OS SHADoWS: PCoLRo- 3 (2C0-2C3) (PO D00p, ?1 p00E, p2 p00I, GRAFPO- CMFP3 (Plaver craphlcs Reslsters): P3 D0l0): These addresses r".rlte dara dlrectly into rhe player craphtcs Reglsters, independent of DMA. If DMA ls enabled then the graptllcs reglsters I{iU be loaded autonatlcally fron the nenory area specified by PMBASE(see page II.3).

D7

D6

D

D3

D2

Lefl

DI

DO R l g hr

Playe! on TV Screen r11.9

GRAFM(Mlsslle Graphlcs Reqlsters)O01I): Thls address r^'rltes data dllectly lllto the Mlsslle Graphlcs Reglster, lndependent of Dl,tA.

I

I

D7ID6 L

R M3

D5 ID4 L R ]

D3 -

M2

I

D2 R

D 1I D O ]

-

Ml

R

l{0

SIZEP0 - SIZEP3 (Plaver stze)(?0 D008. ?1 D009, P2 D00A, ?3 These addresses write data lnto the ?laver Stze Control Reeisters.

N o used

t

l

l lDrlD0 0

0

0

1

I

0

I

1

D00B):

liorlzontal Slze Register (Player) Nornal stze (8 color clocks vide) Twtce Noroal Size (16 color clocks h{de) Nornal slze 4 Tines Nornal size (32 color cLocks wide)

Wlth nornal size objecls, each blt in the graphlcs register corresponds to one color c1ock. Ior laxger objects, each bit ts extended over nore than one color clock. SIZEM (Mlsslle Slze)(D00c): Slze Control Register.

D7

D6

\__\r.--l M3

D5

D4

D3

M2

D2

Thls address I'rltes

D1

Ml

DO

data into

the ll1sslle

Eorizontal Slze Register (Misstle)

MO 0

0

0

I

I

I

Normal Slze (2 color clocks \r'Ide) Twice Nornal Slze (4 color clocks dde)

4 Tlnes NorEal Slze (8 color clocks \rrde)

ttPOS?0- H?0SP3 (Player Eorlzontal Posltlon)(P0 D000. ?1 D001. P2 D002, ?3 D003)r These addresses wrlte data lnto the Player Horlzontal Posltlon Reglster (see display dlagran ln sectlon IV). fhe horizontal positon value deternlnes the color clock locatton of the left edge of the object. Hex 30 is the lefl edge of a standerd wldth screen. Ilex D0 ls the rlght edge of a standard screen. I

7

D6

D5

D4

D

D2

D1

DO

III,IO

.u,-

_ swwer

Positlon

uj uuu/r; Inese addresses rN.rlte data (see ItpOSpO descrlDtion). Reglsrers

D7 I D

D 5I D

t, ur ouo:. into

the Misslle

itorlzontal

D 3l D 2 l D l

mpL4Y -(yc4LE-!-Uq!4dQ9.!O: -v e r t l.c a l D e l a y R e g l s r e r .

rhls

a.lclress t'rites

dara irto

the

I ! | i t - - - - - - _ l

p7tp6 lp5 lp4 lp3 D2 | lDrlDO P3

P2

?l

PO

M3

M2

l,1l

MO

VDELAYls used to glve one-Ilne resolutton 1n rhe vertlcal po_ sltlonlng of an object when lhe 2-1ine resolutlon dtsplay ts enabled. Settlng s blt tn VDELAy to I noves the corresponcltng otllct aown ty one TV flne. If player-nlsslle Dl4Ais enabled then chang{ng the vertlcai tocation of ar oblect by nore thar one line 1s acconpllsied by ,."i"g tii" ._""a 1n the nenory nap. If Dl,tA is dlsabled rhen rhe vertical loiatlon can Ue set.up by assenbly language code whlch stores data tnto ttre grafhics reglsters at the deslred line, M g t E ! - Y I P L - l - \ a 2 P F r . l , 1 3(PMPi s s l ] e . r o p t a v f t e t d c o l r i s r o n s ) ( p O o O , p O O r , h , v^u^ z, . u u u r r : Inese addresses read l,tisstte to playfietd Cotlisions. A I blt neans that a colllslon has been detected since the last HITCLR.

Not used o forced)

| | | I J p3 L D2 | Dt I DO Playfleld

P O P F .P l P F . P 2 P

Type

3PF (Player t o P 1 efd Colltslons) Player to Playfield

p 0 0 5 . p 0 0 6 . p 0 0 7 ) : These addtesses Not used zero torced)

| | I | p3 | D2 J Dt I DO Playfteld

MIPI,. M2P1,.M3PL sl1e to D00A. p00B): These addresses read Mlsslle Not Used

r Cofl lo

Player

Type on) (D008 Coltislons.

I D

D1

2

0 Player

ltunber

POPI. PI P'IPL. P to Plaver ollislons D00F): These addresses read Playe r to Player C o l l l s i o n s

Not osed

(D00 Collisions.

I

I

I

rorced) lD3 lD2 lDI lD I (Player 0 against player

0

Player Nunber

O ts always a zero). III.lI

Erc.

00c DOOD

"HlT"

(co1llslon

IM!B-

Ttls

clesr)

D OI E

address clears all

wrlte

colllslon

btts

descrlbed

Not

I.

AUDIO AUDCTL(Audio Control) (D208):

r'roa! C"trt.of r"gr"t.t. 7 D1 D6 D5 D4 D3 D2 D] DO

D5

D6

D

Thls address wrltes data blt 3 SKCTL tro-tone

{Ll*-"i" D2

D

DI

lnto

Audlo

the

DO

Change 17 btt poly inlo a 9 blt below poly' clock chan$el 1 r'tth 1.79 MHZ, lnstead of 64 relz. clock Channel 3 with 1.79 }l1lz, instead of 64 Klz. Clock Channel 2 with Channel 1, lnstead of 64 ].J lZ (f6 BlT). clock Chamel 4 nilh channeL 3, lnstead of 64 xllz (16 BIT)' in Channel I, clocked by chanflel 3. Inser! Ill Pass lllter (See sectlon 11. ) 1n Chan$el 2, clocked by Channel 4. Insext l{i Pass llLter tnto 15 KlZ. Chaflge Normal 64 ICIZ frequeocy,

The glven above are apProxinate. Tne frequencles Ee9!-lEgSg!g1es: glve[ (f1[) below Elact Frequency that clocks the dlvtde by N counters ls (NTSCorly, ?AL differert).

FIN

FIN

t.789'19

t . 7 9 MItZ 6 4 KtZ

6 3 ,9 2 1 0

15

15.6999

The Nornal Iour

Tornula =

for

output

Use modifled -

Use norDal

frequency

forldrla

forlerla

for

for

fout

fout

is:

Fin/2N

(AUDF), plus I (N=AUDF+1). where N = The blnary nudber 1r) the frequency reglster = r.t9 ttltL and a rlore The MODIFIED FORMUI.Ashould be ssed when I1rI ls desired: 2 (AIIDF + M) lihere:

M M

8 b 1 t counter (AUDCTI-blt 3 o r 4 = 0 ) 1 6 b 1 t counlex (AIJDCTLblt 3 o r 4 = l )

rll.12

AUpII. AUpr2. AUpF3.AUpr4 (Audlo Freouencv) (p200. p202. t204. D206) These addresses lrrlte data lnlo each of lhe four Audlo Freqrency Control Reglsters. Each reglster controls a dlvtde by "N" counter.

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

1

Note: "Nt' ls one gleater than the blnary nunber 1n Ardlo Irequency Reglster AUDF(x).

AUDCl. AUDC2, AUDC3. AUDC4(Audlo Channel Co$tro1)(D201. D203. D205. D207): These addresses wrlte data into each of the four Ardlo Control' Each Reglster controls lhe no13e content and volurne of the Reglsters. correspondlng Audio channel. olse Cofltent or Dlstorlion

volune

D2

Dlvlsor "N" set by audlo frequency !egister. - 17 BIT poly - 5 BIT poly - N - 5 B I T p o l y - N - 2

HEX

D7

D6

D5

D4

0

0

0

0

0

2

0

0

l

0

0

I

0

0

6

0

I

1

0

- 4 BIT poly ' 5 BIT poly - N - 5 B I T p o l y - N - 2

I

I

0

0

0

- 17 BIT poly - N

I

X

1

0

-PureIone-N-r

c

I

I

0

0

-4BtTpoly-N

I

x

X

DO

DI

- Force Output (Volune onlY)

0

0

0

0

0

- I-olrest voluroe (off)

8

1

0

0

0

- Ealf

F

t

l

l

Itr. l3

l

Volume

- Eighest

Volune

PITCIT VALUBST'ORTIIE I.IUSICALNoTXS-AUDCTL=0. AUDC = hex AX AI'DF

t{ex ID

c

ItrGtt NOTES

B Atl or Bb e# G l# ! E D# D C#

or Ab or Gb

or Eb o! Db

c B AtAor Bb G# or Ab G F# or cb F E D/l or Eb D C# or Db

c

I1IDDLE C

B A# or Bb

L0w

C# G F# I E D# D c#

NOTES

c

2l 23 25 28

or Ab or Gb

2D 2l 32 35 39 3C 4A 48 4C 5I 55 5B 60 66 6c 72 79 80 88 90 99 A)D CI

or Eb

cc

or Db

D9 E6

Dec 29 3l 33 35 40 42 45 41 50 57 60 64 68 72 76 81 85 9I 96 102 108 II4 t2\ r28 I36

r44 153

r62 r73 182 193 204 2t7 230 243

STIUER (Start Tirne!)(D209): This ts'rite address resets all audto frequency divtders generate tlrtrer !q thelr I'AUDF|| value. These dtviders internrpts $hen lhey coun! dolr'n to zero (if enabled by IRQTN). (also see lRQST)

(Randon Nunber Generator) (D20A): This eddress reads the hlgh R-ANDOM order 8 blts of a 17 bit Dolvnonial counter (9 bit, 1f blt 7 of AlrDcTL=t).

D7

D6

D5

D4

D

2 III.I4

G.

KEYAOARDAND SPEAKNR

CoNSoL (Console Sr,'itch Port)(D0lF)r fro.0 the console snltches and lndlcarors. c o d e .)

Not used

I

ero forced)

| D3 | D2 | DI I D0

I

I

Eex 08 should be wtlrten Ones !.ritten CONSOI,Btt

DI D3

Thls address reads or \,Iriles itata (Set to 8 by OS Vertlcal Blank

I

to this

address before readlng the slrltches.

w111 pul1 down on the

sl'itch

llne.

Assignnent:

I

CaroeSelecr \ upElon serecE I Loudspeake! .,,,

- 0 neans snitch

pressed,

- should be held at I except when r.rltlng 0 noEenlarlly. OS nrlles a I durtng verttc al blank.

KBCODE(Kevboard Code)(D209): This address reads the Keyboard Code, and ls usually tead 1n response to a Keyboard Interrupt (IRQ and blts 6 or 7 of IRQST). See TRQENfor lnfornarlon on enabling keyboard inrerruprs. See SKCTLbits I and 0 for key scan and debounce enable.

D7

D6

D4

D3

D2

DI

D7 = Control Key D6 - Shifr Key -

Read by 0S lnto shadoo CH trhen key ls hlt. The OS has a get character functton whtch converts the keycode to ATASCII (Ararl ASCII).

III.15

KEYCODETO ATASCII CON\,"ERSION

KNY KEY CODE CAP

KEY

L .C .

u,c.

CTRL

4C

0c

00 OI 02

L J ;.

6C 3B

3A

OA 7B

03 04 05 06

K

+

6B 2R

4B 5C

03 ]E

0

6F

P U RET

70 75 98 69 2D 3D 76

o7 08 09 OA OB

0c OD OE OF 10 tl I2 I3 t4 15 16 I7 l8 I9 1A IB

:

OI

50 55 9R 49 7C 56

c

63

B

62 18

42 58

34

24

33 36

23 26 IB 25 22 2l

x

lc

ESC

ID IE IF

5 2 I

* = speclal

35 32 3I

15 9B 09 lc 1D l6 03

Z 3 6

r0

02 l8 1A

IB

20 2\ 2Z 23 24 25 26 27 28 29 2L 2R 2C 2D 2E 30 3I 32 33 34 35 36 37 38 39 3A 3B 3C 3D

FD

3F

handling

III.I6

KEY CA?

I-.C.

2C SPACE 2 0 2R N 6E

u.c.

TRL

5B 20 5D 4E

00 20 60 OE

M

6D

4D 3I

OD

,|\ R

12

52

T2

79

59 9I 54

05 I9 9E l4 I7

E Y TAB T

w

a 9

0 7 BAC(S 8

T H D

74 77 7l 39 30 37 7E 38 3C 3E 66 68 64

CAPS G 67

s

73

5I 28 29 27 9C 40 7D 9D 46 48

4'l 53 4l

ll

FE 7D FT 06 08 04 07 I3 01

H.

SERIAL PORT (see perlpheral

conoeclor

sKcTI- (Serial Port control)(D20F): reglsler that controls the conflguatlon Fast Pot scan and Keyboald Enable.

D6 D7

D5

D4

D3

D2

Force Break (force

on consofe)

This address vrltes data lnlo lhe of the serial port' and also the

(Bits are nordally zero and perforn the functlons sholrn belolr lrhen true. )

DI

serial

output to zero (space))*

D6) D5 ) sertal Port Mode Control (see mode chalt paee I1.34). D4) set]-a! port description,

at end of

D3

Tno Tone (Serial output transnltted loetc true/false.)

DZ

Iast Po! (Fast ?ol Scar. The ?ot Scan Coonler coBPletes its The seqrence tn tlro TV 1lne tlEes instead of one ftane tlne. are completely disabled.) capacltor dunp transislors

DI

Eoable Key Scan (Enables Keyboard Scanrlng

D0

Enable Debounce (Enables Keyboard Debounce circrils)

D0-Dl

(Borh Zero) chiP) *rt

Inltialize

as two tone slgnal

(State used for

lnsEead of

circuit)

lestlng

and inltializing

OS SHADOW: SSKCTI- (hex 232) The oS enables key scan and debounce and may change the other blts for an aborled cassette operatlofl nay In particular, dlfferent I/O operattons. leave the two tone b1t 1n ihe true state, causlng undesirable audto signals. Thts i0ay be corrected by \{rltlng hex 13 lo both SKCTL and SSKCTL after dotng reglslers. before nodlfylng the audlo I/0 and/or

* NOTE:

n'hen powered on, serial port output nay stay low even if this blt ls cleared. To get S.?. hlgh (nark)' send a byte out (reconnend 00 or FF).

**NOTE:

Thele 1s no original

polrer on state.

III.I7

Pokey has no reset pln.

SKSTAT(Serial Port-Keyboard Slarus)(D20I): This address reads rhe status reglster glving inforBation about the sellal Dor! and kevboard.

D7

D5

D4

D 7 = 0 = Serlal

(Blts are nornally true and provlde the following lnformatior vhen zero.)

D Data Input Frane Error

D6

0 = Serlal

D5

0 = Keyboard Over-run

D4

0 - Direct

D3

0 = Shtft

D2

0 = Last Key is

DI

0 = Sertal

DO

I

Data hput

from Serlal

Over-nrn

Input port

(D5 and D6 are se! to zero when new data and sane blt of IRQST

Key Depressed Stlll

Input Shlft

( SKRES)

Depressed Register

Busy

Not Used (Log1c Tnre)

SKRES(Reset above Status Reqister) (D20A): This wrile address resets 7, 6, and 5 of the Serlal por!-Keyboard Stalus Register to 1.

bits

SERIN (Sertal Input Dara)(D20D): Thls address reads rhe 8 bit parallel holdlng register that ls loaded I,hen a fult byte of serlal input dara has beeo recelved. Thls address ls usually read in response to a serial data ln (IRQ and bit 5 of IRQST). Also see IRQEN. inlerrup!

D7

D

D4

D

Serial lrlo Porr Connector plnout;

6

l.

3. 5. 7. 9. 11. See serlal

8

Clock In Data In to computer Data Out of Coopurer Comand Ardio In

10 t2

2.

10. 12.

Clock GND CND Moror

Out

Control

+5 / Ready +t2

p o r t d e s c r t p r i o n t n 0 S Eanual for Eore deta1ls.

III. t8

SERoUT(Se!la1 output Data)(D2oD): This address rffites to the 8 blt parallel holdlng reglsler tha! ls transferred to Ehe output serlal shlft This reglsier when a fu11 byte of serlal ortpul data has been transmitted. (IRQ serial data out inlerrupt address ts usually \rritlen in response to a and btt 4 of IROST).

D7 I.

D6

D4

D

PORTS (front CONTRoI-LER

of console)

PoRTA (Port A)(D300): Thls address reads or lrrltes data from Player 0 jacks if blt 2 of PACTL is true. Thls address and Player I cortroller conlrol register lf bit 2 of PACTLls zeto. I/o for wrltes to the dlrectlon both ports (A and B) goes through a 6520/6820 Dara Reslster-Addressed stlck

lf

blt

2 of PACTL is

l.

0Deration 0=Swilch pressed l=Switch not pressed

Back

Rlght

Rlght .

Left

Back l-eft

ftrd.

srick0 (Jack r)

(Jack 2) Paddle

o=Str'itch pressed l=Sirltch not pressed

board controller

0

Top Row .\ 2nd Rol' 3rd Row , 4rh Ro\t ) Dlrectlon

Each blt

Control Re

-Ad

ToP Rol.' ) 2nd Row \ 3rd Rowr 4rd

I

2

Jack

if

Jack

blt

2 of PBCTL ts 0

corresponds to a jack ptn

0-tnput l=output os ssADowS: STICKo(hex 278), STICKI (279), PTRIGO-3(27c-27I III. 19

PACTL (Port A ControL) (D302) | the Port A Control Reglsler.

D4

D6

x

D3 X

D2

This addless

\"'rites

or reads data froro

Port A Conrrol Reglster Set up register as shown (x - descrlbed below)

DI

x

(Read ggLI) Peripheral A Interrupt Status Bit. Serial (Reset by readtng Port A Register. bus Proceed line. Set by Pertpheral A lncermpt.) D3 - Peripheral Moto! Control line on serlal bus (trite). (0=0n I -off) D2 Controls Porl A addressing described above (wrlte). {I = Port A Reglsrer 0 = Directlon Control Register). (wrlte) I = Enable. D0 Perlpheral A Interrupt Enable Blt. Reset by poi.'er turn-on ox processor. Se! by Processor.

This address reads or wriles data fron Player 2 PORTB(Port B)(D301): jacks tf bil 2 of PBCTL ls true. Thls address and Player 3 controller control register lf bll 2 of PBCTL ts zero. I/O for lrrltes to the dilectlon borh ports (A and B) soes throush a 5520/6820. Data Resiste!-Addressed

if

bil

2 of PBCTI-ls

I

0=Swltch pressed l=Switch not pressed Right

Back

Rtght

Back

srick2 (Jack 3)

(Jack 4)

o=Swltch pressed 1=Swltch not pressed PTRIG4 PTRlG5

PTRIG6 ?TRIG7

board C

tr Top row ) 2nd Rov \ 3 r d Ror' I 4rd Top Ro\,r) znd Ror' \ 3rd Rol.' f 4th

Jack

r1r.20

4

Jack 3

Dlrectlon

m

Contlo1 Reeister-Addressed

if

blt

2 of PBCTL is 0

l p 7 l p 6 l p 5 l p 4 l p 3 l p 2 l p 1 l p 0 I

t a c h b l t c o r r e s p o n d st o a J a c k p i n 0-tnput

os SI1ADoI\IS:STICK2 (hex 27A), sTIcK3 (278), PTRIG4-7 (280-283) PBCTI (Port B Control) (D303): the Port B Control Register.

This address \rrltes

ol reads data fron

Port B Conlrol Reglster Sel up .egister as sholrn (X=Described bero!') D7

D3 D2 DO

(Read 94I) Peripheral B Interrupt Srarus Blt. Serlal bus Interrupl line. Re8et by Readlng Port B Reglster. Set by Perlpheral B Inrernrpt. Peripheral CommandIdentlflcation. Serial bus CoEnand L1ne. Controls ?or! B addresslng descrlbed above. (l= Port B Regisrer 0 = Dlrection Control Register) Perlphetal B lnterrupt Enable Bit. I = Enable. Reset by power turn-on or processor. Set by processor. (Set to he). 3c br os IRQ code)

POT0 - P0T7 (Pol Va1ues) (D200-D207): These addresses read the value (0 to 228) ot 8 pots (paddLe controllers) connected to the 8 lines por port. The paddle controllers are nuobered from left to right nhen facing the console keyboard. Turning the paddle knob clockirise results in decreasing pot values. The values are valld only after 228 TV lines follor1ng the "POTGO"connaod described beloi.' or after AJ-LPOT chanees.

D7

D6

D5

D

Each ?or Value (0-228) 0S SHADOWS: ?ADDLO- 7 (}],ex 270-211)

III.2I

ALIPOT (A11 Pot Lines Siw-rltaneouslv) (D208): present state of the 81ine pot port!

This address reads the

Capacitor dunp transitors ftrst be turned off by elthe! golng to fast pot scan node (blt 2 of SKCTL) or starting pot scan (PoTCO).

Pot runber: 7 6

5

4

3

2

I

0

0 - Pot register I = Pot register

value ls val1d. value ls not valld,

8 ?ot Lilre States

ryL9gl!le:t-.3.e1--gse4 Data

No Birs

:

Used

Thls write address atarts the pot scan sequence. The pot values (POT0 - POTT) should be read first. Thls sr1!e strobe ls then used causlog the follo!,rlng sequellce, l. 2. 3. 4. 5.

Scan Counter cleared to zero. Capacitor dullp translslors turned off. Scan Counter beglns counring. Counter value captured in each of 8 registers (POTOP0TT) as each pot line crosses trigger voltage. Counler reaches 228, capacitor dunp transistors turned

(Wrillen

to by OS ver!1cal

blank code)

TRIGo, TRIcl, TRIG2, TRIG3 (Trisqex Ports)(0 3 D013): These addresses read por! plns nordally controller trlgger buttons.

Not Used

I DO

ed

D0I0, I D0I1. 2 D012. connected to the loystick

0 = burton pressed I = butto[ not pressed

OS SHADOWS:STRIGo-3 (hex 284-287)

NOTE:

1TIIGOlhru TRIG3 are nornally read dlrectly by rhe nlcroprocessor. Ilowever, lf bil 2 of GRACTI,ls I, rhese inputs are latched wheoever they go to loglc zero. These latches are rese! (true) when bl! 2 of GRACTLls set to 0.

trl.22

PENIT(Llqht Pen Horlzontal Color Clock Posltlon) (D40C) : Thts address reads the llorlzontal l,lght Pen Register (based on the horlzontal color clock counter 1n hardnare). The values range fron 0 !o declnal 227. Wraparound pENtt occurs $hen the pel! lf near the right edge of a standard-!,/ldth screen. and PENVare nodllled when any of the loystick trlgger llnes ts pulled loir.

t

4 l D t\7

H6

tr5

E4

r

n3

H2

t

l

r{1

l{0

0S SHADOW: LPENH (hex 234) PENV (L1eht Pen Vertlcal TV Llne Posltton) (D40D) : Thls address reads the Vertlcal Light ?en Register (8 most slgnlflcant bits, sane as VCOUNT).

D7 L

D5

D6

P

8

7

5 resolutlon

OS SltADoW: LPENV (hex 23s)

Front PaneI (Conlrolfer)

Jacks as T/O Parrs:

PrA (6s2016820) Out: Io :

?olt

TIL tevels, ml levels,

A Circuit

I load 1 load

(lyp1cal): Jack

Port B Circult

6520

(typical): ot5 4.7K (B) 220

Jack

.00r

"Trlgger" PorL Circult

( typl cal ) : Jack

arl.23

supplied.

ge.!!!.9.1f9r-39:!-3.99s! : lemale (connector)

Male (console) I

3

2

5

5

4

3 8

Controllers PADDI,E (POT)

1

1 6

os

HARDI{ARE

VARIASLES

JOYSTICK

I

Iorward

Top

Blt 0 or 4**

Btt

0***

2

Back

2nd

B1t I or 5**

Blt

1:t,t*

3

Left

A(Left)rrisser

3rd Rc,l.'*

Blt 2 0r 5*:t

Rlght

| B(Risht)Trtsser I

BottonoRow,t Blt 3 or 7**

PoT B (Rlght)

1st Colunn

POl r,3,5,7

P T R I G O2, , 4 , 6 Blr 2*** ?TRTGI,3,5,7 Blt 3*** PADDLl,3,5,7

3rd colunn

1, 2 , 3 T R 1 G 0 , 1 , 2 , 3 sTRrGo

6

Trigger

Button

+5

7 8 9

GND

I

KEYBOA.R,D

PIN

5

I

2

+5

GND

PoTA (Left)

* Wrlte ** ?oRTA or PORTB * * * S T I C K0 , 1 , 2 o r 3

lat.24

2nd coluBn

P o T0 , 2 , 4 , 6

PA.DDLO,2,4,6