Analog To Digital Converters

ME 6405: Mechatronics

Analog to Digital Converters Erik Lee Gabriel Ramirez Siddharth Doshi

February 13, 2008

Georgia Institute of Technology George W. Woodruff School of Mechanical Engineering

Analog to Digital Converter Overview •Signals •ADC •ADC Properties

Georgia Institute of Technology George W. Woodruff School of Mechanical Engineering

What is an Analog Signal •Continuous in nature •Has a value at every instant in time

Georgia Institute of Technology George W. Woodruff School of Mechanical Engineering

What is a Discrete Signal •Non-continuous •No knowledge of values between samples

Georgia Institute of Technology George W. Woodruff School of Mechanical Engineering

What is an ADC? •Converts an analog signal to discrete values •Most cases it’s a voltage signal to some physical parameter (temp,pressure,etc.)

Georgia Institute of Technology George W. Woodruff School of Mechanical Engineering

ADC Properties •Quantization –Saturation

•Sampling –Aliasing

Georgia Institute of Technology George W. Woodruff School of Mechanical Engineering

Quantization •The process of converting a voltage value to a binary word. •Dependent on resolution of Analog to Digital converter •Can range from 6 to 18 bits 1.2

1

0.8

0.6

0.4

0.2

0

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Quantization

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Quantization Resolution RV =

∆V fs 2n

RV = Voltage Resolution ∆V fs = Full-Scale Voltage Range n = Number of Bits of ADC Increase Resolution

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Resolution and Saturation •To increase resolution always use a input voltage range that is equal to ADC voltage range •Can amplify signal to increase resolution •Saturation Example –ADC full-scale range is 0V to 10V –What if our analog signal is oscillation between 10V and 11V? Georgia Institute of Technology George W. Woodruff School of Mechanical Engineering

Sampling Frequency 1 Fs = Ts

Ts

= Sampling Period

Ts

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Sampling •At each sampling period the voltage value at that time will be quantized •The sampling frequency is limited by the ADC •Can vary from 1000 Hz to the MHz range

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Aliasing •Must satisfy Nyquist Criterion if we are going to try to reconstruct the signal

f sample > 2 f signal

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Aliasing •Frequencies will show up as a lower frequency

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Filtering •No matter how fast one samples, can’t guarantee there is no aliasing •Low-pass filters can be used to prevent aliasing –Butterworth •Better attenuation •Larger phase shift

–Bessel Georgia Institute of Technology George W. Woodruff School of Mechanical Engineering

Filtering/Sampling •Cutoff at 0.5 •1st order Butterworth filter Example:

ω samp = 1000 Hz ω cutoff = 500 Hz Frequencies down to 200Hz will still be attenuated.

Georgia Institute of Technology George W. Woodruff School of Mechanical Engineering

Types of ADC • Flash ADC • Delta-Sigma ADC • Dual Slope (integrating) ADC • Successive Approximation ADC

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Types of ADC • Comparison

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Types of ADC • Flash –Most high-speed oscilloscopes

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Types of ADC • Flash Advantages • Simplest in terms of operational theory • Most efficient in terms of speed, very fast • limited only in terms of comparator and gate propagation delays

Disadvantages • Lower resolution • Expensive • For each additional output bit, the number of comparators is doubled • i.e. for 8 bits, 256 comparators needed

Georgia Institute of Technology George W. Woodruff School of Mechanical Engineering

Types of ADC • Sigma Delta ADC – resolution as fine as 24 bits –Audio frequency signals

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Types of ADC • Sigma Delta ADC Disadvantages Advantages • Slow due to oversampling • High resolution • No precision external components needed

Georgia Institute of Technology George W. Woodruff School of Mechanical Engineering

Types of ADC • Dual Slope (integrating) ADC –Superior noise rejection –DMMs

Georgia Institute of Technology George W. Woodruff School of Mechanical Engineering

Types of ADC • Dual Slope ADC Advantages • Input signal is averaged • Greater noise immunity than other ADC types • High accuracy

Disadvantages • Slow • High precision external components required to achieve accuracy

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Successive Approximation ADC •Binary search through all quantization levels. •From MSB to LSB. •MSB initialized as 1. •Closed-Loop.

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Successive Approximation ADC

•Circuit

Georgia Institute of Technology George W. Woodruff School of Mechanical Engineering

Successive Approximation ADC

•Example

• 10 bit resolution or 0.0009765625V of Vref • Vin= .6 volts • Vref=1volts • Find the digital value of Vin Georgia Institute of Technology George W. Woodruff School of Mechanical Engineering

Successive Approximation ADC

• MSB (bit 9)

Divided Vref by 2 Compare Vref /2 with Vin If Vin is greater than Vref /2 , turn MSB on (1) If Vin is less than Vref /2 , turn MSB off (0) Vin =0.6V and V=0.5 Since Vin>V, MSB = 1 (on)

Georgia Institute of Technology George W. Woodruff School of Mechanical Engineering

Successive Approximation ADC • Next Calculate MSB-1 (bit 8) Compare Vin=0.6 V to V=Vref/2 + Vref/4= 0.5+0.25 =0.75V Since 0.6<0.75, MSB is turned off

Calculate MSB-2 (bit 7) Go back to the last voltage that caused it to be turned on (Bit 9) and add it to Vref/8, and compare with Vin Compare Vin with (0.5+Vref/8)=0.625 Since 0.6<0.625, MSB is turned off

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Successive Approximation ADC

•This process continues for all the remaining bits.

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Successive Approximation ADC Advantages

Disadvantages

• Capable of high speed and reliable • Medium accuracy compared to other ADC types • Good tradeoff between speed and cost • Capable of outputting the binary number in serial (one bit at a time) format.

• Higher resolution successive approximation ADC’s will be slower • Speed limited to ~5Msps

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A/D on HC11 • • • • • • •

Components (Block Diagram) Features Options Register A/D Control Register A/D Results Registers Conversion Timing Example Program Georgia Institute of Technology George W. Woodruff School of Mechanical Engineering

A/D Converter on HC11 PE0 AN0

8-BIT CAPACITIVE DAC WITH SAMPLE AND HOLD

PE1 AN1

VRL

PE2 AN2

SUCCESSIVE APPROXIMATION REGISTER AND CONTROL

PE3 AN3 PE4 AN4

VRH

ANALOG MUX

RESULT

PE5 AN5

INTERNAL DATA BUS

CCF

PE7 AN7

CA CB CC CD MULT SCAN

PE6 AN6

ADCTL A/D CONTROL RESULT REGISTER INTERFACE ADR 1

ADR 2

ADR 3

ADR 4

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Simplified Diagram Pin: 7

6

5

4

3

2

1

0

Port E (analog input) ADCTL

ADR1 - result 1

Analog Multiplexer A/D Converter

Result Register Interface

ADR2 - result 2 ADR3 - result 3 ADR4 - result 4

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Features • Charge Redistribution SAR ADC • 8 input channels, can convert 4 in one procedure, +/-0.5LSB Accuracy • Analog Input between 0-5V • Resolution = 8 bits = 256 Discrete Values = Steps of (VRH-VRL)/256 • VRL Æ #$00, VRHÆ #$FF Georgia Institute of Technology George W. Woodruff School of Mechanical Engineering

Analog Input translation Table Bit 7

6

5

4

3

2

1

Bit 0

% (VRH-VRL)

50%

25%

12.5%

6.25%

3.12%

1.56%

0.78%

0.39%

VRH= 5V VRL= 0V

2.500

1.250

0.625

0.3125

0.1562

0.0781

0.0391

0.0195

VRH= 3.3V VRL= 0V

1.65

0.825

0.4125

0.2063

0.1031

0.0516

0.0258

0.0129

Page 41, Programming Reference guide

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Option Control Register OPTION Register ($1039)

Reset:

7

6

5

4

3

ADPU

CSEL

IRQE

DLY

CME

0

0

0

1

0

2

0

1

0

CR1

CR0

0

0

ADC concerned with : ADPU – A/D power up CSEL – A/D Charge Pump Clock select DLY – Oscillator Startup Delay (4000 clock cycles)

Georgia Institute of Technology George W. Woodruff School of Mechanical Engineering

Option Control Register ADPU - A/D Charge Pump Power Up 0: Turn off the A/D 1: Turn on the A/D (by enabling the charge pump) Note: Wait 100 microseconds before using the ADC to allow charge pump and comparator circuits to stabilize.

CSEL - A/D Charge Pump Clock select 0: Use the E-clock for the A/D 1: Use internal RC oscillator that runs at around 2MHz Note: If the E-clock is 750KHz or higher, CSEL should be 0. Otherwise CSEL should be 1.

Georgia Institute of Technology George W. Woodruff School of Mechanical Engineering

A/D Control Register ADCTL Register ($1030) 7

6

CCF Reset:

0

5 SCAN

0

4 MULT

3

2

1

CD

CC

CB

Indeterminate after Reset

MULT - Single or multiple channel 0: Sample a single channel (four times) 1: Sample four channels CD,CC,CB,CA - Channel selection If MULT is 0, then CC-CA bits specify the channel If MULT is 1, then CC specifies the group: 0: Sample AN0-AN3, 1: Sample AN4-AN7 CD is reserved for factory test use CCF - Conversion Complete Flag Set when all four conversions are complete Cleared by writing to ADCTL - starts the next conversion SCAN - Continuous scan mode 0: Take one set of four conversions and stop 1: Continually perform new conversions

Georgia Institute of Technology George W. Woodruff School of Mechanical Engineering

0 CA

A/D Control Register Conversion Combinations

Single Channel (MULT = 0)

Multiple Channel (MULT = 1)

1 channel. Single Conversion Converted 4 times. Results in ADR1-4. (SCAN = 0)

4 channels. Converted once. Results in ADR1-4.

1 channel. Continuous Conversion Converted continuously. (SCAN = 1) ADR1-4 overwritten

4 channels. Converted continuously. ADR1-4 overwritten

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A/D Control Register Channel Selection CD 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1

CC 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1

CB 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1

CA 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

Channel Signal PE0 PE1 PE2 PE3 PE4 PE5 PE6 PE7 Reserved Reserved Reserved Reserved VH VL 1/2 VH Reserved

If Mult =1, ADR ADR1 ADR2 ADR3 ADR4 ADR1 ADR2 ADR3 ADR4 ADR1 ADR2 ADR3 ADR4 ADR1 ADR2 ADR3 ADR4

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A/D Results Registers ADR1-ADR4 Registers Read:

7

6

5

4

3

2

1

Write: Reset:

Indeterminate after Reset

ADR1 = $1031

Read Only.

ADR2 = $1032

Writes to these register have no effect.

ADR3 = $1033 ADR4 = $1034

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0

Conversion Sequence/Timing E Clock cycles:

Sample (12) ADCTL write (1)

Bit 7 (4) 6 (2) _ (2) 0 (2) End (2) Successive approximation

CCF

1st, ADR1 0

2nd, ADR2 32

4th, ADR4 3rd, ADR3 96 64 128 total

Georgia Institute of Technology George W. Woodruff School of Mechanical Engineering

Stop & Wait Modes Enter wait/stop mode – conversion sequence suspended Exit wait/stop mode – channel re-sampled / conversion resumed – For stop mode, A/D circuitry requires time to stabilize (10 ms or DLY bit in OPTION) Georgia Institute of Technology George W. Woodruff School of Mechanical Engineering

Program Example ORG $1040 LDAA #$80 STAA $1039 LDY #$30 LOOP

WAIT

DEY BNE

LOOP

LDAA STAA

#$00 $1030

LDX #$1030 BRCLR 0,X #$80 WAIT LDAA PSHA SWI END

OPTION ADPU=1,CSEL=0 Delay for charge pump to stabilize 100µs ADCTL SCAN=0,MULT=0, CHAN=000 Wait until CCF or bit 7=“1”

$1031 Read and store result

Georgia Institute of Technology George W. Woodruff School of Mechanical Engineering

ADC Examples •ADC0808/ADC0809 – 8-Bit µP Compatible A/D Converters with 8-Channel Multiplexer

Georgia Institute of Technology George W. Woodruff School of Mechanical Engineering

ADC Examples

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ADC Examples •Vehicles –ECU •Temp Sensor •Oxygen Sensor •RPM

•TV Tuner Card

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ADC Examples •Oscilloscope

•Music Recording

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ADC Examples •Analog signal needs to be processed, stored or transported in digital form.

Georgia Institute of Technology George W. Woodruff School of Mechanical Engineering