Analog And Digital Electronics.pdf

Syllabus From 2017-18 Academic Year

Paper–VII-(A) Elective (Electronics) Semester –VI Elective Paper –VII-(A): Analog and Digital Electronics No. of Hours per week: 04 Total Lectures:60 Unit-I (14 Hours) 1. FET-Construction, Working, characteristics and uses; MOSFET-enhancement MOSFET, depletion MOSFET, construction and working , drain characteristics of MOSFET, applications of MOSFET 2. Photo electric devices: Structure and operation, characteristics, spectral response Unit-II (10Hours) 3. Operational Amplifiers: Characteristics of ideal and practical Op-Amp (IC 741), Basic differential amplifiers, Op-Amp supply voltage, IC identification, Internal blocks of Op-Amp, its parameter off set voltages and currents. Unit-III (10 Hours) 4. Applications of Op-Amp: Op-Amp as voltage amplifier, Inverting amplifier, Non-inverting amplifier, voltage follower, summing amplifier, difference amplifier, comparator, integrator, differentiator. Unit-IV(14 Hours) 5. Data processing circuits: Multiplexers, De-multiplexers, encoders, decoders, 6. Data processing circuits: Characteristics for Digital ICs -RTL, DTL, TTL, ECL CMOS (NAND & NOR Gates). Unit-V (12 Hours) 7. Sequential digital circuits: Flip-flops, RS, Clocked SR, JK, D, T, Master-Slave, 8. Flip- flop, Conversion of Flip flops. ****************** Elective Paper-VII Practical: Analog and Digital Electronics 2hrs/Week Minimum of 6 experiments to be done and recorded 1) Characteristics of FET 2) Characteristics of MOSFET 3) Characteristics of LDR 4) Characteristics of Op-amp.(IC741) 5) Op-Amp as amplifier/inverting amplifier 6) Op-Amp as integrator/differentiator 7) Op-Amp as summing amplifier/difference amplifier 8) IC 555 as astable multivibrator 9) IC 555 as monostable amplifier 10) Master slave flip-flop 11) JK flip-flop

Model paper B.Sc. DEGREE EXAMINATIONS (Regular) (Examination at the end of Third Year)- Semester-VI Elective Paper VII-A:: Analog & Digital Electronics Maximum: 75 marks Time: Three hours Section – A Answer ALL questions (5x10=50 marks) (Essay Type Questions) 1(a).Write construction and working of FET and its characteristic curves and uses Or 1(b).Explain the structures & working of photo electric devices and & name such devices. 2(a).Differentiate the characteristics of an idea & practical op- amplifier write Internal blocks of op – amplifier. Or 2(b).How op amplifier works as voltage amplifier with blocks diagrams and write its applications. 3(a).Write briefly about non-inverting amplifier summing amplifier comparator voltage followers. Or 3(b).Design a CMOS circuit using NAND such that Y=AB + CD. write characteristics of Digital IC’S. 4(a) what are data processing circuits?. Differentiate multiplexers & de multiplexers. Or 4(b) What are the Characteristics of Digital ICs-Describe RTL and DTL ICs 5(a) Explain the concept of master – slate-flip-flop with necessary diagram & Difference between RS & clocked SR. Or 5(b).Design a circuit to convert JK Flip – Flop to D Flip –Flop what is difference between them. Section – B (5 × 5 = 25 marks) Answer any FIVE questions. 6. Differentiate between enhance MOSFET & Depleti on MOSFET. 7. Explain characteristic is of photo electric devices. 8. What are different types of operational amplifiers? 9. Draw the circuit diagram of differentiator and integrator 10..Explain encodes &decodes with suitable diagrams 11. Draw circuit diagram of T flip flop. 12 .Design NAND & NOR gates using 2:1 multiplexes. 13. Briefly explain the characterictics of different logic families. 14. Write the Applications of MOSFET

A bipolar junction transistor (BJT) is a current controlled device i.e., output characteristics of the device are controlled by base current and not by base voltage. However, in a field effect transistor (FET), the output characteristics are controlled by input voltage (i.e., electric field) and not by input current. This is probably the biggest difference between BJT and FET. There are two basic types of field effect transistors: (i) Junction field effect transistor (JFET) (ii) Metal oxide semiconductor field effect transistor (MOSFET) Junction Field Effect Transistor: A junction field effect transistor is a three terminal semiconductor device in which current conduction is by one type of carrier i.e., electrons or holes. Construction: A JFET consists of a p-type or n-type silicon bar containing two pn junctions at the sides as shown in Fig. The bar forms the conducting channel for the charge carriers. If the bar is of n-type, it is called n-channel JFET as shown in Fig. and if the bar is of p-type, it is called a p-channel JFET as shown in Fig. The two pn junctions forming diodes are connected internally and a common terminal called gate is taken out. Other terminals are source and drain taken out from the bar as shown. Thus a JFET has essentially three terminals viz., gate (G), source (S) and drain (D). Principle. The JFET operates on the principle that width and hence resistance of the conducting channel can be varied by changing the reverse voltage VGS. Working. The working of JFET is as follows : (i) When a voltage VDS is applied between drain and source terminals and voltage on the gate is zero, the two p-n junctions at the sides of the bar establish depletion layers. The electrons will flow from source to drain through a channel between the depletion layers. The size of these layers determines the width of the channel and hence the current conduction through the bar. (ii) When a reverse voltage VGS is applied between the gate and source, the width of the depletion layers is increased. This reduces the width of conducting channel, thereby increasing the resistance of n-type bar. Consequently, the current from source to drain is decreased. On the other hand, if the reverse voltage on the gate is decreased, the width of the depletion layers also decreases. This increases the width of the conducting channel and hence source to drain current. Therefore, the current from source to drain can be controlled by the application of potential (i.e. electric field) on the gate. For this reason, the device is called field effect transistor.

Note 1: a p-channel JFET operates in the same manner as an n -channel JFET except that channel current carriers will be the holes instead of electrons and the polarities of VGS and VDS are reversed. Note 2: If the reverse voltage VGS on the gate is continuously increased, a state is reached when the two depletion layers touch each other and the channel is cut off. Under such conditions, the channel becomes a non conductor. Schematic Symbol of JFET

Drain Characteristic curve: (i) Since IDSS is measured under shorted gate conditions, it is the maximum drain current that you can get with normal operation of JFET. (ii) There is a maximum drain voltage [VDS (max)] that can be applied to a JFET. If the drain voltage exceeds VDS (max), JFET would breakdown as shown in Fig. (iii) The region between VP and VDS (max) (breakdown voltage) is called constant-current region or active region. As long as VDS is kept within this range, ID will remain constant for a constant value of VGS. In other words, in the active region, JFET behaves as a constant–current device. For proper working of JFET, it must be operated in the active region. Pinch off Voltage (VP). It is the minimum drain-source voltage at which the drain current essentially becomes constant. Note: For values of VDS greater than VP, the drain current is almost constant. It is because when VDS equals VP, the channel is effectively closed and does not allow further increase in drain current. It may be noted that for proper function of JFET, it is always operated for VDS > VP. However, VDS should not exceed VDS (max) otherwise JFET may breakdown. Gate-source cut off voltage VGS(off). It is the gate-source voltage where the channel is completely cut off and the drain current becomes zero. Transfer characteristics: As the gate source voltage increases from zero to cutoff voltage, Drain current decreases from maximum value to zero. Difference Between JFET and Bipolar Transistor The JFET differs from an ordinary or bipolar transistor in the following ways :

JFET

BJT

1. Current conduction is only due to one Current conduction by both types of type of carrier either electron or hole. carriers i.e., electrons and holes.

2. Voltage driven device.

Current driven device.

3. Low noise level.

High noise level.

4. High input resistance.

Low input resistance.

5. Gain is characterized transconductance. 6. Better thermal stability.

by Gain is characterized by voltage gain. Less thermal stability.

Expression for Drain Current (ID)

Salient Features of JFET The following are some salient features of JFET : (i) A JFET is a three-terminal voltage-controlled semiconductor device i.e. input voltage controls the output characteristics of JFET. (ii) The JFET is always operated with gate-source pn junction reverse biased. (iii) In a JFET, the gate current is zero i.e. IG = 0A. (iv) Since there is no gate current, ID = IS. (v) The JFET must be operated between VGS and VGS (off). For this range of gate-to-source voltages, ID will vary from a maximum of IDSS to a minimum of almost zero. (vi) The drain current ID is controlled by changing the channel width. (vii) Since JFET has no gate current, there is no β rating of the device. We can find drain current ID. Advantages of JFET (i) It has a very high input resistance of the order of 100 MΩ. This permits high degree of isolation between the input and output circuits. (ii) FET is less noisy than BJT, because no junctions are present like BJT. So, the partition noise is absent i.e., carriers are noise free. (iii) FET is relatively less affected by radiation. (iv) It has better thermal stablility. (v) A JFET has a smaller size, longer life and high efficiency. Applications: 1. High Input Impedance Amplifier 2. Low-Noise Amplifier 3. Differential Amplifier 4. Constant Current Source 5. Analog Switch or Gate 6. Voltage Controlled Resistor. MOSFET Introduction: The main drawback of JFET is that its gate must be reverse biased for proper operation of the device i.e. it can only have negative gate operation for n-channel and

positive gate operation for p-channel. This means that we can only decrease the width of the channel (i.e. decrease the *conductivity of the channel) from its zero-bias size. This type of operation is referred to as depletion-mode operation. Therefore, a JFET can only be operated in the depletion-mode. However, there is a field effect transistor (FET) that can be operated to enhance (or increase) the width of the channel (with consequent increase in conductivity of the channel) i.e. it can have enhancement-mode operation. Such a FET is called MOSFET. Metal Oxide Semiconductor FET (MOSFET) A field effect transistor (FET) that can be operated in both depletion mode and the enhancement-mode is called a MOSFET. Types of MOSFETs There are two basic types of MOSFETs, 1. Depletion-type MOSFET or D-MOSFET. The D-MOSFET can be operated in both the depletion-mode and the enhancementmode. For this reason, a D-MOSFET is called depletion /enhancement MOSFET. 2. Enhancement-type MOSFET or E only MOSFET. The EMOSFET can be operated only in enhancement-mode. Symbols for D-MOSFET There are two types of D-MOSFETs viz (i) n-channel D-MOSFET and (ii) pchannel D-MOSFET. Construction: The gate construction of D-MOSFET. A thin layer of metal oxide (usually silicon dioxide, SiO2) is deposited over a small portion of the channel. A metallic gate is deposited over the oxide layer. As SiO2 is an insulator, gate is insulated from the channel. Note that the arrangement forms a capacitor. One plate of this capacitor is the gate and the other plate is the channel with SiO2 as the dielectric. Since the gate is insulated from the channel, we can apply either negative or positive voltage to the gate. Therefore, D-MOSFET can be operated in both depletion-mode and enhancement-mode. However, JFET can be operated only in depletion-mode. The negative-gate operation is called depletion mode whereas positive-gate operation is known as enhancement mode. (i) Depletion mode. The electrons repel the free electrons in the n-channel, leaving a layer of positive ions in a part of the channel as shown in Fig. In other words, we have depleted (i.e. emptied) the n-channel of some of its free electrons. Therefore, by changing the negative voltage on the gate, we can vary the resistance of the n-channel and hence the current from source to drain. Note that with negative voltage to the gate, the action of D-MOSFET is similar to JFET. Then it is called depletion mode.

(ii) Enhancement mode. Fig. shows enhancement-mode operation of n-channel DMOSFET. Since the gate is positive, it induces negative charges in the n-channel as shown in Fig. These negative charges are the free electrons drawn into the channel. Then, the total number of free electrons in the channel is increased. Thus a positive gate voltage enhances or increases the conductivity of the channel. The greater the positive voltage on the gate, greater is the conduction from source to drain. Transfer characteristics: (i) The point on the curve where VGS = 0, ID = IDSS. (ii) As VGS goes negative, ID decreases below the value of IDSS till ID reaches zero when VGS =VGS (off) just as with JFET. (iii) When VGS is positive, ID increases above the value of IDSS. E only MOSFET The E-MOSFET has no physical channel from source to drain because the substrate extends completely to the SiO2 layer. It is only by the application of VGS (gate-to-source voltage) of proper magnitude and polarity that the device starts conducting. The minimum value of VGS of proper polarity that turns on the E-MOSFET is called Threshold voltage [VGS (th)]. Operation: When gate is made positive (i.e. VGS is positive) as shown in Fig., it attracts free electrons into the p region. The free electrons combine with the holes next to the SiO2 layer. If VGS is positive enough, all the holes touching the SiO2 layer are filled and free electrons begin to flow from the source to drain. The effect is the same as creating a thin layer of n-type material (i.e. inducing a thin n-channel) adjacent to the SiO2 layer. Thus the E-MOSFET is turned ON and drain current ID starts flowing form the source to the drain. Transfer characteristics: When VGS is less than VGS (th), there is no induced channel and the drain current ID is zero. When VGS is equal to VGS (th), the E-MOSFET is turned ON and the induced channel conducts drain current from the source to the drain. Beyond VGS (th), ID increases. If the value of VGS decreases, the channel becomes narrower and ID will decrease.

Uses of MOSFET: 1. MOSFETs are used even in the case of motor control applications. 2. MOSFETs are used to perform switching actions in case of basic buck converters used in DC-DC power supplies. 3. MOSFET working leads to their usage as a switch. 4. MOSFET is used in chooper circuits. 5. Depletion type MOSFETs in source-follower configuration are used in linear voltage regulator circuits. Differentiate between enhance MOSFET & Depletion MOSFET. D-MOSFET : 1.Voltage from gate to source(Vgs) can be positive or negative. 2.Has two modes of operation: depletion and enhancement mode. 3.Biasing: Self bias, Gate bias, Voltage divider bias, Zero bias. 4. No threshold voltage. E-MOSFET : 1.Voltage from gate to source(Vgs) is always positive. 2.Has one mode of operation: enhancement mode. 3.Biasing: Gate bias, Voltage divider bias, Drain feedback bias. 4.E-MOSFETs have threshold voltage. Photo electric devices: photoelectric effect: The photoelectric effect refers to the emission, or ejection, of electrons from the surface of, generally, a metal in response to incident light. That is, the average energy carried by an ejected (photoelectric) electron should increase with the intensity of the incident light. Photoelectric Device An electron device in which an electromotive force (emf) or photoelectric current is generated as a result of the absorption of the energy of optical radiation that is incident on the device is called photo electric device. Or A device which gives an electrical signal in response to visible, infrared, or ultraviolet radiation called photo electric devices.  Phototubes are vacuum-tube devices that operate on the basis of photoemission.  photocells are solid-state devices that operate on the basis of the internal photoelectric effect of photo-emf generation. Photo tube: A typical phototube is a two-electrode vacuum-tube device that contains a photocathode and an anode, or electron collector. The electrodes are placed in an evacuated or gas-filled envelope made of glass or quartz. A luminous flux that is incident on the photocathode causes photoemission from the cathode’s surface; when the

phototube’s circuit is closed, a photoelectric current that is proportional to the luminous flux flows in the circuit. In gas-filled phototubes, the photoelectric current is amplified as a result of the ionization of the gas and the occurrence of a non-self-sustaining avalanche gas discharge. The most widely used phototubes have cesium anti monide or cesium oxide-silver photo cathodes.

Figure 1. Schematic diagrams of: (a) a phototube and (b) a photocell Photocell: A photocell is a semiconductor device with a homogeneous p-n junction diode. The absorption of optical radiation in photocells causes an increase in the number of free carriers in the semiconductor. The electric field at the junction or contact spatially separates the charge carriers; for example, in a p-n-type photocell, the electrons accumulate in the n-region and the holes, in the p-region. Consequently, a photo-emf is generated between the layers. When the external circuit of a photocell is closed through a load, an electric current begins to flow. Photocells are made of such materials as Se, GaAs, CdS, Ge, or Si. Photocells are often photo-diodes. Photocells are also used for the direct conversion of the energy of solar radiation to electric energy in solar batteries and photovoltaic converters. Light Emitting Diode(LED), Light depending resistor, solar cell are such devices. characteristics of photoelectric devices: 1. The luminous sensitivity is the ratio of the photoelectric current to the luminous flux producing the current at the rated anode voltage (for phototubes) or when the output terminals are short circuited (for photocells). 2. The spectral response gives the optical wavelength range in which a given photoelectric device is sensitive. For example, this wavelength range is 0.2–0.7 micrometers (μm) for a phototube and 0.5–2.0 μm for a germanium photocell. 3. The current-voltage characteristic shows the relationship between the photoelectric current and the voltage across a given photoelectric device with a constant luminous flux and makes it possible to determine the best operating conditions for the device. 4. The conversion efficiency (also applicable to solar cells) is the ratio of the electric power generated by a given device at a nominal load and the incident luminous power. Applications:  Visual signals where light goes more or less directly from the source to the human eye, to convey a message or meaning  The light from LEDs can be modulated very quickly so they are used extensively in optical fiber and free space optics communications.  This includes remote controls, such as for TVs, VCRs, and LED Computers, where infrared LEDs are often used.

 LED combined with a photodiode or phototransistor to provide a signal path with electrical isolation between two circuits.  This is especially useful in medical equipment where the signals from a lowvoltage sensor circuit.  LEDs are used as motion sensors, for example in optical computer mice. **** ALL THE BEST ****

Operational Amplifiers: Characteristics of ideal and practical Op-Amp (IC 741), Basic differential amplifiers, Op-Amp supply voltage, IC identification, Internal blocks of Op-Amp, its parameter off set voltages and currents.

The operational amplifier: An operational amplifier is a direct coupled high gain amplifier consisting of one or more differential (OPAMP) amplifiers and followed by a level translator and an output stage. An operational amplifier is available as a single integrated circuit package. Differential amplifier: A differential amplifier is a type of electronic amplifier that amplifies the difference between two input voltages but suppresses any voltage common to the two inputs. Construction: Let us consider two identical emitter biased circuits as shown in the fig.  Q1, Q2 be two transistors having same characteristics.  RE1= RE2 and RC1= RC2.  The magnitude of +VCC is equal in the magnitude of – VEE . These supply voltages are measured with respect to ground.  We should recollect these two circuits as follows to obtain differential amplifiers as shown in the figure. o Recollect +Vcc supply voltages of the two circuits since the voltages are of the same polarity and magnitude. Similarly –VEE supply voltages. o Recollect the emitter E1 of the transistor Q1 to the emitter E 2 of the transistor Q2 . Then, RE1∥RE2= RE. o Show the input signal Vin1applied to the base B1 of the transistor Q1 and Vin2applied to the base B2 of transistor Q2 . o Label the voltage between the collectors C1 and C2 as Vo refers output voltage. o The resultant circuit is known as “Differential Amplifier”. o The output of the differential amplifier is Vo= A(Vin1-Vin2). Where A = differential gain, (Vin1-Vin2) = difference of the two input voltages. Working: (i) Suppose the signal is applied to input 1 and input 2 is grounded as shown in Fig. The transistor Q1 will act in two ways: as a common emitter amplifier and as a common collector amplifier. As a common emitter amplifier, the input 1 will appear at output 1 (i.e., collector of Q1) as amplified inverted signal as shown in Fig. As a common collector amplifier, the signal appears on the emitter of Q1 in phase with the input and only slightly smaller. Since the emitters of Q1 and Q2 are common, the emitter signal becomes input to Q2. Therefore, Q2 Page 1 of 5

functions as a common base amplifier. As a result, the signal on the emitter of Q2 will be amplified and appears on output 2 (i.e., collector of Q2 ) in phase with the emitter signal and hence in phase with the input signal. (ii) Now suppose the signal is applied to input 2 and input 1 is grounded. As explained above, now Q2 acts as a common emitter amplifier and common collector amplifier while Q1 functions as a common base amplifier. Therefore, an inverted and amplified signal appears at output 2 and non -inverted, amplified signal appears at output 1. When signal applied to the input of DA produces no phase shift in the output, it is called non inverting input. When the signal applied to the input of DA produces 180° phase shift, it is called inverting input. It is often identified with (–) sign. The non inverting input is then represented by (+) sign. It may be noted that terms non inverting input and inverting input are meaningful when only one output terminal of DA is available. Classification: The configurations are classified into four types depending on the no. of input signals used and the way an output voltage is measured. Those are… 1. Dual input; balanced output differential amplifier. 2. Dual input; unbalanced output differential amplifier. 3. Single input; balanced output differential amplifier. 4. Single input; unbalanced output differential amplifier.

If we use two input signals the configuration is said to be Dual input. Otherwise it is a single input configuration. On the other hand, if the output voltage is measured between two collectors, it is referred to as a balanced output, because both collectors are at d.c potential with respect to ground. However, if the output is measured at one of the collector with respect to ground, the configuration is called an unbalanced output. The configurations are as shown in the figure.

Block diagram of Op-Amp: The block diagram of OPAMP is shown in the figure.

Page 2 of 5

Input stage: The input stage is Dual input, balanced output differential amplifier. This stage is generally provides most of the voltage gain of amplifier and also establishes the input resistance of the operational amplifier. Intermediate stage: It is usually another stage of differential amplifier which drives by the output of the first stage. In most amplifiers, the intermediate stage is dual input unbalanced output differential amplifier. Level shifting stage: Because direct coupling is used the d.c voltage at the output of the intermediate stage is well above the ground potential. Therefore, the level translator circuit is used after the intermediate stage to shift the d.c level at the output of an intermediate stage downward to zero volts with respect to ground. Generally, level shifting stage is the emitter follower using constant current bias circuit. Output stage: The final stage is usually a push-pull complementary symmetry amplifier. The output stage increases the output voltage swing and rises the current supplying capability of the operational amplifier. Pin configuration of IC-741:

Pin 1 & 5: These pins are used to reduce output off-set voltage to zero volts. Pin 2: This pin is known as inverting input terminal. Pin 3: This pin is known as non-inverting input terminal. Pin 4 & 7 : These are the power supply about -15V & +15V. Pin 6: This is used to measure output voltage with respect to ground. Pin 8: No connection for the favor of symmetric view. Characteristics of an Ideal Op-Amp: 1. Input resistance must be infinite. 2. Output resistance should be as small as zero. 3. Bandwidth should be as wide as infinite. Page 3 of 5

4. Voltage gain should be as high as infinite. 5. Characteristics of Op-Amp should not change with temperature. 6. Output Vo =0, when input Vi=0. 7. Common mode rejection ratio (CMRR) should tend as infinite. 8. Slew rate should tend as infinite. Characteristics of Practical op-amp: 1. very high voltage gain, very high input impedance and very low output impedance. 2. The input voltage Vin appears between the two input terminals and the output voltage is AvVin taken through the output impedance Zout. 3. Since the voltage gain (Av ) of a practical OP-amp is very high, an extremely small input voltage (vin ) will produce a large output voltage (vout). 4. Since the input impedance (Z in) is very high, a practical OP-amp has very small input current. 5. Since the output impedance (Zout) of a practical OP-amp is very low, it means that output voltage is practically independent of the value of load connected to OP-amp.

Parameters of op – amp: 1. Input offset voltage(Vio ): It is the voltage that must be applied between the two input terminals to null the output offset voltage. This voltage could be positive or negative. Input offset voltage Vio= Vdc1-Vdc2 For IC 741, Vio= 6 milli volts d.c. 2. Input bias current (I B): Input bias current IB is the average of the currents that flow into the inverting and non-inverting terminals of the op-amp. I +I Input bias current IB= B1 2 B2= 500mA 3. Input offset current (Iio ): The algebric difference between currents into the inverting and non-inverting terminals is referred to as input offset current Iio . Iio= |IB1-IB2|= 6mA 4. Common Mode Rejection Ratio: It is the ratio of differential voltage gain (Ad ) to the common mode voltage gain (ACM ). VO= AdVin1-Vin2 VO= AdVid

Ad=

VO Vid Vocm= AcmVcm Vocm Acm= Vcm Page 4 of 5

CMRR= For Ideal op-amp, Vocm= 0, CMRR= ∞. For IC 741, CMRR= 90dB.

Ad VO Vcm = × Acm Vid Vocm

Importance of CMRR. The CMRRis the ability of a DA to reject the common-mode signals. The larger the CMRR, the better the DA is at eliminating common-mode signals. Let us illustrate this point. Suppose the differential amplifier has a differential voltage gain of 1500 (i.e., ADM =1500) and a common-mode gain of 0.01 (i.e., ACM = 0.01). CMRR =

1500 = 150,000 0.01

This means that the output produced by a difference between the inputs would be 150,000 times as great as an output produced by a common-mode signal. The ability of the DA to reject common-mode signals is one of its main advantages. Common mode signals are usually undesired signals caused by external interference. For example, any RF signals picked up by the DA inputs would be considered undesirable. The CMRR indicates the DA’s ability to reject such unwanted signals. 5. Slew Rate (SR): It is defined as the maximum rate of change of output voltage and is

dV

6. 7. 8. 9.

expressed in volts per microsecond.SR= omaxV μsec. dt It indicates how rapidly the output of op-amp can change in respons to changes in input frequency. For IC 741, SR= 0.5V μsec. and for ideal op-amp, SR= ∞. Differential input resistance(Ri): It is the equivalence resistance that can be measured at either the inverting or non-inverting input terminal with the other terminal connected to the ground. For IC741, Ri=2MΩ. Output resistance(Ro ): It is the equivalent resistance that can be measured between the output terninal of the op-amp and the ground. For IC741, Ro=75Ω. Power consumption: It is the amount quiescent power(Vin =0V) that must be consumped by the op-amp in orderr to operate properly. For IC741, 85mH. Supply current: It is corrent drawn by the op-amp from powersupply. For IC741, 2.8mA.

Page 5 of 5

Unit III: Applications of Op-Amp: Op-Amp as voltage amplifier, Inverting amplifier, Non-

inverting amplifier, voltage follower, summing amplifier, difference amplifier, comparator, integrator, differentiator.

Applications of Op-Amp: Slew Rate: Amplifier means low signal converts into high signal. But, we are giving high signal as the input. In the op-amp, there are internal capacitors are there. It takes a finite time to change. The feedback does get wait much time. So, it give bad signal i.e., called as slew rate. The op-amp normally operates with very small input Vi at the amplifier input. This represents between the difference V1 and the feedback voltage Vf. Suppose a stop function of large signal Vi is applied the internal capacitors of the amplifier and the feedback loop can’t change the voltage rapidly. And finite time is required for Vo to respond to the step. The feedback is delayed played in its return to the input and the amplifier input voltage Vi is very large. This drives the amplifier into saturation. Until the feedback voltage can respond. So, a distorted output waveform appears. The slew rate may be defined as the time rate of charge of closed loop amplifier output under large signal condition. Virtual ground: The branch point ‘s’ has a special significance in op-amp. This may be explain by determent the effective impedance between s and

R

ground, which is given byZS= 1+fA. According to the equation, the impedance of ‘s’ to the ground is very low. If the gain is large. The low impedance results from the negative feedback voltage which cancels the input signal at ‘s’ and tends to keep the branch point at ground potential. For this reason, the point ‘s’ is called Virtual Ground. Although ‘s’ kept at ground potential by the feedback action no current to the ground exit at this point. Op-amp as Differential amplifier or voltage amplifier: The function of differential amplifier is to amplify the difference between two signaals. The differenttial amplifier is used in physical instruments. Differential amplifier also forms an basic stage of an integrated op-amp with differential inputs. The figure shows a linear active device with two input signals V1 and V2 and one output signal Vo. Each measured with respect to the ground in an ideal differential amplifier. The output signal should be given by, VO= AdV1-V2. Where, Ad is the differential amplifier gain of the amplifier. Thus, any signal which is common to both inputs will have no effect on the output voltage. However, a practical differential amplifier cannot be described by equation 1. This is because output depends not only upon the different signal Vd i.e., (V1 - V2) of the two signals but also upon the average V +V signal is called “common mode signal” Vocm= 1 2 2. Page 1 of 7

Op-amp as Inverting amplifier: The input resistance Ri is infinite for an ideal op-amp. But, for practical amplifier it must be larger than output resistance. Thus, the closed loop gain AVF for the amplifier can be obtained by applying Kirchoff’s law. Iin= IB+IF Since, Rin is very large the input biasing current IB is very small. Iin= IF Vin-V2 V2-Vo = →1

Ri Rf VO= AV1-V2= -AV2 [V1= 0] -Vo V2= A Vin+Vo A -Vo A-Vo from eqn.1, = Ri Rf AVin+Vo -Vo -AVo = AR i ARf Rf[AVin+Vo ]= Ri[-Vo-AVo ] RfAVin+RfVo= -RiVo -RiAVo -RfAVin= Vo(Ri+RiA+Rf) Vo -ARf = Vin Ri+RiA+Rf

Since, the internal gain A of the amplifier is very large. Therefore, ARi is greater than Ri+Rf. Vo -ARf -Rf = =

Vin

ARi

Ri

The negative sign indicates that input and output are out of phase by 180o . Op-amp as Non-inverting Amplifier: The circuit as shown in the figure is commonly known as non inverting amplifier with feedback because it uses feedback and the input signal is applied to the inverting input terminal of the op-amp. The feedback circuit is composed of two resistors Ri and Rf. The feedback in this arrangement in voltage series feedback, referring to the circuit. Vid= V1-V2 The differential voltage is equal to the input voltage Vin , the feedback voltage Vf in the other words the feedback voltage is always oppose the input voltage. Hence, the feedback is said to be negative.

V

Closed loop gain AvF= V o

in

But we know that Vo= AV1-V2 Here, V1= Vin Page 2 of 7

Vo R Ri+RF i Vo Vo= AVinR Ri+RF i AVo Vo= AVinR Ri+RF i VoRi+RF= AVinRi+RF-AVoRi VoRi+RF+ARi= AVinRi+RF Vo ARi+RF = Vin Ri+RF+ARi V2=

The internal gain ARi≫Ri+RF so, we may neglect it. Vo ARi+RF RF = = 1+

Vin

AR i

Ri

The voltage gain of a non inverting amplifier can be made equal to or greater than 1. The voltage gain is positive. This is not surprising because output signal is in phase with the input signal. Voltage Follower: The voltage follower arrangement is a special case of non inverting amplifier where all of the output voltage is fed back to the inverting input as shown in Fig. Note that we remove Ri and Rf from the non inverting amplifier and short the output of the amplifier to the inverting input. The voltage gain for the voltage follower is calculated as under: Vo RF 0 ACL= = 1+ = 1+ (∵RF= 0Ω)

Vin

Ri

Ri

Thus the closed-loop voltage gain of the voltage follower is 1. The most important features of the voltage follower configuration are its very high input impedance and its very low output impedance. These features make it a nearly ideal buffer amplifier to be connected between high-impedance sources and low-impedance loads. Summing Amplifiers: A summing amplifier is an inverted Op-amp that can accept two or more inputs. The output voltage of a summing amplifier is proportional to the negative of the algebraic sum of its input voltages. Hence the name summing amplifier. Fig. shows a three-input summing amplifier but any number of inputs can be used. Three voltages V1 ,V2 and V3 are applied to the inputs and produce currents I1 , I2 and I3 . Using the concepts of infinite impedance and virtual ground, you can see that inverting input of the Op-amp is at virtual ground (0V) and there is no current to the input. This means that the three input currents I1, I2 and I3 combine at the summing point A and form the total current (If) which goes through Rf as shown in Fig. ∴ IF= I1+ I2+ I3 When all the three inputs are applied, the output voltage is Output voltage, Page 3 of 7

Thus the output voltage is proportional to the algebraic sum of the input voltages (of course neglecting negative sign). An interesting case results when the gain of the amplifier is unity. In that case, Rf= R1= R2= R3 and output voltage is Thus, when the gain of summing amplifier is unity, the output voltage is the algebraic sum of the input voltages. Applications of Summing Amplifiers: By proper modifications, a summing amplifier can be made to perform many useful functions. 1. As averaging amplifier 2. As subtractor Averaging amplifier. By using the proper input and feedback resistor values, a summing amplifier can be designed to provide an output voltage that is equal to the average of input voltages. A summing amplifier will act as an averaging amplifier when both of the following conditions are met: (i) All input resistors (R1, R2 and so on) are equal in value. (ii) The ratio of any input resistor to the feedback resistor is equal to the number of input circuits. Fig. shows the circuit of averaging amplifier. Note that it is a summing amplifier meeting the above two conditions. All input resistors are equal in value (3 kΩ). If we take the ratio of any input resistor to the feedback resistor, we get 3 kΩ/ 1 kΩ= 3. This is equal to the number of inputs to the circuit. Referring to the circuit in Fig, the output voltage is given by;

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Note that Vout is equal to the average of the three inputs. The negative sign shows the phase reversal. Subtractor: A summing amplifier can be used to provide an output voltage that is equal to the difference of two voltages. Such a circuit is called a subtractor and is shown in Fig. As we shall see, this circuit will provide an output voltage that is equal to the difference between V1 and V2 . The voltage V1 is applied to a standard inverting amplifier that has unity gain. Because of this, the output from the inverting amplifier will be equal to –V1. This output is then applied to the summing amplifier (also having unity gain) along with V2 . Thus output from second OP-amp is given by; It may be noted that the gain of the second stage in the subtractor can be varied to provide an output that is proportional to (rather than equal to) the difference between the input voltages. However, if the circuit is to act as a subtractor, the input inverting amplifier must have unity gain. Otherwise, the output will not be proportional to the true difference between V1 and V2 . Integrators: A circuit that performs the mathematical integration of input signal is called an integrator. The output of an integrator is proportional to the area of the input waveform over a period of time. An integrator is a circuit that performs integration of the input signal. The most popular application of an integrator is to produce a rampoutput voltage (i.e.a linearly increasing or decreasing voltage). Fig. shows the circuit of an OP-amp integrator. It consists of an OP-amp, input resistor Rand feedback capacitor C. Note that the feedback component is a capacitor instead of a resistor. when a signal is applied to the input of this circuit, the output-signal waveform will be the integration of input-signal waveform. Because of virtual ground and infinite impedance of the OP-amp, all of the input current i flows through the capacitor i.e. i = ic.

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Eq. shows that the output is the integral of the input with an inversion and scale multiplier of 1/RC. Differentiator: A circuit that performs the mathematical differentiation of input signal is called a differentiator. The output of a differentiator is proportional to the rate of change of its input signal. A differentiator is a circuit that performs differentiation of the input signal. In other words, a differentiator produces an output voltage that is proportional to the rate of change of the input voltage. It’s important application is to produce a rectangular output from a ramp input. Fig. shows the circuit of OP-amp differentiator. It consists of an OP-amp, an input capacitor C and feedback resistor R. Note how the placement of the capacitor and resistor differs from the integrator. The capacitor is now the input element. Because of virtual ground and infinite impedance of OP-amp, all the input current ic flows through the feedback resistor R i.e. ic= iR.

Eq. shows that output is the differentiation of the input with an inversion and scale multiplier of RC. We see that if the input voltage is constant, dvi/dt is zero and the output voltage is zero. The faster the input voltage changes, the larger the magnitude of the output voltage. Comparators: Often we want to compare one voltage to another to see which is larger. In this situation, a comparator may be used. A comparator is an OP-amp circuit without negative feedback and takes advantage of very high open-loop voltage gain of OP-amp. A comparator has two input voltages (non inverting and inverting) and one output voltage. Because of the high open-loop voltage gain of an OP-amp, a very small difference voltage between the two inputs drives the amplifier to saturation. For example, consider an OP-amp having AOL= 100,000. A voltage difference of only 0.25 mV between the inputs will produce an output voltage of (0.25 mV) (100,000) = 25V. However, most of OP-amps have output voltages of less than ± 15V because of their d.c. supply voltages. Therefore, a very small differential input voltage will drive the OP-amp to saturation. This is the key point in the working of comparator. Fig. illustrates the action of a comparator. The input voltages are v1 and v2 . If the differential input is positive, the Page 6 of 7

circuit is driven to saturation and output goes to maximum positive value. Reverse happens when the differential input goes negative i.e. now output is maximum negative (– Vsat= – 13V). This circuit is called comparator because it compares v1 to v2 to produce a saturated positive or negative output voltage. Note that output voltage rapidly changes from – 13V to + 13V and vice-versa.

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Unit IV: 5. Data processing circuits: Multiplexers, De-multiplexers, encoders, decoders, 6. Data processing circuits: Characteristics for Digital ICs -RTL, DTL, TTL, ECL CMOS (NAND & NOR Gates). Data processing circuits: Data is information that has been translated into a convenient form to process. Data processing circuits are logic circuits that process binary data. Such logic circuits are……. 1. Multiplexer (MUX) 2. De Multiplexer (DMUX) 3. Encoder 4. Decoder Multiplexers: The multiplexer, is a combinational logic circuit designed to switch one of several input lines through to a single common output line by the application of a control signal. It is also called data selector. It follows the formula 2 = Where ‘m’ is number of selection lines and ‘n’ is number of inputs. It has 4:1, 8:1, 16:1 multiplexers. 4:1 Multiiplexer: It has data select inputs which permit digital data on any one of the inputs to be switched to the output line. The logic block diagram for a four input multiplexer is as shown in the figure. Here, we use four AND gates with two inputs as selection lines and one input as data line. All the outputs of AND gates are connected as inputs of OR gate as shown. Finally, the output of OR gates leads the process. Working: Case 1: If a binary (S1=0, S0=0) is applied to the data select line, the data on the input D0 appears on the data output. = Case 2: If a binary one (S1=0, S0=1) is applied to the data select line, the data on the input D1 appears on the data output line. = Case 3: If a binary one (S1=1, S0=0) is applied to the data select line, the data on the input D2 appears on the data output line. = Case 4: If a binary one (S1=1, S0=1) is applied to the data select line, the data on the input D3 appears on the data output line. = The total expression for the data o/p is … = + + + Applications of Multiplexer: Multiplexer are used in various fields where multiple data need to be transmitted using a single line. 1. It allow the process of transmitting different type of data such as audio, video (Communication system) at the same time using a single transmission line. Page 1 of 12

2. In telephone network, multiple audio signals are integrated on a single line. 3. These are used to implement huge amount of memory into the computer, at the same time reduces circuit connections. 4. It can be used for the transmission of data signals from the computer system of a satellite or spacecraft to the ground system using the GPS (Global Positioning System) satellites. De-Multiplexer: A demultiplexer (or demux) is a device that takes a single input line and routes it to one of several digital output lines. A demultiplexer is also called a data distributor. Demultiplexer means one to many. A demultiplexer is a circuit with one input and many output. By applying control signal, we can steer any input to the output. Few types of demultiplexer are 1-to 2, 1-to-4, 1-to-8 and 1-to 16 demultiplexer. 1:4 De Multiplexer: A Demultiplexer basically reverse the multiplexing function. The figure shows a one line to four line de multiplexer circuit. The data i/p line goes to all of the AND gates. The two data select lines enable only one gate at a time and the data appear in o/p line. This data bit is transmitted to the data bit of the output lines. This depends on the value of S1 and S0, the control input. Case 1: When S1=0, S0=0, the upper first AND gate is enabled while other AND gates are disabled. Therefore, only data bit ‘I’ is transmitted to the output, giving Y0 = I. Case 2: When S1=0, S0=1, the second AND gate is enabled while other AND gates are disabled. Therefore, only data bit ‘I’ is transmitted to the output, giving Y1 = I. Case 3: When S1=1, S0=0, the third AND gate is enabled while other AND gates are disabled. Therefore, only data bit ‘I’ is transmitted to the output, giving Y2 = I. Case 4: When S1=1, S0=1, the upper first AND gate is enabled while other AND gates are disabled. Therefore, only data bit ‘I’ is transmitted to the output, giving Y3 = I. Applications of Demultiplexer: 1. Demultiplexer is used to connect a single source to multiple destinations. 2. Demultiplexer are also used for reconstruction of parallel data and ALU circuits. 3. The multiplexer and demultiplexer work together to carry out the process of transmission and reception of data in communication system. 4. In an ALU circuit, the output of ALU can be stored in multiple registers or storage units with the help of demultiplexer. 5. It is used in serial to parallel converter, which is used for reconstructing parallel data from incoming serial data stream. Page 2 of 12

2-input AND gate implementation using 2:1 mux: Figure below shows the truth table of a 2-input AND gate. If we observe carefully, OUT equals '0' when A is '0'. And OUT follows B when A is '1'. So, if we connect A to the select pin of a 2:1 mux, AND gate will be implemented if we connect D0 to '0' and D1 to 'B'.

Figure 1: Truth table of AND gate Figure 2 below shows the implementation of 2-input AND gate using a 2:1 multiplexer.

Figure 2: Implementation of AND gate using a 2:1 mux 2-input NAND gate using 2:1 mux: Figure below shows the truth table of a 2-input NAND gate. If we observe carefully, OUT equals '1' when A is '0'. Similarly, when A is '1', OUT is B'. So, if we connect SEL pin of mux to A, D0 pin of mux to '1' and D1 to B', then it will act as a NAND gate.

Figure 3: Truth table of 2-input NAND gate Figure 4 below shows the implementation of a 2-input NAND gate using 2:1 mux.

Figure 4: Implementation of 2-input NAND gate using 2:1 mux

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2-input OR gate using 2x1 mux: Figure 5 below shows the truth table for a 2-input OR gate. If we observe carefully, OUT equals B when A is '0'. Similarly, OUT is '1' (or A), when A is '1'. So, we can make a 2:1 mux act like a 2-input OR gate, if we connect D0 pin to B and D1 pin to A, with select connected to A.

Figure 5: Truth table of 2-input OR gate Figure 6 below shows the implementation of 2-input OR gate using a 2:1 multilpexer:

Figure 6: Implementation of 2-input OR gate using 2:1 mux 2-input NOR gate using 2x1 mux: Figure 7 below shows the truth table of a 2-input NOR gate. If we observe carefully, OUT equal B' when A is '0'. Similarly, OUT equals '0' when A is '1'. So, we can make a 2-input mux act like a 2-input NOR gate, if we connect SEL of mux to A, D0 to B' and D1 to '0'.

Figure 7: Truth table of 2-input NOR gate Figure 8 shows the implementation of 2-input NOR gate using 2:1 mux.

Figure 8: Implementation of 2-input NOR gate using 2x1 mux 2-input XOR gate using 2x1 mux: Figure 11 shows the truth table for a 2-input XOR gate. If we observe carefully, OUT equals B when A is '0' and B' when A is '1'. So, a 2:1 mux can be used to implement 2-input XOR gate if we connect SEL to A, D0 to B and D1 to B'.

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Figure 11: Truth table of 2-input XOR gate Figure 12 shows the implementation of 2-input XOR gate using 2x1 mux.

Implementation of 2-input XOR gate using 2x1 mux NOT gate using 2:1 mux: Figure 13 shows the truth table for a NOT gate. The only inverting path in a multiplexer is from select to output. To implement NOT gate with the help of a mux, we just need to enable this inverting path. This will happen if we connect D0 to '1' and D1 to '0'.

Figure 13: Truth table of NOT gate Figure 14 shows the implementation of NOT gate using 2x1 mux:

Figure 14: Implementation of NOT gate using 2x1 mux Differences between Multiplexer and De Multiplexer: Multiplexer1. Many inputs & one output. 2. Data is selected by select lines. 3. Parallel to serial conversion. 4. When we design multiplexer, we don't need additional gates. 5. Example- 8:1, 16:1, 32:1

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Demultiplexer1. One inputs & many output. 2. Data distributer. 3. Serial to parallel conversion. 4. When we design demultiplexer, we need additional gates. 5. Example- 1:8, 1:16, 1:32.

Encoder: When we insert any character or symbol to a digital system, through key board, it is needed to be encoded in machine readable farm. Digital systems like computer etc, cannot read the characters or symbol directly. The system reads and computes any characters, numbers and symbols in their digital form. An encoder does the job that means, it converts different human readable characters or symbol to their equivalent digital format. An encoder is basically multi inputs and multi outputs digital logic circuit, which has as many inputs as the number of character to be encoded and as many outputs as the number of bits in encoded form of characters. Suppose we have to design an encoder which will encode 10 characters (from 0 to 9). The encoded form of each character would be 4 bit binary equivalent. Then the encoder will have 10 numbers of input lines and each for one character. There will be four output lines to represent 4 bit encoded form of each input character. Similarly for encoding M numbers of characters in N bit format, we need M input N output digital encoder. In encoder normally, the input of which encoding to be done, is made high, other all inputs remain low at that time. That means a digital encoder works on active high input. To understand about a digital encoder let us design the above decimal to binary encodes. The truth table for 10 inputs 4 output encoder would be, From truth table it is found, that output A would be high at D8, D9. So, it can be written as Page 6 of 12

This circuit can also be considered as Decimal to BCD encoder. Decoder: The decoder is an electronic device that is used to convert digital signal to an analogue signal. It allows single input line and produces multiple output lines. The decoders are used in many communication projects that are used to communicate between two devices. The decoder allows N- inputs and generates 2 power N-numbers of outputs. For example, if we give 2 inputs that will produce 4 outputs by using 4 by 2 decoder. The encoders and decoders are designed with logic gates such as AND gate. There are different types of decoders like 4, 8, and 16 decoders and the truth table of decoder depends upon a particular decoder chosen by the user. The subsequent description is about a 4-bit decoder and its truth table. The four bit decoder allows only four outputs such as D0, D1, D2, and D3 as shown in the below diagram. 2-to-4 line Decoder In this type of encoders and decoders, decoders contain two inputs A1, A0 and four outputs represented by D0, D1, D2, and D3. As you can see in the truth table – for each input combination, one output line is activated. In this example, you can notice that, each output of the decoder is actually a minterm, resulting from a certain inputs combination, that is: D0 =A1 A0, which corresponds to input 00 D1 =A1 A0, which corresponds to input 01 D2 =A1 A0, which corresponds to input 10 D3 =A1 A0, which corresponds to input 11 The circuit is implemented with AND gates, as shown in the figure. In this circuit, the logic equation for D0 is A1.A0, and so on. Thus, each output of the decoder will be generated to the input combination.

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Logic families: Most digital systems are desired by combining various logic functions all these logic circuits are available in IC modules and are divided into many families each family is classified by abbreviations which indicate the type of logic circuit used.  Resistor-Transistor Logic (RTL)  Diode-Transistor Logic (DTL)  Transistor-Transistor Logic (TTL)  Emitter Coupled Logic (ECL)  Complementary Metal Oxide Semiconductor Logic (CMOS) Resistor-Transistor Logic (RTL): It was the first family group of logic circuits to be developed and packaged in IC form in early 1960s. Diode-Transistor Logic (DTL): It is followed RTL in a late 1960s. Transistor-Transistor Logic (TTL): It was introduced in the early 1970s. Emitter Coupled Logic (ECL): It is the fastest logic line currently available. Complementary Metal Oxide Semiconductor Logic (CMOS): It has the lowest power consumption and high fan out of the currently available logic circuit. Characteristics of Digital Integrated Circuits: 1. Speed of operation: The Speed of operation of a digital circuit is given in terms of the propagation delay time. The input delay times and output delay times can be demonstrated as: The delay times are measured in between the 50% voltage levels of input and output wave forms. 2. Power Dissipation: It is the amount of power dissipated in an IC. It is determined through the current, ICC that this draws from the Vcc supply and is provided by Vcc x Icc. Icc is the average value of ICC [O] and ICC [1]. This is specified in mW. 3. Figure of merit: For digital IC, this is explained as the product of speed and power. This is specified in Pico joules i.e. nanoseconds x milli watt = pj. The low value of speed power product is required. 4. Fan in: The fan in of a logic gate is the number of input that the logic gate can handle properly. 5. Fan Out: It is the no of the same gates that can be driven by a gate. High fan out is beneficial, as this reduces the requirement for additional drivers to drive more gates. 6. Noise Immunity: Stray electric and magnetic fields make unnecessary voltages termed as noise, on the connecting wires in between logic circuits and may generate unwanted operation. The circuit's capability to tolerate noise signals is termed to as the noise immunity. 7. Operating Temperature: A range of temperature wherein an IC functions properly should be identified. The accepted temperature range for consumer IC' s are from 0 to 70 degree C and for industrial applications [from 55° C to +125° C for military applications]. Resistor-Transistor Logic (RTL): Resistor-Transistor gates are not very Page 8 of 12

expensive and are very simple to construct. The RTL logic NOR is as shown in the figure. Operation: we will assume ideal transistors. When both i/ps A and B are zero volts, both transistors are turned off. Hence output point goes to +VCC so that o/p is logic ‘1’. If either or both i/ps terminals are at +VCC that are high or logic ‘1’ then both transistors would be fully turned on(saturation). The output goes logically zero. It is seen that the output is at logic 1 only when both inputs are at logic 0. The NOR logic function is as shown in the figure. The RTL family has the following characteristics 1. Relatively low speed. 2. Low fan out ‘6’ and a fan in of ‘4’. 3. Poor noise immunity. 4. Expensive since resistors are required to be fabricated. 5. Cannot operate at speeds above 4mHz. Diode-Transistor logic (DTL): It is a saturated circuit because transistors operated between cutoff and saturation. It was the next family to be introduced after RTL. It consist diodes, resistors and transistors. The basic gate of this family performs NAND function as shown in the figure. The circuit basically consists of a diode AND gate followed by a transistor inverter leads to a NAND gate. Operation: When both D1 and D2 have positive voltage applied to them (logic 1), neither conducts and Q is turned ON by the current provided by VCC through R1. Since Q becomes saturated, point C brought to ‘0’ volts (logic 0). Hence the output goes to logic ‘0’. If either or both input are at zero volts (logic 0), the associated diode will conduct output point to ground i.e., zero volts. Since there is no base voltage for Q, It will be cutoff, there by output is +VCC i.e., logic 1. It is seen that output is low (logic 0) only when all the inputs are high. That is the condition for a NAND gate. Characteristics: 1. Relatively lower speed. 2. Comparatively better noise immunity. 3. Transmission delay of 30 nano seconds. 4. A fan in of ‘8’. 5. A fan out of ‘5’. Transistor-Transistor Logic (TTL): The basic TTL circuit is never used in practice. Its modified version with an added output stage is in common use. This extra output is often known as TOT empole stage because the three output components Q3, Q4 and D are stacked one on top of the other in the manner of a TOT empole.

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When input is high: In this case, the two input terminals have positive voltage and the emitter base junctions is reverse biased because of which there is no emitter current hence Q1 is off. Since collector base junction of Q1 is forward biased, base current of Q2 flows from +VCC through R1 and hence Q2 is forward on. As a result, potential of point N falls so much that Q3 is turned off at the same time Q4 is turned on by the voltage drop across R3. Now when Q4 is on it’s collector potential (output) is nearly that of it’s emitter. Hence the output is low that is logic ‘0’. In short, when the inputs are logic 1, Q1 is off, Q2 is on, Q3 is off and Q4 is on because of which the output becomes logic 0. When input is low: If any of the two inputs or both are low, Q1 turns on and potential of its collector falls hence Q2 is turned off (ground). So that Q4 is also turned off since N is at VCC, it turns Q3 on the potential of output is VCC minus drop in R4, Q3 and D. Thus, the drops do not amount too much result output at logic ‘1’. It may be noted that when even numbered transistors are on, the odd numbered ones are off and vice versa. The function of diode D in circuit is to prevent both Q3 and Q4 being turned on simultaneously or at the same time. They would offer low impedance to the supply which will draw excessive current and produce large noise spikes in the output. It may also be noted that the addition of a pair of TOT empole transistors increase the operating speed and output current capability of this circuit. Note: any one of circuit only….values are not necessary. Identify R1, R2, R3 and R4…. Characteristics: The standard TTL family has… 1. Greater speed than DTL. 2. Less noise immunity. 3. Average propagation delay per gate of 9 nano seconds. 4. Average power dissipation of 10mW. 5. A Fanout of 10 meaning one output can drive to other TTL inputs. 6. A Fan in of 6. Emitter Coupled logic (ECL): It has the highest speed of any of the currently available logic circuits. It is primarily due to the fact that transistors never operate fully saturated or cutoff that’s why ECL is known as Non saturated logic. It has propagation delay time varying from 0.75 nano second to 2 nano second. However power dissipation is increased since one transistor always in the active region. Page 10 of 12

Another feature of ECL is that it provides two output which are always compliment of each other as shown in the figure. It is so because circuit operation is based on the differential operator. This family is particularly suited to monolithic fabrication techniques. Operation: The basic circuit is shown in figure. It is combined OR/NOR circuit and is operated from a VEE = −5.2 power supply. A built in constant current source provides current to the emitter. Logic ‘1’ is represented by -0.9V (less –Ve) and logic 0 by -1.75V (more –Ve) i.e., it is a positive logic. When both i/ps are at logic 0 i.e., − . : In this case, both Q1 and Q2 in OFF mode and Q3 gets ON. As a result, potential at collector of Q1 ad Q2 get high and potential at Q3 get low. So, the output1 becomes high and output2 becomes low. When either i/ps are at logic ‘1’i.e., − . : In this case, either or both Q1 and Q2 in ON mode and Q3 gets OFF. As a result, potential at collector of Q1 ad Q2 get low and potential at Q3 get high. So, the output1 becomes low and output2 becomes high. Characteristics: 1. Propagation delay time for gate of 1nano second meaning that extremely fast speed. 2. Power dissipation of 30mW. 3. Fan out of 50. 4. Fan in of 5. 5. Noise immunity of 0.4V. Complementary metal oxide semi conductor (CMOS): CMOS logic circuit use Eonly MOSFET with both P-MOSFET and N-MOSFET in the same circuits. It gives the advantages of drastic decrease in power dissipation (12mW per gate) and increase in the speed of operation impact. It has the lowest power dissipation among different logic families. It has a very high packing density i.e., the larger number of circuits can be placed and a single chip. As a result, it is extensively used in VLSI circuits such as on chip compters and memory system. The figure shows a CMOS NOR circuit which has two N-channel MOSFETs Q1 and Q2 and two P-channel MOSFETs Q3 and Q4. The two inputs A and B switch between +VDD (logic 1) and ground (logic 0). Operation: Let A=B=logic 1 i.e., have positive voltage. In that case, Q1 and Q2 are ON (closed switches) but Q3 and Q4 are off and acts as open switches as shown in the figure. Hence o/p is logic 0. If either A or B in logic 1, then the associated N channel MOSFET (Q1 or Q2) turned on but the associated P-channel MOSFET (Q3 and Q4) is turned off. Since either Q3 and Q4 will be off, output would be at logic 0. When both A and B are at logic 0, Q3 and Q4 would be ON but Q1 and Q2 would be OFF. Hence o/p would be at logic 1. The above logic represents a NOR function as shown in the truth table. It would be observed from the figure that in each combination of A and B. There is at least one open switch between +VDD and ground. Characteristics: 1. low power consumption. Page 11 of 12

2. 3. 4. 5. 6. 7.

high noise immunity. A wide variety of CMOS logic devices in the 4000 series are available. VDD ranges from +3 V to +16 V The input impedance, in either state, of CMOS gates is typically 1012 Ω. The output impedance is 1kΩ. The fan-out of CMOS devices is usually greater than 50.

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Unit V: 7. Sequential digital circuits: Flip-flops, RS, Clocked SR, JK, D, T, Master-Slave, 8. Flip- flop, Conversion of Flip flops. Sequential digital circuits: A combinational logic circuits with memory elements are called Sequential digital circuits. The output state of a “sequential logic circuit” is a function of the following three states, the “present input”, the “past input” and/or the “past output”. Sequential Logic circuits remember these conditions and stay fixed in their current state until the next clock signal changes one of the states, giving sequential logic circuits “Memory”. Sequential logic circuits are generally termed as two state or Bistable devices which can have their output or outputs set in one of two basic states, a logic level “1” or a logic level “0” and will remain “latched” (hence the name latch) indefinitely in this current state or condition until some other input trigger pulse or signal is applied which will cause the bistable to change its state once again. The word “Sequential” means that things happen in a “sequence”, one after another and in Sequential Logic circuits, the actual clock signal determines when things will happen next. Simple sequential logic circuits can be constructed from standard Bistable circuits such as: Flip-flops, Latches and Counters and which themselves can be made by simply connecting together universal NAND Gates and/or NOR Gates in a particular combinational way to produce the required sequential circuit. Types of sequential circuits: There are two types of sequential circuit, synchronous and asynchronous. Synchronous types use pulsed or level inputs and a clock input to drive the circuit. An asynchronous circuit, or self-timed circuit, is a sequential digital logic circuit which is not governed by a clock circuit. Flip-Flops: Flip flop is a sequential circuit which generally samples its inputs and changes its outputs only at particular instants of time and not continuously. A flip-flop is a bistable circuit made up of logic gates. The most important use of this property is that a flip-flop can “store” binary information 0 or 1. It is also called as bistable multivibrator. Different types of Flip flops are….. 1. RS Flip flop 2. Clocked RS Flip flop 3. J-K flip flop 4. Master-Slave flip flop 5. T flip flop 6. D flip flop R–S Flip-Flop. The RS (Reset-Set) flip-flop is one of the simplest sequential circuits and consists of two gates connected as shown in Fig. Notice that the output of each gate is connected to one of the inputs of the other gate, giving a form of positive feedback or ‘cross-coupling’. Page 1 of 20

The circuit has two active low inputs marked S and R, as well as two outputs, Q and . Table shows what happens to the Q and outputs when logic 0 is applied to either the S or R inputs. Working: The working of the circuit depends upon the behavior of the gates. The output of the NOR gate is low if atleast one i/p is 1 and output is high only when all the inputs are low. They are four possible combinations are available for this flip flop. Case 1: When both inputs are low i.e., R=0, S=0. In this case, the flip flop remains in the same state i.e., for S=0, R=0. The Q remains unchanged. Case 2: When R=0, S=1. In this case, = 1, = 0. Thus 1 at the S input is said to SET the flip flop and it switches to the stable state where = 1, = 0. Case 3: When R=1, S=0. In this case, = 0, = 1 Thus, 1 at the R input and is said to RESET the flip flop and switches to the stable state where = 0, = 1. Case 4: When both inputs are high i.e., R=1, S=1. In this case, = 0, = 0. The last input condition is forbidden because it forces the outputs of both NOR gates to the low state. i.e., = = 0 1 is not allowed. Fig. shows a timing diagram describing the action of the basic RS Latch for logic changes at R and S. At time (a) S goes high and sets Q, which remains high until time (b) when S is low and R goes high, resetting Q. During period (c) both S and R are high causing the non-allowed state where both outputs are high. After period (c) Q remains high until time (d) when R goes high, resetting Q. Period (e) is another non-allowed period, at the end of which both inputs go low causing an indeterminate output condition in period (f). Clocked SR Flip-flop: In the clocked RS flip flop the appropriate levels applied to their inputs are blocked till the receipt of a pulse from another source called clock. The flip flop changes state only when clock pulse is applied depending upon the inputs. The basic circuit is as Page 2 of 20

shown in the figure. This circuit is formed by adding AND gates at inputs to the RS flip flop. In addition to control inputs Set and Reset, there is a clock input also. 1) When the clock is Low i.e ‘0’, the outputs of two input and gates will be ‘0’ for any input of S & R. The 0-0 input to the RS flip flop with NOR gates results in “NO CHANGE STATE” at the output. This ensures for the clock zero or low condition the output will remains in the same state. 2) When the clock is high the input AND gates acts as a input follower i.e. when the other input is 0 output will be zero or if the input is ‘1’ output will be ‘1’. In this case, the RS flip flop acts according to the input S & R and changes its state according to the input. Delay flip flop: D flip flop also called as delay flip flop where it can be used to introduce a delay in the digital circuit by changing the propagation delay of the flip flop. Here the input data bit at D will reflects at the output after a certain propagation delay. Figure shows the Clocked D Flip flop with additional two AND gates with two inputs are clock and D. When the clock is low it disables the two AND gates and prevents the Flip flop from changing the states. When a clock is high, it is important as the flip flop output state depends on the input D bit. A high D sets the flip flop output high and a low D resets it. Applications:  It is used as a buffer to store the intermediate data  It is also used to introduce the delay in the circuits. JK Flip flop: J and K in the JK flip flop means Jack and Kilby who invented this flip flop combination. This toggling condition is mostly used in the counters. Figure shows the circuit diagram of JK flip flop in which two AND gates are placed input to the SR flip flop. One input of AND gate is J or K and second input is the feedback parameter of output, in a summarized way the inputs of first AND gate is J & (Q bar) and the second gate inputs are R & Q. A clock signal is provide to the both AND gates for enabling or disabling the flip flop operation. The following points shows the operating conditions of JK flip flop: 1. When J & K are low, (i.e. 0), the two AND gates will disable irrespective of the & and two inputs to S & R flip flop will be zero which gives a no state condition. This condition is called latched condition as the flip flop retains its last value.

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2. When J is Low and K is High, the upper or first AND gate disables, therefore there is no way to set the output of flip flop only the flip flop will be reset. Once flip flop resets Q becomes 0 and lower AND also disables and leads to no change condition of flip flop even the clock pulse is high. 3. When J is High & K is Low, the lower AND gate gets disables which disables the resetting condition of flip flop. So the flip flop can only be set. After this again the two AND gates are disabled because of =0 in this condition and it leads to no change condition. 4. When J & K is High, both AND gates can be enabled which is possible to SET or RESETS the flip flop. It is very important condition as it toggles the flip flop output states. Note: Toggle means, that every time the J and K inputs are in 1. When a rising clock pulse appears, will change both outputs Q and . If Q was 1, then with the clock pulse will change to 0, and be allways the opposite to Q.

will

T-Flip flop: The name T flipflop is termed from the nature of toggling operation. The major applications of T flipflop are counters and control circuits. T flip flop is modified form of JK flip-flop making it to operate in toggling region. Whenever the clock signal is LOW, the input is never going to affect the output state. The clock has to be high for the inputs to get active. Thus, T flip-flop is a controlled Bistable latch where the clock signal is the control signal. Thus, the output has two stable states based on the inputs which have been discussed below. Case 1: When clock is low, T-Flip flop is disabled. Case 2: When T = 0, and clock is high then Qn+1 = Qn. Master-Slave Flip-Flop: The Master-Slave Flip-Flop is basically a combination of two JK flip-flops connected together in a series configuration. Out of these, one acts as the “master” and the other as a “slave”. The output from the master flip flop is connected to the two inputs of the slave flip flop whose output is fed back to inputs of the master flip flop. In addition to these two flip-flops, the circuit also includes an inverter. The inverter is connected to clock pulse in such a way that the inverted clock pulse is given to the slave flip-flop. Working: Case 1: When J =0, K=0; The clock pulses have no effect. Thus, Q retains at it’s last state i.e., If Master is at high state, then slave will be at high stage. If Master is at low state, then slave will be at low state. Page 4 of 20

Case 2: When J=0, K=1; The master RESETs on the positive clock edge. The high of the master goes to the K input of the slave. Therefore, when the negative clock edge hits the slave is forced to RESET. Case 3: When J=1, K=0; The master SETs on the positive clock edge. The high Q output of the master drives the J input of the slave. So, when the negative clock edge hits, the slave SETs. Case 4: When J=1, K=1; If the master’s J and K inputs are high, it Toggles on the positive clock edge and the slave then Toggle on the negative clock edge. In all cases, regardless of what the Master does, the slave copies. if the master SETs, the Slave SETs. On the other words If the master RESETs, the slave RESETs. i.e., Slave follows the Master. Converters (Flip flops): Conversion of flip-flops causes one type of flip-flop to behave like another type of flip-flop. In order to make one flip-flop mimic the behavior of another certain additional circuitry and/or connections become necessary. Conversion of JK Flip-Flop to SR Flip-Flop: Step 1: Write the Truth Table of the Desired Flip-Flop Here SR flip-flop is to be designed using JK flip-flop. Thus we need to write the truth table for SR flip-flop.

Step 2: Obtain the Excitation Table for the given Flip-Flop from its Truth Table Excitation tables provide the details regarding the inputs which must be provided to the flipflop to obtain a definite next state (Qn+1) from the known current state (Qn).

From the truth table of JK flip-flop we can see that Qn+1 will become 0 from Qn = 0 for both (i) J = K = 0 and (ii) J = 0 and K =1. This means that to obtain the next state, Qn+1 as 0 from the current state Qn = 0, J must be made zero while K can be either 0 or 1. This is indicated Page 5 of 20

as 'X' (don't care condition). Similarly to obtain the next state as 1 from the current state 0, one has to have J equal to 1 while K can be either 0 or 1. This leads to the second row of excitation table to be filled with values Qn = 0, Qn+1 = 1, J = 1 and K = X. On the same grounds, entire excitation table needs to be filled. Step 3: Append the Excitation Table of the given Flip-Flop to the Truth Table of the Desired Flip-Flop Appropriately to obtain Conversion Table Here the conversion table is obtained by filling-up the values of the J and K inputs for the given Qn and Qn+1, by referring to the excitation table.

Step 4: Simplify the Expressions for the Inputs of the given Flip-Flop In this case, we need to arrive at the logical expressions for the inputs J and K in terms of S, R and Qn using suitable simplification technique like K-map.

Step 5: Design the Necessary Circuit and make the Connections accordingly Here neither additional circuit nor new connections are necessary.

Conversion of JK Flip Flop to D Flip Flop: Step 1: Write the Truth Table of the Desired Flip-Flop Here D flip-flop is to be designed using JK flip-flop. Thus we need to write the truth table for D flip-flop.

Step 2: Obtain the Excitation Table for the given Flip-Flop from its Truth Table Excitation tables provide the details regarding the inputs which must be provided to the flipflop to obtain a definite next state (Qn+1) from the known current state (Qn).

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From the truth table of JK flip-flop we can see that Qn+1 will become 0 from Qn = 0 for both (i) J = K = 0 and (ii) J = 0 and K =1. This means that to obtain the next state, Qn+1 as 0 from the current state Qn = 0, J must be made zero while K can be either 0 or 1. This is indicated as 'X' (don't care condition). Similarly to obtain the next state as 1 from the current state 0, one has to have J equal to 1 while K can be either 0 or 1. This leads to the second row of excitation table to be filled with values Qn = 0, Qn+1 = 1, J = 1 and K = X. On the same grounds, entire excitation table needs to be filled. Step 3: Append the Excitation Table of the given Flip-Flop to the Truth Table of the Desired Flip-Flop Appropriately to obtain Conversion Table Here the conversion table is obtained by filling-up the values of the J and K inputs for the given Qn and Qn+1, by referring to the excitation table.

Step 4: Simplify the Expressions for the Inputs of the given Flip-Flop In this case, we need to arrive at the logical expressions for the inputs J and K in terms of D and Qn using suitable simplification technique like K-map.

Step 5: Design the Necessary Circuit and make the Connections accordingly Here we need to connect NOT gate through J to K.

Conversion of JK Flip Flop to T Flip Flop: Step 1: Write the Truth Table of the Desired Flip-Flop Here T flip-flop is to be designed using JK flip-flop. Thus we need to write the truth table for T flip-flop.

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Step 2: Obtain the Excitation Table for the given Flip-Flop from its Truth Table Excitation tables provide the details regarding the inputs which must be provided to the flipflop to obtain a definite next state (Qn+1) from the known current state (Qn).

From the truth table of JK flip-flop we can see that Qn+1 will become 0 from Qn = 0 for both (i) J = K = 0 and (ii) J = 0 and K =1. This means that to obtain the next state, Qn+1 as 0 from the current state Qn = 0, J must be made zero while K can be either 0 or 1. This is indicated as 'X' (don't care condition). Similarly to obtain the next state as 1 from the current state 0, one has to have J equal to 1 while K can be either 0 or 1. This leads to the second row of excitation table to be filled with values Qn = 0, Qn+1 = 1, J = 1 and K = X. On the same grounds, entire excitation table needs to be filled. Step 3: Append the Excitation Table of the given Flip-Flop to the Truth Table of the Desired Flip-Flop Appropriately to obtain Conversion Table Here the conversion table is obtained by filling-up the values of the J and K inputs for the given Qn and Qn+1, by referring to the excitation table.

Step 4: Simplify the Expressions for the Inputs of the given Flip-Flop In this case, we need to arrive at the logical expressions for the inputs J and K in terms of T and Qn using suitable simplification technique like K-map.

Step 5: Design the Necessary Circuit and make the Connections accordingly Here we need to connect J to K. Page 8 of 20

Conversion of SR Flip Flop to JK Flip Flop: Step 1: Write the Truth Table of the Desired Flip-Flop Here JK flip-flop is to be designed using SR flip-flop. Thus we need to write the truth table for JK flip-flop.

Step 2: Obtain the Excitation Table for the given Flip-Flop from its Truth Table Excitation tables provide the details regarding the inputs which must be provided to the flipflop to obtain a definite next state (Qn+1) from the known current state (Qn).

From the truth table of SR flip-flop we can see that Qn+1 will become 0 from Qn = 0 for both (i) S = R = 0 and (ii) S = 0 and R =1. This means that to obtain the next state, Qn+1 as 0 from the current state Qn = 0, S must be made zero while R can be either 0 or 1. This is indicated as 'X' (don't care condition). Similarly to obtain the next state as 1 from the current state 0, one has to have S equal to 1 R equal to 0. This leads to the second row of excitation table to be filled with values Qn = 0, Qn+1 = 1, S = 1 and R = 0. On the same grounds, entire excitation table needs to be filled. Step 3: Append the Excitation Table of the given Flip-Flop to the Truth Table of the Desired Flip-Flop Appropriately to obtain Conversion Table Here the conversion table is obtained by filling-up the values of the S and R inputs for the given Qn and Qn+1, by referring to the excitation table.

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Step 4: Simplify the Expressions for the Inputs of the given Flip-Flop In this case, we need to arrive at the logical expressions for the inputs S and R in terms of J, K and Qn using suitable simplification technique like K-map.

Step 5: Design the Necessary Circuit and make the Connections accordingly Here we need to connect J to K.

Conversion of SR Flip Flop to D Flip Flop: Step 1: Write the Truth Table of the Desired Flip-Flop Here D flip-flop is to be designed using SR flip-flop. Thus we need to write the truth table for D flip-flop.

Step 2: Obtain the Excitation Table for the given Flip-Flop from its Truth Table Excitation tables provide the details regarding the inputs which must be provided to the flipflop to obtain a definite next state (Qn+1) from the known current state (Qn).

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From the truth table of SR flip-flop we can see that Qn+1 will become 0 from Qn = 0 for both (i) S = R = 0 and (ii) S = 0 and R =1. This means that to obtain the next state, Qn+1 as 0 from the current state Qn = 0, S must be made zero while R can be either 0 or 1. This is indicated as 'X' (don't care condition). Similarly to obtain the next state as 1 from the current state 0, one has to have S equal to 1 R equal to 0. This leads to the second row of excitation table to be filled with values Qn = 0, Qn+1 = 1, S = 1 and R = 0. On the same grounds, entire excitation table needs to be filled. Step 3: Append the Excitation Table of the given Flip-Flop to the Truth Table of the Desired Flip-Flop Appropriately to obtain Conversion Table Here the conversion table is obtained by filling-up the values of the S and R inputs for the given Qn and Qn+1, by referring to the excitation table.

Step 4: Simplify the Expressions for the Inputs of the given Flip-Flop In this case, we need to arrive at the logical expressions for the inputs S and R in terms of D and Qn using suitable simplification technique like K-map.

Step 5: Design the Necessary Circuit and make the Connections accordingly Here we need to connect NOT gate through S to R.

Conversion of SR Flip Flop to T Flip Flop: Step 1: Write the Truth Table of the Desired Flip-Flop Here T flip-flop is to be designed using SR flip-flop. Thus we need to write the truth table for T flip-flop. Page 11 of 20

Step 2: Obtain the Excitation Table for the given Flip-Flop from its Truth Table Excitation tables provide the details regarding the inputs which must be provided to the flipflop to obtain a definite next state (Qn+1) from the known current state (Qn).

From the truth table of SR flip-flop we can see that Qn+1 will become 0 from Qn = 0 for both (i) S = R = 0 and (ii) S = 0 and R =1. This means that to obtain the next state, Qn+1 as 0 from the current state Qn = 0, S must be made zero while R can be either 0 or 1. This is indicated as 'X' (don't care condition). Similarly to obtain the next state as 1 from the current state 0, one has to have S equal to 1 R equal to 0. This leads to the second row of excitation table to be filled with values Qn = 0, Qn+1 = 1, S = 1 and R = 0. On the same grounds, entire excitation table needs to be filled. Step 3: Append the Excitation Table of the given Flip-Flop to the Truth Table of the Desired Flip-Flop Appropriately to obtain Conversion Table Here the conversion table is obtained by filling-up the values of the S and R inputs for the given Qn and Qn+1, by referring to the excitation table.

Step 4: Simplify the Expressions for the Inputs of the given Flip-Flop In this case, we need to arrive at the logical expressions for the inputs S and R in terms of T and Qn using suitable simplification technique like K-map.

Step 5: Design the Necessary Circuit and make the Connections accordingly Here we need to connect AND gates in front of S to R and joint the inputs as shown.

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Conversion of D Flip Flop to JK Flip Flop: Step 1: Write the Truth Table of the Desired Flip-Flop Here JK flip-flop is to be designed using D flip-flop. Thus we need to write the truth table for JK flip-flop.

Step 2: Obtain the Excitation Table for the given Flip-Flop from its Truth Table Excitation tables provide the details regarding the inputs which must be provided to the flipflop to obtain a definite next state (Qn+1) from the known current state (Qn).

From the truth table of D flip-flop we can see that Qn+1 will become 0 from Qn = 0 for D=0. Similarly to obtain the next state as 1 from the current state 0, from D=1. On the same grounds, entire excitation table needs to be filled. Step 3: Append the Excitation Table of the given Flip-Flop to the Truth Table of the Desired Flip-Flop Appropriately to obtain Conversion Table Here the conversion table is obtained by filling-up the values of the D inputs for the given Qn and Qn+1, by referring to the excitation table.

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Step 4: Simplify the Expressions for the Inputs of the given Flip-Flop In this case, we need to arrive at the logical expressions for the inputs D in terms of J, K and Qn using suitable simplification technique like K-map.

Step 5: Design the Necessary Circuit and make the Connections accordingly Here we need to connect two AND gates, OR gate in front of D and NOT gate at K input as shown.

Conversion of D Flip Flop to SR Flip Flop: Step 1: Write the Truth Table of the Desired Flip-Flop Here SR flip-flop is to be designed using D flip-flop. Thus we need to write the truth table for SR flip-flop.

Step 2: Obtain the Excitation Table for the given Flip-Flop from its Truth Table Excitation tables provide the details regarding the inputs which must be provided to the flipflop to obtain a definite next state (Qn+1) from the known current state (Qn).

From the truth table of D flip-flop we can see that Qn+1 will become 0 from Qn = 0 for D=0. Similarly to obtain the next state as 1 from the current state 0, from D=1. On the same grounds, entire excitation table needs to be filled. Step 3: Append the Excitation Table of the given Flip-Flop to the Truth Table of the Desired Flip-Flop Page 14 of 20

Appropriately to obtain Conversion Table Here the conversion table is obtained by filling-up the values of the D inputs for the given Qn and Qn+1, by referring to the excitation table.

Step 4: Simplify the Expressions for the Inputs of the given Flip-Flop In this case, we need to arrive at the logical expressions for the inputs D in terms of J, K and Qn using suitable simplification technique like K-map.

Step 5: Design the Necessary Circuit and make the Connections accordingly Here we need to connect AND gates, OR gate in front of D and NOT gate at R input as shown.

Conversion of D Flip Flop to T Flip Flop: Step 1: Write the Truth Table of the Desired Flip-Flop Here T flip-flop is to be designed using D flip-flop. Thus we need to write the truth table for T flip-flop.

Step 2: Obtain the Excitation Table for the given Flip-Flop from its Truth Table Excitation tables provide the details regarding the inputs which must be provided to the flipflop to obtain a definite next state (Qn+1) from the known current state (Qn).

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From the truth table of D flip-flop we can see that Qn+1 will become 0 from Qn = 0 for D=0. Similarly to obtain the next state as 1 from the current state 0, from D=1. On the same grounds, entire excitation table needs to be filled. Step 3: Append the Excitation Table of the given Flip-Flop to the Truth Table of the Desired Flip-Flop Appropriately to obtain Conversion Table Here the conversion table is obtained by filling-up the values of the D inputs for the given Qn and Qn+1, by referring to the excitation table.

Step 4: Simplify the Expressions for the Inputs of the given Flip-Flop In this case, we need to arrive at the logical expressions for the inputs D in terms of T and Qn using suitable simplification technique like K-map.

Step 5: Design the Necessary Circuit and make the Connections accordingly Here we need to connect X-OR gate at input as shown.

Conversion of T Flip Flop to JK Flip Flop: Step 1: Write the Truth Table of the Desired Flip-Flop Here JK flip-flop is to be designed using T flip-flop. Thus we need to write the truth table for JK flip-flop.

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Step 2: Obtain the Excitation Table for the given Flip-Flop from its Truth Table Excitation tables provide the details regarding the inputs which must be provided to the flipflop to obtain a definite next state (Qn+1) from the known current state (Qn).

From the truth table of T flip-flop we can see that Qn+1 will become 0 from Qn = 0 for T=0. Similarly to obtain the next state as 1 from the current state 0, from T=1. On the same grounds, entire excitation table needs to be filled. Step 3: Append the Excitation Table of the given Flip-Flop to the Truth Table of the Desired Flip-Flop Appropriately to obtain Conversion Table Here the conversion table is obtained by filling-up the values of the T inputs for the given Qn and Qn+1, by referring to the excitation table.

Step 4: Simplify the Expressions for the Inputs of the given Flip-Flop In this case, we need to arrive at the logical expressions for the inputs T in terms of J, K and Qn using suitable simplification technique like K-map.

Step 5: Design the Necessary Circuit and make the Connections accordingly Here we need to connect two AND gates and OR gate at input as shown.

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Conversion of T Flip Flop to SR Flip Flop: Step 1: Write the Truth Table of the Desired Flip-Flop Here SR flip-flop is to be designed using T flip-flop. Thus we need to write the truth table for SR flip-flop.

Step 2: Obtain the Excitation Table for the given Flip-Flop from its Truth Table Excitation tables provide the details regarding the inputs which must be provided to the flipflop to obtain a definite next state (Qn+1) from the known current state (Qn).

From the truth table of T flip-flop we can see that Qn+1 will become 0 from Qn = 0 for T=0. Similarly to obtain the next state as 1 from the current state 0, from T=1. On the same grounds, entire excitation table needs to be filled. Step 3: Append the Excitation Table of the given Flip-Flop to the Truth Table of the Desired Flip-Flop Appropriately to obtain Conversion Table Here the conversion table is obtained by filling-up the values of the T inputs for the given Qn and Qn+1, by referring to the excitation table.

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Step 4: Simplify the Expressions for the Inputs of the given Flip-Flop In this case, we need to arrive at the logical expressions for the inputs T in terms of S, R and Qn using suitable simplification technique like K-map.

Step 5: Design the Necessary Circuit and make the Connections accordingly Here we need to connect two AND gates and OR gate at input as shown.

Conversion of T Flip Flop to D Flip Flop: Step 1: Write the Truth Table of the Desired Flip-Flop Here D flip-flop is to be designed using T flip-flop. Thus we need to write the truth table for D flip-flop.

Step 2: Obtain the Excitation Table for the given Flip-Flop from its Truth Table Excitation tables provide the details regarding the inputs which must be provided to the flipflop to obtain a definite next state (Qn+1) from the known current state (Qn).

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From the truth table of T flip-flop we can see that Qn+1 will become 0 from Qn = 0 for T=0. Similarly to obtain the next state as 1 from the current state 0, from T=1. On the same grounds, entire excitation table needs to be filled. Step 3: Append the Excitation Table of the given Flip-Flop to the Truth Table of the Desired Flip-Flop Appropriately to obtain Conversion Table Here the conversion table is obtained by filling-up the values of the T inputs for the given Qn and Qn+1, by referring to the excitation table.

Step 4: Simplify the Expressions for the Inputs of the given Flip-Flop In this case, we need to arrive at the logical expressions for the inputs T in terms of D and Qn using suitable simplification technique like K-map.

Step 5: Design the Necessary Circuit and make the Connections accordingly Here we need to connect X-OR gate at input as shown.

The End….Yours Chandar Rao, Lecturer in physics, Vignan Degree college, Vissanna pet.

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