A New Grounded Lamination Gate (glg) For Diminished Fringe Capacitance Effects In High-k Gate Dielectric Mosfets

IEEE Trans. on Electron Devices, Vol.53, pp.2578-2581, October 2006.

A New Grounded Lamination Gate (GLG) for Diminished Fringe Capacitance Effects in High-K Gate Dielectric MOSFETs M. Jagadesh Kumar1, Vivek Venkataraman and Sumeet Kumar Gupta Department of Electrical Engineering, Indian Institute of Technology, Delhi, Hauz Khas, New Delhi – 110 016, INDIA. Email: [email protected] Fax: 91-11-2658 1264

Abstract A grounded lamination gate (GLG) structure for high-K gate dielectric MOSFETs is proposed with grounded metal plates in the spacer oxide region. Two-dimensional device simulations performed on the new structure demonstrate a significant improvement with respect to the threshold voltage roll-off with increasing gate dielectric constant (due to parasitic internal fringe capacitance) keeping the effective oxide thickness same. A simple fabrication procedure for the grounded lamination gate MOSFET is also presented.

Index Terms: Silicon-on-Insulator (SOI), MOSFET, High-K gate dielectric, Internal fringe capacitance, Threshold voltage, simulation.

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Corresponding author

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1. Introduction In highly scaled down MOSFETs, parasitic capacitance becomes an appreciable part of the active device capacitance due to the fringing effect at the edges of the conductors affecting the power delay product and speed of the circuit [1]. Fringing field also affects important device parameters such as the threshold voltage. This is particularly true when we use high-K gate materials in SOI-MOSFETs [2], resulting in dielectric thicknesses comparable to the device gate length (keeping effective oxide thickness (EOT) and hence gate to channel capacitance (Cox) same). This leads to an undesirable increase in the fringing fields from the gate to the source/drain regions and will compromise the short-channel performance [3] such as a decrease in threshold voltage (Vth) with increasing gate dielectric permittivity( ε ox ) [4-9]. The purpose of this brief is to propose a modification in the high-K dielectric SOIMOSFET structure by introducing the Grounded Lamination Gate (GLG) in the spacer region to prevent the fringing field lines, emanating from the bottom of the gate electrode, from entering the source/drain regions. The dependence of threshold voltage on the gate dielectric permittivity is obtained for the high-K gate SOI MOSFETs with and without the GLG structure using the two-dimensional device simulator MEDICI [10]. Our results demonstrate that the application of grounded lamination gate (GLG) is very effective in controlling the threshold voltage roll-off even at high gate dielectric permittivities. The drain I-V characteristics are simulated to investigate the impact of the grounded lamination gate on the drain saturation current. A CMOS compatible fabrication procedure is also suggested.

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2. Proposed Device Structure Fig. 1(a) shows the schematic cross-sectional view of a conventional SOI MOSFET with high-K gate dielectric and Fig. 1(b) shows the proposed grounded lamination gate (GLG) SOI MOSFET structure with metal plates of thickness tp in the spacer region at a distance of tm from the gate on either side. These metal plates are grounded so that the fringing field lines terminate on these plates rather than the source/drain regions. The extent to which these plates will cover the high K gate dielectric is decided by the silicon nitride thickness (tm) that seperates the metal plate from the gate as shown in Fig. 1(b). We have first optimized the distance tm so that the grounded lamination is neither too close nor too far from the gate. It is observed that if the plates are too close to the gate (i.e tm is low) , the gate-to-channel capacitance(Cox) itself gets reduced due to diversion of electric field lines from the gate electrode to the grounded metal plates which are required for causing inversion in the channel region. This results in a very high threshold voltage and very low transconductance. On the other hand, if the plates are too close to the source/drain electrodes (i.e. tm is large), the external parasitic capacitance becomes very high resulting in a huge electric field in the spacer region near the metal plates. Also the effectiveness of the metal plates to mitigate the effect of parastic internal fringe capacitance is reduced. For a gate length (Lg) of 50 nm and spacer width (tspacer) of 25 nm, the optimum distance of the plates from the gate (tm) is found to be about 10 nm. The thickness of the metal plates (tp) is kept small in comparison to the spacer width ( for tspacer = 25 nm, tp = 2-3 nm). It is also important to point out that the distance tm between metal plates and the polygate cannot be made too small to minimize any possible tunnel currents between the polygate and the grounded metal plate. The other parameter that one needs to examine is the depth to which the high-K gate dielectric needs to be covered by the grounded metal plates. This is decided by the thickness of the silicon

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nitride which seperates the metal plate from the gate. As discussed above, for an optimum spacing of 10 nm between the metal plate and the gate, the gate dielectric will be uncovered by 10 nm from the bottom (i.e. Si/SiO2 interface). For a dielectric permittivity of 60 and with an equivalent oxide thickness of 2 nm, the physical thickness of the high-K gate dielectric is approximately 30 nm. Therefore, with a metal seperation of 10 nm from the gate, two-thirds of the gate dielectric will be covered by the grounded metal plates and as we will show in the following section, this is sufficient to effectively control the fringing field effects on the threhsold voltage of the MOSFET. The device parameters used in our simulation are given in Table 1.

3. Results Fig. 2 shows the variation of surface potential along the channel for the high-K SOI MOSFET with and without GLG. It can be seen that the surface potential is lower for the structure with GLG. This indicates that the effect of the internal fringe capacitance is getting mitigated resulting in a later onset of inversion and hence a higher threshold voltage. The threshold voltage is then extracted from 2-D simulation using the commonly used maximum transconductance method. Fig. 3 shows the variation of threshold voltage as a function of gate dielectric permittivity with and without GLG. It is evident from the figure that the drop in threshold voltage for the structure without metal plates is as high as about 40 mV (~20% of the threshold voltage value for ε SiO2 = 3.9) as ε ox increases from 3.9 to 80. However, for the proposed structure there is a minimal variation in threshold voltage. For tm = 10 nm, the threshold voltage is almost constant for the entire range of ε ox with a maximum deviation of as little as 5 mV ( ~ 2.5 %).

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Fig. 4 shows the drain I-V characteristics of the high-K SOI-MOSFET with and without GLG. The drain saturation characteristic is not affected drastically by the grounded metal plates, and is similar to that of the MOSFET without GLG except for a slight negative offset due to a larger threshold voltage. The drain saturation current of GLG MOSFET also suggests that there are no possible tunnel currents between the polygate and the grounded metal plate.

4. Proposed GLG MOSFET Device Fabrication The GLG MOSFET can be fabricated using standard CMOS steps as shown by the top and side views of the fabrication steps in Fig. 5. We begin with the MOS structure as shown in Fig. 5(a) with the poly gate over the gate dielectric with appropriate equivalent oxide thickness (EOT). A thin (~10 nm) Si3N4 layer is deposited using CVD (Chemical Vapour Deposition) or sputtering (Fig. 5(b)). This is followed by the CVD/sputtering of a very thin layer of TiN (~ 2 nm) which will function as the grounded lamination for the gate (as can be seen in Fig. 5(c)). A low temperature oxide (LTO) is next deposited (Fig. 5(d)) and anisotropically etched using plasma etching/reactive ion etching (RIE) resulting in a sidewall oxide on both sides of the gate as shown in Fig. 5(e). A window is now opened using a mask to the polysilicon gate as shown in top view of Fig. 5 (f). This is the only additional contact window mask that is required to fabricate the GLG structure. A thick dielectric layer (TEOS) is then deposited all over and is planarized using CMP as shown in Fig. 5(g). In order to ground the metal plates, a contact window for the same is opened in the TEOS oxide, using the same mask used for the source/drain contacts. After metallization and pattering, the final GLG MOSFET structure can be realized as shown in Fig. 5(h).

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5. Conclusions Reducing the fringing capacitance effects is crucial in the design of high speed small geometry high-K gate dielectric SOI-MOSFETs. In this brief, using two-dimensional simulation, we have presented a grounded lamination gate (GLG) SOI MOSFET structure to effectively extenuate the threshold voltage roll-off with increase in gate dielectric constant (and thus the physical gate dielectric thickness) due to parasitic internal fringe capacitance. A simple fabrication procedure is also suggested.

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References 1. B. H. Cheng, M. Cao, V. R. Rao, A. Inani, P. V. Voorde, W. M. Greene, J. M. C. Stork, Z. P. Yu, P. M. Zeitzoff, and J. C. S. Woo, “The Impact of High- Gate Dielectrics and Metal Gate Electrodes on Sub-100 nm MOSFETs”, IEEE Trans. on Electron Devices, Vol. 46, No. 7, pp. 1537-1544, July 1999. 2. J. Robertson, “High dielectric constant oxides,” Eur. Phys. J. Appl. Phys., Vol. 28, pp.265-291, 2004. 3. D. N. Pattanayak, J. G. Poksheva, R. W. Downing and L. A. Akers, “Fringing field effect in MOS Devices,” IEEE Trans. on Electron Devices, Vol.5, pp.127-131, March 1982. 4. N. R. Mohapatra, M. P. Desai, S. G. Narendra, and V. R. Rao, “The Effect of High-K Gate Dielectrics on Deep Submicrometer CMOS Device and Circuit Performance,” IEEE Trans. on Electron Devices, vol. 49, pp. 826-831, May 2002. 5. M. J. Kumar, S. K. Gupta and V. Venkataraman, "Compact Modeling of Parasitic Internal Fringe Capacitance Effects on the Threshold Voltage of High-K Gate Dielectric Nanoscale SOI MOSFETs," IEEE Trans. on Electron Devices, Vol.53, pp.706-711, April 2006. 6. S. W. Lee, “A proposed method for determining a MOSFET gate electrode's bottom dimension and the on-state fringing capacitance,” IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, Vol.12, pp.96-101, Jan. 1993. 7. J.-C. Guo, C.-Y. Lu, C. C. –H. Hsu, P.-S. Lin and S. S. –S. Chung, “Performance and reliability evaluation of high dielectric LDD spacer on deep sub-micrometer LDD MOSFET,” IEEE Trans. on Electron Devices, Vol.41, pp.1239 – 1248, July 1994. 8. T. Ernst and S. Cristoloveanu, “Buried oxide fringing capacitance: a new physical model and its implication on SOI device scaling and architecture,” Proc. IEEE International SOI Conference, 1999, pp.38 – 39. 9. C. C. McAndrew, G. Zaneski, P. A. Layman, and S. G. Ayyar, “Accurate characterization of MOSFET overlap/fringing capacitance for circuit design,” International Conference on Microelectronic Test Structures, 1994, pp.15 – 20. 10. MEDICI 4.0, Technology Modeling Associates, Inc., Palo Alto, CA, 1997.

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Table 1: Simulation Parameters Parameter Value 20 Source/Drain doping 2x10 cm-3 Channel doping 8.5x1017 cm-3 Gate Length(Lg) 50 nm Distance between metal plates and gate (tm) 10 nm Thickness of metal plate(tp) 2 nm Effective Oxide Thickness (EOT)* 2.0 nm Work Function of gate material 4.35 V (n+ poly) Silicon film thickness 25 nm Spacer oxide thickness (tspacer) 25 nm BOX thickness 100 nm Substrate Thickness 250 nm Gate electrode thickness 50 nm Source/drain – Gate overlap 5 nm (* Physical oxide thickness is calculated by multiplying EOT by ε ox ε SiO2 )

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Figure Captions

Figure 1. Figure 2. Figure 3.

Cross-sectional view of a high-K gate MOSFET (a) without GLG and (b) with GLG. Surface Potential variation along the channel with and without GLG. (VGS = 0.02 V, VDS = 0.05 V). Threshold voltage variation with gate dielectric constant with and without GLG.

Figure 4.

Current voltage characteristics in high-K gate MOSFET with GLG and without GLG.

Figure 5.

Proposed fabrication steps for the GLG MOSFET showing top and side views.

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tspacer

Poly

Field Oxide

Field Oxide

High K Oxide tOX Lg

N+ Source

P Silicon

N+ Drain

Buried Oxide

Substrate

Lamination Metal Thickness = tp

Silicon Nitride Thickness = tm

Poly

Field Oxide

Field Oxide High K Oxide

N+ Source

P Silicon

N+ Drain

Buried Oxide

Substrate

Fig. 1 10

Surface potential (V)

0.55 With GLG 0.50

Without GLG

0.45

εOX = 60

0.40 0

30 10 20 40 50 Distance along channel (nm)

Fig. 2

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Threshold voltage (V)

0.23 With GLG Without GLG 0.21

0.19

0.17 0

20 40 60 Fig.dielectric 3 Gate permittivity

80

Fig. 3

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Drain current (A/μm)

1.2

×10-3 VGS = 0.75 V

1.0

εOX = 60

0.8 0.6 0.4

With GLG

0.2 0.0

Without GLG 0

0.2

0.4 0.6 0.8 Drain Voltage (V)

1.0

Fig. 4

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Legends used in Fig. 5 Polysilicon

Diffusion Region

High-k Dielectric

LTO

Silicon Nitride

Titanium Nitride

TEOS

Contact Metal

Gate

STI

STI Source

Drain

Fig. 5(a) 14

Source

Drain

Fig. 5(b)

15

Source

Drain

Fig. 5(c)

16

Source

Drain

Fig. 5(d)

17

Source

Drain

Fig. 5(e)

18

Source

Drain

Fig. 5(f)

19

TEOS

TEOS

Source

Drain

Fig. 5(g)

20

Source

Drain

Fig. 5(h)

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