On The Parasitic Gate Capacitance Of Small Geometry Mosfets,

On the Parasitic Gate Capacitance of Small Geometry MOSFETs M. Jagadesh Kumar, Vivek Venkataraman and Sumeet Kumar Gupta Department of Electrical Engineering Indian Institute of Technology Huaz Khas, New Delhi 110 016, INDIA Email: [email protected] Phone: 91-11-2659 1085. Parasitic capacitances in aggressively scaled down MOSFETs play a major role in influencing the device performance. Often, accurate and simple models are required to predict the detrimental effect of the parasitic capacitances which often do not scale down with device dimensions. The paper by Kamchouchi and Zaky [1] is the earliest article to have reported a semi-analytical model for the edge capacitance of thick electrodes. Using the Kamchouchi model, various dependencies of the parasitic capacitances in small geometry MOS devices are evaluated by Greeneich [2]. Later, Suzuki [3] evaluated the dependence of parasitic capacitance on gate length, gate electrode thickness, and gate oxide thickness using a 2-D device simulator and compared his model with Kamchouci model and concluded that either Kamchouci model or Suzuki model should be used for small size devices since both models reproduce the numerical data well. Various capacitance components [3] in a scaled down MOSFET are shown in Fig.1.

LG

Ctop

tp

Cside Cbottom

Cin

tox

Fig.1 Schematic geometry of conductor silicon capacitance [3].

The Kamchouchi model [1] for Cside, Cbottom, and Ctop are given as

C side =

ε ox λn[a ] π

where

a = 2 K (K 2 − 1) t K =1+ p t ox

1/ 2

Cbottom =

+ 2K − 1

⎡ ⎡ ⎛ πL ⎞⎤ ⎤ ⎞ ε ox ⎛⎜ 2 − λn 4 − λn ⎢1 − 2 exp ⎢− 2⎜⎜1 + G ⎟⎟⎥ ⎥ ⎟ 2t ox ⎠⎦ ⎥⎦ ⎟⎠ π ⎜⎝ ⎢⎣ ⎣ ⎝

and

Ctop =

ε ox ⎡ u ⎤ λn π ⎢⎣ a ⎥⎦

where u is determined from

π LG 2 t ox

=

⎡ a R + 1⎤ a + 1 ⎡ R + 1 ⎤ a −1 R n + λ λn ⎢ ⎢ ⎥− ⎥ a R2 − 1 a ⎣ R − 1⎦ ⎣ a R − 1⎦

with

R=

u −1 u−a

However, we have noticed that in [2] and [3], the models for Ctop and Cbottom have been interchanged as given below:

Ctop =

⎡ ⎡ ⎛ πL ⎞ ⎤ ⎤ ⎞ ε ox ⎛⎜ 2 − λn 4 − λn ⎢1 − 2 exp ⎢− 2⎜⎜1 + G ⎟⎟⎥ ⎥ ⎟ π ⎜⎝ 2t ox ⎠⎦ ⎦⎥ ⎟⎠ ⎣ ⎝ ⎣⎢

and

Cbottom =

ε ox ⎡ u ⎤ λn π ⎢⎣ a ⎥⎦

It is important to use the correct models for Ctop and Cbottom as given in [1] since each of these capacitances, if considered independently, will have a different effect on the device performance. The aim of this correspondence is to bring the above to the notice of the readers so that a similar error is not carried forward in future studies.

REFERENCES [1] H. Kamchouchi and A. Zaky, “A direct method for the edge capacitance of thick electrodes,” J. Phys. D: Appl. Phys., vol. 8, pp. 1365–1371, 1975 [2] E. W. Greeneich, “An analytical model for the gate capacitance of small geometry MOS structures,” IEEE Trans. Electron Devices, vol. ED-30, pp. 1838– 1839, 1983. [3] K. Suzuki, “Parasitic capacitance of sub-micrometer MOSFET’s,” IEEE Trans. Electron Devices, vol. 46, pp. 1895–1900, Sept. 1999.

This manuscript is published in: M. Jagadesh Kumar, Vivek Venkataraman and Sumeet Kumar Gupta, "On the Parasitic Gate Capacitance of Small Geometry MOSFETs," IEEE Trans. on Electron Devices, Vol.52, pp.1676-1677, July 2005.