#a Comparison By Simulation And By Measurement Of The Substrate Noise Generated By Cmos, Csl, And Cbl Digital Circuits

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A Comparison by Simulation and by Measurement of the Substrate Noise Generated by CMOS, CSL, and CBL Digital Circuits Edgar Francisco Monteiro Albuquerque and Manuel Medeiros Silva, Senior Member, IEEE

Abstract—Current-steering logic (CSL) and current-balanced logic (CBL) are logic families that have been proposed with the objective of reducing the substrate noise in mixed-signal integrated circuits. These two families are compared here with conventional CMOS by simulation, using a substrate model extracted from the layouts, and also by measurements on a test chip. With small, low-power cells, noise reduction of CSL and CBL with respect to CMOS is only marginal; the same result is obtained with large, high-power (buffer) cells, if the supply wire inductance is very low. For large cells with typical wire bonding supply inductance (of the order of 10 nH), CBL cells provide significant noise reduction and are more effective than CSL cells; these become even noisier than CMOS cells for large inductance values. The results here, considering the real substrate noise, are more reliable than previous evaluations considering only the amplitude of the supply current spikes. Index Terms—CMOS integrated circuits, logic families, low-noise logic, mixed-signal integrated circuits, substrate noise.

I. INTRODUCTION

I

N MIXED-SIGNAL integrated circuits, there is a digital sector that generates switching noise and an analog sector to which the noise is coupled via the substrate, which is shared by the two sectors [1]. The noise coupling can be reduced, to some extent, by careful layout and routing. Further noise reduction is necessary, and this is the purpose of new low-noise logic families, that are expected to generate less noise into the substrate than conventional CMOS digital circuits [2]–[6]. The most interesting of the new families, due to their simpler structure, are current-steering logic (CSL) [6] and current-balanced logic (CBL) [7]. Reduced noise in CSL and CBL circuits is obtained by having an ideally constant supply current. Due to nonideal effects, the supply current still has spikes associated with the output voltage transitions, but their amplitude is reduced by one to two orders of magnitude with respect to CMOS. However, the substrate noise depends on the time derivative of the supply current, and not on the amplitude of its variations; furthermore, there are other sources of substrate noise, in addition to the supply current

Manuscript received March 2, 2004; revised July 9, 2004 and October 18, 2004. This work was supported by the Portuguese Foundation for Science and Technology under Project POCTI/33001/ESE/2000, Scholarships PRAXIS BD/11143/97, POCTI—SFRH/BPD/6996/2001, and Program POSI. This paper was recommended by Associate Editor G. Palumbo. The authors are with I.S.Técnico (INESC-ID), Technical University of Lisbon, 1000-029 Lisbon, Portugal (e-mail: [email protected]; [email protected]). Digital Object Identifier 10.1109/TCSI.2005.844110

Fig. 1.

Substrate noise in a mixed-signal circuit.

variation. Thus, to evaluate the effective improvement obtained with CSL or CBL it is necessary to consider the actual substrate noise. This is the purpose of this paper. We use computer simulation and also measurements on a test chip to compare the substrate noise produced by conventional CMOS with that produced by CSL and CBL. We start by reviewing substrate noise generation in mixedsignal circuits (Section II) and the low-noise families CSL and CBL (Section III). We compare, in Section IV, the substrate noise voltage in CSL and CBL cells with that in conventional CMOS cells. This is done by simulation, using a substrate model extracted from the layouts. This procedure is also used to show that the amount of substrate noise generated by CBL cells is insensitive to parameter mismatches, which is a key issue concerning the practical interest of the CBL family. In Section V, we describe the test chip, and we present the experimental results in Section VI, which is followed by the conclusions. II. SUBSTRATE NOISE IN MIXED-SIGNAL CIRCUITS In mixed-signal integrated circuits, the digital sector and the analog sector share a common substrate. In Fig. 1 we represent one transistor of the digital sector and one transistor of the analog sector. In a lumped element equivalent circuit the substrate is modeled by a single “substrate node” connected to the other nodes in the digital and analog sectors by parasitic resistances and capacitances, some of which are shown in Fig. 1 (the resistances shown would ideally be short circuits, and the capacitances would be open circuits). This single-node approach was originally adopted for duallayer substrates (thin lightly doped, high resistivity epitaxial

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layer grown on top of a thick, heavily doped, low resistivity bulk layer) used in digital technologies [1]. It has been shown that this approach is also applicable to single-layer homogeneous substrates [8], [9], such as that in the technology used in the examples in this paper. In [8] and [9] the results obtained assuming a single-node substrate representation, for both low-resistivity and high-resistivity substrates, do not differ substantially from the results obtained using a more conventional simulation procedure (boundary element method). In dual-layer substrates, the substrate node corresponds physically to the heavily doped bulk layer, which behaves as a single node. In single-layer substrates, the substrate node has meaning only for modeling purposes. One of the terminals of the external voltage supply is the “ground,” i.e., the common reference to all signals, digital and analog. The connection to the supply voltage has inductance and resistance, but only the inductance is included in Fig. 1, since the effect of the resistance can be neglected. The substrate noise is the voltage between the substrate node and the ground terminal. The substrate noise originated by the switching of the digital cells has two main sources, which are referred to here as supply noise and capacitive noise (this is called MOSFET noise in [10]). Supply noise—The supply current spikes that occur during the state transition of the digital cells are translated into a voltage , which influences the substrate node voltage. This increases with the supply inductance and with the steepness of the current spikes. Capacitive noise—The voltage steps at the nodes of the digital cells are coupled to the substrate node through the parasitic capacitances. An additional source of substrate noise is impact ionization [10], which may be significant in advanced technologies with a very thin oxide under the gate. The substrate noise voltage affects the analog cells due to the body effect and due to the capacitive coupling to the transistor terminals. This effect increases with the coupling areas (capacitances) and the steepness of the voltage variation. The supply noise can reach hundreds of millivolts [11], [12] and has been regarded as a major cause of performance degradation in mixed-signal circuits. This has motivated the development of the low-noise logic families to be reviewed in the next section. III. LOW-NOISE LOGIC FAMILIES The common principle of the low-noise logic families that have been proposed for use in mixed-signal circuits is to have a supply current that is ideally constant. Due to nonideal effects, it still has switching spikes, but their amplitude is strongly reduced, with respect to CMOS digital circuits. In the first families that were proposed [2]–[6], the constant supply current is obtained by having the connection to the power supply through a current source. These low-noise families include source-coupled logic [2], [3], folded source-coupled logic [4], nMOS CBL [5], and CSL [6]. Some of these families have limited practical interest, due to their complicated structure, with a large number of devices and terminals, which leads to large area and power dissipation and also to difficult routing.

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Fig. 2. CSL. (a) Gate. (b) Inverter.

The most interesting of these families is CSL, since CSL circuits are much simpler. Some applications of CSL circuits have been reported [13], [14]. The structure of a CSL gate is shown in Fig. 2(a), where the nMOS logic block is the same that would be used between the output and ground in an nMOS gate or in a CMOS gate. is steered to ground through the nMOS The supply current block when this is in the low resistance state (output low); otherwise it is sank through the diode connected transistor (output high). The special case of the CSL inverter is shown in , Fig. 2(b), where the nMOS block is reduced to transistor and the current source is realized by transistor with a con. stant bias voltage The current source in CSL cells is responsible for the lownoise performance, but it is also the origin of shortcomings: ; • routing of additional line for bias voltage • limited output voltage swing, since the current source , must remain in saturation (this sets a limit transistor, to the use of low supply voltage); • wide current source transistor, for acceptable output , and must be swing (this implies low enough to produce the required delay). These limitations can be overcome by using a different principle: to obtain a constant supply current, a current equalizer transistor is used instead of a current source, thus leading to a different family, CBL [7]. A CBL gate has the structure shown in Fig. 3(a). This can be ) viewed as a pseudo-nMOS gate (nMOS logic block plus has been added. If transistors [15] to which transistor and are matched, i.e.,

then it can be shown [7] that the supply current is constant, for any value of (the supply current has the same in both logic states, and remains constant during the value state transitions). In the above equations and are the threshold voltages of the pMOS and nMOS transistors, respecand are the mobilities, is the gate capacitance tively, is the aspect ratio of the transistors. per unit area, and

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Fig. 3.

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CBL. (a) Gate. (b) Inverter.

We will show below that the low noise performance of CBL is insensitive to parameter mismatches, and, therefore, accurate and is not critical. It has been shown [16] matching of that low amplitude current spikes are still obtained with shortchannel transistors, in which the velocity saturation effect does by those not allow the exact cancellation of the variations of to yield a constant . of The number of transistors in CBL and CSL gates is the same , in an -input gate). By avoiding the use of a current ( source, CBL circuits have the following important advantages with respect to CSL. • Almost full voltage swing, since the high voltage level , and the low voltage level, , can be is low. This means wider noise margins, voltage levels compatible with standard CMOS, and the possibility of low (down to V with V), and, hence, low-power operation. does not • Smaller area and power for the same delay: have to be in saturation, so it can be narrower, and, due to , the other transistors can also be narrower; capacitances are lower, and the required delay is obtained with lower current levels (a lower power-delay product is obtained, in spite of the higher voltage swing). • Simpler routing, since there is no current source bias.

IV. SIMULATION RESULTS Until now, the noise reduction provided by low-noise logic cells has been assessed simply by considering the amplitude of the supply current variation. This, however, is very insufficient, since it ignores capacitive noise, and it is not even a rigorous . What indicator of supply noise, which depends on really matters is the substrate voltage (Fig. 1), and this will be used here to compare the noise performance of CSL, CBL, and conventional CMOS. We designed the layout of the cells considering the 0.8 m CMOS technology of AMS. This is an -well technology, with uniformly doped substrate having a resistivity of 20 cm. We use the SPACE extractor [17], which was configured for this technology, to extract the circuit and substrate models from the layouts.

Fig. 4. Three inverters in our comparative study with substrate equivalent circuit (broken lines). (a) CMOS. (b) CSL. (c) CBL.

The extracted netlists would be extremely complicated, unless simplifications are made. Hence, SPACE was configured to ignore the resistance of all conductive layers (diffusions, polisilicon, metal) and the resistances between them (layer-via-layer); the sheet resistance of -wells was also ignored (this is two orders of magnitude below that of our substrate), and the only capacitances considered are the junction capacitances, including the -well/substrate capacitance (the other capacitances are much lower). Furthermore, in the substrate model, resistances between neighboring nodes are ignored when these are far apart. We use a single-node substrate model, as explained in Section II. In spite of these drastic simplifications the conclusions obtained have been confirmed by measurement on a test chip. The three cells in our comparative study are shown in Fig. 4, where the simplified substrate model is indicated. A. Low-Power Cells We consider first small cells, with low power dissipation. For a fair comparison, CSL and CBL cells are designed with equal power dissipation and with all other parameters as similar as possible for CSL, CBL and CMOS. Although the technology allows a supply voltage of 3.3 V, we use 2 V for all cells, since this leads to cells with good dynamic and static performance, using transistors with near minimum dimensions. A

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TABLE I TRANSISTOR DIMENSIONS AND EXTRACTED SUBSTRATE MODEL

higher supply voltage would be a less natural choice: power consumption would be increased, and transistors with nonminimum length would be used to produce the same bias current (thus the delay and the power-delay product would be increased). A and 0.2 V; CBL and CSL cells have 0.7 V and 1.5 V; CMOS cells CSL cells have were designed with the same delay as the CBL cells. The transistor dimensions are given in Table I, together with the resistances and capacitances of the extracted substrate model. The resistances in Table I have the order of magnitude that might be expected, in view of the results reported in the literature [8], [9]. Resistances between neighbor terminals can be one order of magnitude (or more) above resistances between the terminals and the substrate node when the distance between terminals is significantly higher than the terminals’ dimensions (resistances between nonneighbour terminals are ever higher, and they are neglected). We use HSPICE to simulate the cells inserted in 61-stage ring oscillators, in which all the cells but one are given an ideal suband in their substrate model): thus, we strate ( avoid that the noise contributions of different cells combine in a complicated way, due to the overlapping of the sequential transients, which would make it impossible to derive conclusions from the simulation results. 10 nH, which is The supply wire inductance is chosen as a typical value with wire bonding. The substrate voltage waveforms are shown in Fig. 5. It can be seen that the amplitude of the substrate noise is similar for the three families, with a minor and almost equal improvement produced by CSL and CBL. This indicates that in these low-power cells capacitive noise is dominant over supply noise: since CSL and CBL reduce only the supply noise, there is no significant improvement. B. Large Buffer Cells We now consider high-current cells, with large dimensions, suitable for driving heavy loads. The test circuits are buffer trees driven by ring oscillators, as shown in Fig. 6. The inverters in

Fig. 5. Substrate voltage waveforms in low-power cells (simulation of circuits in Fig. 4 with dimensions in Table I and L = 10 nH).

Fig. 6. Ring oscillator and buffer tree.

the ring oscillators and in the first level of the buffer tree are the low-power cells above, denoted by A. These cells, in both CSL and CBL versions, have a static supply current of 40 A. This value was chosen because the cells are fast and have transistors with near minimum dimension, for the supply voltage used (2 V). The next cells in the chain (cells B and C) have the current increased by a factor of four (160 A and 640 A), which corresponds to a tapering factor of the transistor dimensions in the range normally used in buffer chains. The last cells in the chain (cells D) have their current increased with respect to the previous ones, but their value is limited to 1500 A, since a higher current was felt to be unrealistic, in view of the very high power consumption and very wide transistors that would be required. Since the CMOS inverters do not have static supply

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TABLE II TRANSISTOR DIMENSIONS (m=m) OF CELLS IN RING OSCILLATOR AND BUFFER TREE

current, they are designed so that the average transition time is the same as that with CBL. The transistor dimensions are given in Table II. The noise generated by the larger buffers in the tree (D in Fig. 6) will be dominant, since they have higher supply noise ) and higher capacitive noise (due to the (due to the high large area). For a fair comparison it is important that these cells are suitably designed. The criterion that we have adopted for the CSL and CBL cells is that they have the same static current (and hence the same power consumption) and the same low . The CMOS cell, having no static output voltage level power consumption, was dimensioned to have the same average transition time as the CBL cell, which will lead to a fair comparison, since the noise is related to the transition time. For the output buffer cells D, the power-delay product of CBL, 692 fJ, is lower than that of CSL, 1697 fJ, which is one of the advantages of CBL, as pointed out above. Both values are much higher than the power-delay product of the corresponding CMOS cell, 14.4 fJ. This is due to the static supply current of CSL and CBL, which must be regarded as the price to be paid for their low-noise property. It should be noted that CSL and CBL are not general purpose logic families, and should not be considered as a replacement for CMOS in general digital systems. CSL and CBL have been proposed as alternatives to CMOS for mixed-signal integrated circuits, in which it is very important to reduce the substrate noise. The extracted substrate model was a rather complicated resistive network involving all cells (in the ring oscillator and buffer tree). We have performed HSPICE simulations for different values of the supply wire inductance , and we have plotted the amplitude of the substrate noise voltage in Fig. 7. 10 nH are shown in Fig. 8. The waveforms for For low inductance values nH the same conclusions apply that were obtained above for the low-power cells, indicating that the supply noise is much lower than capacitive noise, which was to be expected, in view of the low inductance. For medium inductance levels, around 10 nH (typical values with wire bonding), significant noise reduction with respect to CMOS is obtained with CBL. This indicates that the supply noise is now important. This is in accordance with our expectations, considering the high supply current and significant inductance. CSL also provides some noise reduction, but less than CBL. With very high inductance levels, CSL circuits became very noisy.

Fig. 7. Substrate noise amplitude versus supply wire inductance, in high-power cells (simulation of the circuits in Fig. 6 with dimensions in Table II).

Fig. 8. Substrate voltage waveforms in high-power cells (simulation of the circuits in Fig. 6 with dimensions in Table II and L = 10 nH).

For low-current cells the substrate noise level is very similar for CSL and CBL. This is also true for high-current cells with very low supply inductance; with medium/high inductance CSL becomes significantly noisier than CBL. C. Effect of Parameter Mismatches on CBL Noise Supply noise reduction in CBL cells is due to the conand (Fig. 3) stant supply current when transistors are matched. In order to find how sensitive CBL cells are to parameter mismatches, we consider the same CBL ring oscillator and buffer tree as above. We apply the same simulation procedure to obtain the substrate noise voltage with nominal and matched) and with a mismatch parameter values (

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Fig. 11. Microphotograph of (a) ring oscillator + buffer trees, and (b) noise detecting transistor.

Fig. 9. Effect of parameter mismatches on CBL substrate noise (simulation of circuits in Fig. 6 with dimensions in Table II and L 10 nH).

=

Fig. 12.

Fig. 10.

Noise receiver (analog) in the test circuit.

of 20% in and (these are the largest mismatches to be expected with the technology under consideration). The results, in Fig. 9, show that the substrate noise is very insensitive to parameter mismatches, which confirms the interest of CBL from a practical point of view. V. EXPERIMENTAL RESULTS In the test circuit, we use as noise generators the same buffer trees driven by ring oscillators that have been simulated (Fig. 6), with the same transistor dimensions (Table II). To probe the substrate noise voltage, a large noise-sensing nMOS transistor is used, as in [1], which is placed far from the ring oscillators on the test chip (about 3 mm), with additional precautions being taken to ensure that the noise coupling through the substrate is dominant with respect to the coupling through the bonding wires. The noise-sensing transistor is a common-source stage loaded by the 50- input of the oscilloscope (Fig. 10). The gate bias voltage and, hence, the stage gain is externally adjusted so that the drain signal is high enough to

Printed circuit test board.

be observed clearly. A microphotograph of this noise detector is shown in Fig. 11(b). A microphotograph of the three ring oscillators with buffer trees is shown in Fig. 11(a). The value of the supply inductance is expected to be at least 10 nH, due to the wire bonding and printed circuit tracks. In this situation, the effect of the substrate noise will be easier to detect, since it will be dominant with respect to other forms of noise. This is the situation in which low-noise families are more likely to be of practical interest. The test chip was attached directly to a printed circuit board (PCB) with wire bonding from the pads on the chip to tracks on the PCB (chip-on-board). This test board (Fig. 12) contains an integrated circuit voltage regulator (6 V/2 V), that produces the supply voltage for the digital cells, and resistive trimmers to adjust the regulator output voltage, the current source in the CSL cells, and the quiescent current in the noise detector (6 mA). There are also four jumper switches, to select the ring oscillator that is active, by controlling a CMOS switch that closes the loop of the ring oscillator. An SMA connector is attached directly to the PCB. The test board was designed very carefully to avoid spurious effects: paths are the shortest possible, connections to the ring oscillators are far apart from those to the noise detector, and all empty spaces are filled with ground planes. The circuit is powered by batteries. Decoupling capacitors have not been used, since we have found that they cause some ringing.

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experimental waveforms (Fig. 13) has been performed. Concerning the simulation waveforms, the spectral contents of CBL is only significant below 500 MHz; it is narrower that in the case of CMOS and CSL, which have spectral contents, upto about 800 MHz. There is significant high frequency contents (around 600 MHz) in the CSL spectrum, due to the ringing that can be observed in the corresponding waveform in Fig. 8. The experimental waveforms have a narrower spectrum than the simulation waveforms, which can be explained by the filtering due to the measurement setup (the spectrum is limited to about 300 MHz in all three cases). An alternative way of comparing the effect of the substrate noise for the three types of cells is to measure the jitter of the ring oscillators. We have obtained for the standard deviation of the oscillation period the following values: CMOS 72 ps; CSL 101 ps; CBL 27 ps. We find again that the substrate noise effect is reduced for CBL, with respect to CMOS, and it is not reduced for CSL (the jitter values are approximately in the same proportion as the amplitude of the noise waveforms in Fig. 13). VI. CONCLUSION

Fig. 13.

Drain voltage with noise in transistor of Fig. 10.

The voltage waveforms at the drain of the noise detector transistor are shown in Fig. 13 and from these, conclusions can be derived which agree with those obtained from the simulation results in Fig. 8. The waveforms in Fig. 8 are the noise voltage between the substrate node and ground in a reduced model of the substrate. Fig. 13 shows measurements of the voltage induced by substrate noise on the noise probing transistor. There is no simple theoretical relationship between the waveforms in Figs. 8 and 13, but the amplitude of the waveforms in each figure can be used to compare the noise performance of the three logic families. The conclusions from the experimental waveforms agree with the conclusions obtained from the simulation waveforms. The peak-to-peak values in Figs. 8 and 13 show that CBL noise is 2.5 times lower than CMOS noise. The noise amplitude is higher in CSL than in CMOS, which is explained by the very : the large area large width of the current source transistor means that there is a very high capacitive noise, and this is confirmed by the shape of the CSL waveform in Fig. 13 (it has the shape of the response of an RC circuit, and is different from the other waveforms, which have the shape of spikes’ derivatives). These results do not mean that CSL circuits are useless: it is only for very large cells, as those here, that they fail to produce substrate noise improvement. For these large cells only CBL can produce an improvement. The conclusions above apply to the amplitude of the noise waveforms. To compare the spectrum of the waveforms, the fast Fourier transform (FFT) of both the simulation (Fig. 8) and

We have compared, by computer simulations and by measurements on a test chip, the substrate noise produced by CMOS digital circuits with the noise produced by CSL and CBL circuits. In the simulations we have considered both small (low-power) cells and large (high-power) buffer cells. The large cells have been included in a test chip and a good agreement has been obtained between experimental and simulation results. This comparative study shows the following. • For small cells (low-power), the noise reduction provided by CSL and CBL with respect to CMOS is only marginal; this indicates that in small cells capacitive noise is dominant over supply noise. • For large (buffer) cells with very low supply wire inductance, the same conclusion as above applies. For medium and high inductance levels (such as those to be expected with wire bonding) CBL cells are effective in reducing the substrate noise, which indicates that, in this case, the supply noise dominates over capacitive noise; CSL cells are less effective, and, for high inductance levels, provide no improvement with respect CMOS. Simulations have also been used to demonstrate that the low noise property of CBL cells has low sensitivity to parameter mismatches. The general conclusion of this work is that the real substrate noise improvement obtained with the low-noise families is less than indicated by looking simply at the amplitude of the supply current spikes. The reduction is only significant for large cells, and, for these, CBL is more effective than CSL if the supply wire inductance is high. ACKNOWLEDGMENT The authors wish to thanks Prof. L. Silveira for his advice concerning substrate model extraction, and the anonymous reviewers, whose comments have led to a clarification of several points in the text.

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REFERENCES [1] D. K. Su, M. J. Loinaz, S. Masui, and B. A. Wooley, “Experimental results and modeling techniques for substrate noise in mixed-signal integrated circuits,” IEEE J. Solid-State Circuits, vol. 28, no. 4, pp. 420–430, Apr. 1993. [2] S. Kiaei, S.-H. Chee, and D. J. Allstot, “CMOS source-coupled logic for mixed-mode VLSI,” in Proc. IEEE Int. Symp. Circuits and Systems, May 1990, pp. 1608–1611. [3] M. Maleki and S. Kiaei, “Enhancement source-coupled logic for mixedmode VLSI circuits,” IEEE Trans. Circuits and Systems I, vol. 39, no. 6, pp. 399–402, Jun. 1992. [4] D. J. Allstot, S.-H. Chee, S. Kiaei, and M. Shrivastawa, “Folded sourcecoupled logic vs. CMOS static logic for low-noise mixed-signal ICs,” IEEE Trans. Circuits and Systems I, vol. 40, no. 9, pp. 553–563, Sep. 1993. [5] E. Albuquerque, J. Fernandes, and M. Silva, “nMOS-current balanced logic,” Electron. Lett., vol. 32, no. 11, pp. 997–998, 1996. [6] H.-T. Ng and D. J. Allstot, “CMOS current steering logic for low-voltage mixed-signal integrated circuits,” IEEE Trans. VLSI Syst., vol. 5, pp. 301–308, Sep. 1997. [7] E. Albuquerque and M. Silva, “A new low-noise logic family for mixedsignal ICs,” IEEE Trans. Circuits Syst. I, Fundam. Theory Appl., vol. 46, no. 12, pp. 1498–1500, Dec. 1999. [8] A. J. van Genderen, N. P. van der Meijs, and T. Smedes, “Fast computation of substrate resistances in large circuits,” in Proc. Electronic Design and Test Conf., Mar. 1996, pp. 560–565. [9] N. P. van der Meijs, “SPACE for substrate resistance modeling,” in Substrate Noise Coupling in Mixed-Signal ASICs, S. Donnay and G. Gielen, Eds. Norwell, MA: Kluwer, 2003, pp. 65–92. [10] M. Heijningen, J. Compiet, P. Wambacq, S. Donnay, M. Engels, and I. Bolsens, “Analysis and experimental verification of digital substrate noise generation for epi-type substrates,” IEEE J. Solid-State Circuits, vol. 35, no. 7, pp. 1002–1008, Jul. 2000. [11] M. Felder and J. Ganger, “Analysis of ground-bounce induced substrate noise coupling in a low resistivity bulk epitaxial process: design strategies to minimize noise effects on a mixed-signal chip,” IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 46, no. 11, pp. 1427–1436, Nov. 1999. [12] B. R. Stanisic, N. K. Verghese, R. A. Rutenbar, L. R. Carley, and D. J. Allstot, “Addressing substrate coupling in mixed-mode ICs: simulation and power distribution synthesis,” IEEE J. Solid-State Circuits, vol. 29, no. 3, pp. 226–237, Mar. 1994. [13] G. Miao, H. C. Yang, and P. Tang, “An oversampled A/D converter with cascaded fourth order sigma-delta modulation and current-steering logic,” in Proc. IEEE Int. Symp. Circuits and Systems, May 1998, pp. 412–415.

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[14] H. C. Yang, L. K. Lee, and R. S. Co, “A low jitter 0.3–165 MHz CMOS PLL frequency synthesizer for 3 V/5 V operation,” IEEE J. Solid-State Circuits, vol. 32, no. 4, pp. 582–586, Apr. 1997. [15] A. Sedra and K. Smith, Microelectronic Circuits (5th edition). Oxford, U.K.: Oxford Univ. Press, 1998. [16] Z. Butokovic and A. Szabo, “Current-ballanced logic in submicron technology,” in Proc. IEEE MELECON’02, May 2002, pp. 41–44. [17] SPACE v 4.7.1, HELIOS v 1.4.1 Layout to Circuit Extractor Software and Manuals [Online]. Available: http://cobalt.et.tudelft.nl/~space/

Edgar Francisco Monteiro Albuquerque was born in Goa, India, in 1969. He received the graduate degree in electrical and computer engineering, and the M.Sc. and Ph.D. degrees from Instituto Superior Técnico, Technical University of Lisbon, Lisbon, Portugal, in 1994, 1998, and 2001, respectively. He is a Post-Doctoral Fellow at INESC-ID. His research interests are in analog and mixed-signal integrated circuits and data converters. He has also been interested in renewable energy systems, particularly in wind energy.

Manuel Medeiros Silva (M’76–SM’81) was born in Ponta Delgada, Azores, in 1943. He received the degree in electrical engineering from Instituto Superior Técnico, Technical University of Lisbon, Lisbon, Portugal, and the Ph.D. degree from the Imperial College, University of London, London, U.K., in 1967 and 1976, respectively. He was a Professor of Electronics in the Electrical and Computer Engineering Department of Instituto Superior Técnico. He retired from teaching in 2004, but continues his research activity at INESC-ID, where he is head of the Research Group on Analog and Mixed-Signal Circuits (URL: http://analog.inesc-id.pt/medeiros.html). His research interests are in the fields of analog and mixed-signal integrated circuits, analog and digital filters, data converters, and power electronics. He is the author of two textbooks on circuit theory and electronic circuits. Prof. Silva was the founding chairman of the IEEE Portugal Section.

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