#effect Of Substrate Noise On Cmos Rf Circuits

Substrate Noise in Mixed-Signal Integrated Circuits

Min Xu 9/6/2001 Center for Integrated Systems Stanford University Stanford, CA 94305 Now with Big Bear Networks, Inc. 1591 McCarthy Blvd. Milpitas, CA 95035

Outline • Introduction -

Motivation

-

Overall picture

• Test Vehicles • Substrate noise ~ digital circuits (F1) • Analog circuits ~ substrate noise (F2) • Impact on the GPS receiver system • Conclusions

1

C Min Xu, Stanford University

System on a Chip!

PLL Amplifier

Processor

Mixer Memory Filter A/D D/A

I/O

Integrating the entire system on a chip has the advantage of low cost, small size, and low power, but the system is susceptible to performance degradation caused by substrate noise coupling.

2

C Min Xu, Stanford University

System on a Chip?

low cost small size low power

System on a chip

3

switching noise scaling

Two-chip solution

C Min Xu, Stanford University

Reports on Substrate Noise Impact •

Degraded circuit performance -

•

Forced separation of analog and digital circuits in two chip -

•

"In the original design, analog and digital functions were implemented in a single chip, however to reduce digital noise coupling and improve BER performance it is necessary to use separate analog and digital test chips." (K. Azadet, ISSCC, 2000)

Prediction and suggestion -

4

8-bit, semiflash pipelined video A/D continued to fail several specifications after three design fabrication iterations, DNL>+/-1 LSB. (N. K. Verghese, JSSC, March, 1996)

"The optimal solution to cross-talk is a two-chip solution with the first chip contains the sensitive analog circuitry and has no digital." (K. Bult, ISSCC, 1999)

C Min Xu, Stanford University

Overall Picture of Substrate Noise Problem

analog circuit

digital circuit

bs

tra

te

F2

Vsub2

5

propagates (P)

su

F1 Vsub1

•

Vsub1=Vsub2=Vsub for epi process (single node approximation).

•

Vsub=F1(digital clock scheme, package)

•

Analog circuit performance = F2(Vsub)

•

Find F1, F2?

C Min Xu, Stanford University

Approaches of Earlier Research digital circuit te

analog circuit

Vsub2

propagates (P)

su

F1

bs

tra

F2

Vsub1

substrate noise time domain response

equivalent substrate impedance process and isolation techniques, such as guard rings

Vmax

Tsettle

6

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Approach of this Work I. Possible Substrate Noise Effects on Analog Circuits

•

System function:

Y = F2(X+x0+δx, B+δb)

X = dc input, B = bias, x0 = ac input, δb = bias perturbation, δx = input perturbation

•

Expand Y into its Taylor series, retaining only terms as high as second order. The frequency locations of the terms are fs, fn, 0, 2fs, 2fn, fs+fn, |fs-fn| fs = signal frequency,

7

fn = noise frequency,

C Min Xu, Stanford University

Approach of this Work II.

Possible Substrate Noise Effects on a System Noise tones caused by substrate noise

Intermodulation between signal and substrate noise

|Y(f)|2

signal band

fmin

fmax

f

Illustration of substrate noise effects in analog circuits. If noise falls into analog signal band, it will cause SNR reduction; otherwise, the noise in the analog circuit output can be filtered out.

8

C Min Xu, Stanford University

Outline • Introduction • Test Vehicles -

Analog circuit --- LNA

-

Digital circuit emulator

-

Substrate noise sensor

• Substrate noise ~ digital circuits (F1) • Analog circuits ~ substrate noise (F2) • Impacts on the GPS receiver system • Conclusions

9

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Low Noise Amplifier (LNA)* Outp

Outm

Ibias Vb

+ -

CMFB Inm

Inp M1

M2

* D. K. Shaeffer, et al., “A 115-mW, 0.5µm CMOS GPS Receiver with Wide Dynamic-range Active Filters,” IEEE J. Solid-State Circuits, vol. 33, pp. 2219-2231, Dec. 1998

10

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Digital Circuit Emulator sel

clk

digital clock

amp clk_b

mux

shift register clk_in

11

N+ 2C0 N+

x2 sel sel enb_0 enb_1

data_in

C0

x1 enb1

ring oscillator sel

enb0

enb_5 enb6_1 enb6_2 enb6_3

enb5 x 32

32C0 N+

enb6_1,enb6_2 enb6_3 56C0 x56 N+

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Substrate Noise Sensor

Vdd=2.5V

clock

bias

N+

P-

N+

50Ω

Vsensor_out N+

P+

substrate diffusion contact capacitor + channel stop implant P

P+ Bulk

12

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Chip Microdiagram DIGITAL CIRCUIT EMULATOR

SENSOR

LNA

13

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Outline • Introduction • Test Vehicles • Substrate noise ~ digital circuits (F1) -

Substrate noise generated by the digital circuit emulator

-

Generalized model of F1

• Analog circuits ~ substrate noise (F2) • Impacts on the GPS receiver system • Conclusions

14

C Min Xu, Stanford University

Measured Substrate Noise Waveform

An example of the substrate-noise waveform measured at the substrate noise sensor output

0.02

tsettle

Vout (V)

0.01

Vpp 0

Vnp

−0.01 −0.02 −100

−50

0

50

100

Time (ns) Ccouple= 43.52 pF, fclock = 7.1 MHz, trise/fall = 0.9 ns

15

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Time-Domain Substrate Noise Characteristics

Substrate noise magnitude increases linearly with coupling capacitance

Substrate noise settling time does not change with the coupling capacitance 0.015 0.01

0.01

Vout (V)

Vout (V)

0.02

0 −0.01

0.005 0 −0.005 −0.01

−0.02

0

20

40

60

Ccouple (pF) fclock = 7.1 MHz, trise/fall = 0.9 ns

16

−0.015 −5

0

5

time (ns) sensor output when Ccouple = 16, 32, 48, 64, 80, 96, 120, 152, 180C0 fclock = 7.1 MHz, trise/fall = 0.9 ns

C Min Xu, Stanford University

10

Model of Substrate Noise Injection

Lvdd

Vdd

Vdd

Lvdd Rvdd

Rvdd

Rpmos

Mp

Vout

Vin

Cp

Cp Ccouple

Vout

Rp

Ccouple

Rcouple

Mn

Rcouple Vsub(s)

Lgnd

(a)

17

Rn

equivalent to Zsub

Cn

Zsub_up

Vsub(s) Rgnd

Rp

(b)

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Substrate Noise Caused by a Single Digital Transition •

In the s domain, substrate noise caused by a single digital transition is C couple V dd Z sub – up V sub – up ( s ) = --------------------------- × -------------------------------------------------------------------------------------( 1 + t rise s ) ( Z sub – up + L vdd s + R vdd )C s p 1 + ---------------------------------------------------------------------------1 + R pC p s

tup = rise time, Ccouple << Cp

•

and Rp << Rpmos

Substrate noise is a linear function of the Ccouple if trise/fall is a constant. Therefore substrate noise root function is defined as V dd Z sub – up 1 -------------------------------------------------------------------------------------------------------------V root – u p ( s ) = × ( 1 + t rise s ) ( Z sub – up + L vdd s + R vdd )C s p 1 + ---------------------------------------------------------------------------1 + R pC p s

and in time domain as

18

–1

u u p, 1 ( t ) = L ( V root – u p ( s ) )

C Min Xu, Stanford University

Substrate Noise vs. trise/fall I. Time Domain In time domain, substrate noise magnitude decreases as trise/fall increases enb6_1

8C0

x8

N+

enb6_2

digital clock

16C0

x 16

N

enb6_3 x 32

+

Three buffers all on, trise/fall= 0.9 ns

5

5

0

Vout (mV)

Vout (mV)

32C0

N

Only enb6_1 is on, trise/fall = 5.4 ns

−5 −50

0

Time (ns)

19

+

50

0 −5 −50

0

50

Time (ns)

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Substrate Noise vs. trise/fall II. Frequency Domain

Only enb6_1 is on, trise/fall = 5.4 ns

Three buffers all on, trise/fall= 0.9 ns

−40

−40

Vout (dBm)

Vout (dBm)

In frequency domain, increasing trise/fall reduces high frequency substrate noise power, but does not reduce low frequency substrate noise power

−60 −80 −100

500

1000

Frequency (MHz)

20

1500

−60 −80 −100

500

1000

1500

Frequency (MHz)

C Min Xu, Stanford University

Analysis of Substrate Noise Spectral Distribution

•

In time domain, the total substrate noise is the summation of substrate noise caused by each digital transition.

•

For digital circuits with a periodic switching pattern, the substrate noise spectra distribution is the Fourier transform of the time domain substrate noise. C couple 2 2 n n  S ( f ) = ------------------- U up ( f ) + ( – 1 ) U down ( f ) δ  f – ---  T   T

C couple 2 1 n  S ( f ) ∝ ------------------- ----------------------------- δ  f – ---  T  2  T 1 + ( 2πfτ )

21

n = integer

n = integer

C Min Xu, Stanford University

Staggering the Digital Switching I. Time Domain In time domain, staggering digital switching reduces substrate noise magnitude Normal switching

Staggering the digital switching

enb1 x 48

48C0 N+ 48C0 N+

10

10

5

5

0 −5 −10 −50

48C0 N+ 48C0 N+

0 −5 −10

−25

0

Time (ns)

22

enb1 x 48

Vout (mV)

Vout (mV)

enb1 x 48

enb1 x 48

25

50

−50

−25

0

25

50

Time (ns)

C Min Xu, Stanford University

Staggering the Digital Switching II. Frequency Domain In frequency domain, staggering digital switching does not reduce substrate noise in all frequency ranges. Normal switching

enb1 x 48 enb1 x 48

Staggering the digital switching

enb1 x 48

48C0 N

+

enb1 x 48

48C0 N

+

−60 −80 −100

50

100

150

200

Frequency (MHz)

23

N

48C0 +

N

−40

Vout (dBm)

Vout (dBm)

−40

48C0 +

250

300

−60 −80 −100

50

100

150

200

250

300

Frequency (MHz)

C Min Xu, Stanford University

Outline • Introduction • Test Vehicles • Substrate noise ~ digital circuits (F1) -

Substrate noise generated by the digital circuit emulator

-

Generalized model of F1

• Analog circuits ~ substrate noise (F2) • Impacts on the GPS receiver system • Conclusions

24

C Min Xu, Stanford University

Model of F1 Using Filter Banks (I) If substrate noise caused by every digital transition is of the same shape uup,1(t) - substrate noise root function, which describes the substrate noise shape pup,1(t) - capacitance switching rate functions coupling capacitance at time τ: pup,1(τ)dτ

magnitude

uup,1(t-τ) x pup,1(τ)dτ

τ

substrate noise caused by the transitions at time t

Time

τ+dτ

substrate noise at time t: v sub, u p, 1 ( t ) =

t

∫–∞ uu p, 1 ( t – τ ) pu p, 1 ( τ ) dτ

= u u p, 1 ( t ) ⊗ p u p, 1 ( t )

25

C Min Xu, Stanford University

Model of F1 Using Filter Banks (I) N types of substrate noise root functions for low-to-high digital transitions M types of substrate noise root functions for high-to-low digital transitions uup, 1(t)

.. .

u u p, 1 ( t ) ⊗ p u p, 1 ( t )

.. .

.. .

uup, N(t)

udown, 1(t)

u u p, N ( t ) ⊗ p u p, N ( t )

.. .

.. . (t)

udown, M

u down, 1 ( t ) ⊗ p down, 1 ( t )

.. .

u down, M ( t ) ⊗ p down, M ( t )

Time

t

total substrate noise at time t v sub ( t ) =

26

N

M

k=1

k=1

∑ uu p, k ( t ) ⊗ pu p, k ( t ) + ∑ u down, k ( t ) ⊗ p down, k ( t ) C Min Xu, Stanford University

Model of F1 Using Filter Banks (II) pup, 1(t)

.. . pup, N(t)

Uup, 1(f)

.. . Uup, N(f)

u u p, 1 ( t ) ⊗ p u p, 1 ( t )

.. .

Substrate noise caused by low to high transition

u u p, N ( t ) ⊗ p u p, N ( t )

+ pdown, 1(t)

.. . pdown, M(t)

Udown, 1(f)

Vsub(t)

u down, 1 ( t ) ⊗ p down, 1 ( t )

.. . Udown, M(f) u down, M

.. . (t) ⊗ p

down, M ( t )

Substrate noise caused by high to low transition

Filter Bank Digital circuit switching scheme

27

Substrate noise root functions

Substrate noise corresponds to each distinct uup/down,k(t)

C Min Xu, Stanford University

Substrate Noise vs. Digital Switching Pattern (I) An array of identical inverters, therefore, there are two types of substrate noise root functions:

N+

uup,1(t): for low-to-high transition, udown,1(t): for high-to-low tansition

N+

.. .

and two capacitance switching rate functions:

.. .

pup,1(t) for low-to-high transition, pdown,1(t) for high-to-low transition

N+

pup, 1(t)

Uup, 1(f)

Filter-bank model pdown, 1(t)

28

+

Vsub(t)

Udown, 1(f)

C Min Xu, Stanford University

Substrate Noise vs. Digital Switching Pattern II. Periodic Switching If all the buffere inputs are driven by the same clock, the change of digital clock duty cycle changes the filter inputs, thus redistributes substrate noise spectrum.

pup, 1(t)

Uup, 1(f)

+

pdown, 1(t)

Udown, 1(f)

digital clock cycle=50%

digital clock dutycycle=25%

Vout (dBm)

Vout (dBm)

−20 −40

−20 −40 −60

−60 50

100 150 200 Frequency (MHz)

250

300

trise,fall=0.9nsec, fclock=24.8MHz, Ccouple=96Co

29

Vsub(t)

50

100 150 200 250 Frequency (MHz)

300

trise,fall=0.9nsec, fclock=24.8MHz, Ccouple=96Co

C Min Xu, Stanford University

Substrate Noise vs. Digital Switching Pattern III. Random Switching If pup(t) and pdown(t) are i.i.d and wide-sense stationary random processes, the substrate noise spectrum becomes continuous 2

S ( f ) = m δ ( f ) ( u up + u down )

where ∞ u ( t ) dt – ∞ up

∫

u down =

Udown, 1(f)

S(f)

σ2(|Uup(f)|2+|Udown(f)|2) |Uup(f)|2+|Udown(f)|2

∞

σ = var ( p up ( t ) ) = var ( p down ( t ) )

30

+

pdown, 1(t)

Vsub(t)

∫–∞ u down ( t ) dt

m = E ( p up ( t ) ) = E ( p down ( t ) ) 2

Uup, 1(f)

2

2 2 2 + σ  U up ( f ) + U down ( f )   

u up =

pup, 1(t)

m2δ(f)(uup+udown)2

f

C Min Xu, Stanford University

Key Issues in Modeling F1 •

Use frequency domain approach Some widely accepted time-domain substrate noise reduction methods may not be effective, e.g.:

•

-

Staggering the digital switching

-

Increasing the digital transition time

Key factors in the model -

Substrate noise root function physical characteristics of digital circuitry

-

Digital switching scheme timing characteristics of digital circuitry

31

C Min Xu, Stanford University

Outline • Introduction • Test Vehicles • Substrate noise ~ digital circuits (F1) • Analog circuits ~ substrate noise (F2) • Impacts on the GPS receiver system • Conclusions

32

C Min Xu, Stanford University

Measured LNA Outputs Noise tones appear at the LNA output when the digital circuit turns on Digital circuit on

−40

−40

−60

−60

V(dBm)

V(dBm)

Digital circuit off

−80 −100 1350

1400

1450

1500

1550

1600

Frequency (MHz)

−80 −100 1350

1400

1450

1500

1550

1600

Frequency (MHz) RF input = -60 dBm, 1.575 GHz

RF input = -60 dBm, 1.575 GHz Digital circuit operation condition: fclock= 39.825 MHz, trise/fall= 0.9 ns Duty cycle= 50%, Ccouple= 32.6 pF

33

C Min Xu, Stanford University

Measured Substrate Noise Spectrum

Measured substrate noise spectrum at the substrate noise sensor output

V(dBm)

−40

−60

−80

−100

200

400

600

800

1000

1200

1400

1600

1800

Frequency (MHz) RF input = -60 dBm, 1.575 GHz Digital circuit operation condition: fclock= 39.825 MHz, trise/fall= 0.9 ns, Duty cycle= 50%, Ccouple= 32.6 pF

34

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Analysis of Noise Coupling Mechanism δxd − differential-mode noise δxc, δb − common-mode noise

F(X+xd/2+δxd/2+δxc, B+δb)

+

Differential Output: Y

− F(X-xd/2-δxd/2+δxc, B+δb)

Y ∂F = ∂x

x=X

fs

35

∂F xd + ∂x

2

2

δ xd + x=X

fn

∂ F ∂x

2 x=X

2

2

∂ F ∂ F δ xc x d + xd δb + 2 ∂ x ∂b x = X ∂x b = B

fs+fn, |fs-fn|

x=X

∂ F δ xd δ xc + δ δ ∂ b ∂ x x = X xd b b = B

0, 2fn

C Min Xu, Stanford University

Noise Coupling Mechanisms for this LNA

•

IM noise tones (frf-nfclock) in the LNA output are caused by the LOW frequency common mode noise. -

•

Harmonic tones of the digital clock (nfclock) in the LNA output are caused by the HIGH frequency differential mode noise. -

36

Analysis and simulations show that substrate noise is the dominant common mode noise source.

Caused by the differential mode noise: asymmetry of the board, package, bonding, chip.

C Min Xu, Stanford University

Effects of Common-mode Noise I. Identifying IM Noise in the LNA Output Move RF down 5 MHz, the intermodulation (IM) noise tones are moved down by 5 MHz. Measured LNA output −40

V(dBm)

RF input = -60 dBm, 1.575 GHz −60 −80

*

−100 1350

* 1400

* 1450

* 1500

1550

*

Digital circuit operation condition: fclock= 39.825 MHz, trise/fall= 0.9 ns Duty cycle = 50%, Ccouple= 32.6 pF

1600

−40

V(dBm)

RF input = -60 dBm, 1.570 GHz −60 −80 −100 1350

*

* 1400

* 1450

* 1500

* 1550

Digital circuit operation condition: fclock= 39.825 MHz, trise/fall= 0.9 ns Duty cycle = 50%, Ccouple= 32.6 pF

1600

Frequency (MHz)

37

C Min Xu, Stanford University

Effects of Common-mode Noise I. Identifying IM Noise in the LNA Output (cont’d) Reduce the RF signal power by 10 dB, the intermodulation (IM) noise power is reduced by 10dB. Measured LNA output −40

RF input = -60 dBm, 1.575 GHz V(dBm)

−60 −80

*

−100 1350 −40

* 1400

*

*

1450

1500

* 1550

Digital circuit operation condition: fclock= 39.825 MHz, trise/fall= 0.9 ns Duty cycle = 50%, Ccouple= 61.2 pF

1600

V(dBm)

RF input = -70 dBm, 1.575 GHz −60 −80

* −100 1350

* 1400

* 1450

* 1500

1550

*

Digital circuit operation condition: fclock= 39.825 MHz, trise/fall= 0.9 ns Duty cycle = 50%, Ccouple= 61.2 pF

1600

Frequency (MHz)

38

C Min Xu, Stanford University

Effects of Common-Mode Noise II.

Model

•

Mechanism: perturb the bias condition of the LNA

•

Model: single node approximation of the substrate

LNA output −40

V(dBm)

Measured LNA output −60

Simulated LNA output with single node approximation of the substrate

−80

−100 1350

1400

1450

1500

1550

1600

Frequency (MHz)

39

C Min Xu, Stanford University

Effects of Common-Mode Noise III. Experimental Verification •

Theoretical prediction I M ∝ V sub

 2  ⇒ IM power ∝ C couple V sub ∝ C couple 

•

Measurements

Power (dBm)

0 −20

*

119 MHz substrate noise tone measured with the substrate noise sensor

+

1.456 GHz IM noise at the LNA output

−40 −60 −80 −100 2

4

8

16

32

Ccouple (pF)

40

C Min Xu, Stanford University

Effects of Differential-mode Noise I. Noise Sources

•

41

Differential-mode noise is caused by mismatch between the two differential branches that results from

-

location difference with regarding to the digital circuit

-

bonding mismatch

-

on chip inductor pairs dilemma

-

mismatch of devices from process variation

C Min Xu, Stanford University

Effects of Differential-Mode Noise II. Model (difficult) Differential-mode noise is difficult to model due to its stochastic and distributed characteristics •

stochastic: process variation

•

distributed: important at high frequency ≈ Aφ

2πl 2πlf µε φ = -------- = ---------------------λ c

v diff = 10

42

A

F1

F2

Example: f=1.5GHz, l=100µm –2

digital circuit

analog circuit

1

l

te

jωt

tra

– Ae

bs

j ( ωt + φ )

2

3

su

v diff = Ae

C Min Xu, Stanford University

Effects of Differential-Mode Noise III. Measurements •

Theoretical prediction DCN ∝ V sub

  DCN 1 1  ⇒ power ∝ ------------------------------2 V sub ∝ -------------------------------------------------  ( t rise ⁄ fall ) ( 1 + 2πjf t rise ⁄ fall )  DCN --- directly coupled noise

•

Measurements −60

V(dBm)

1.513 GHz tone at the LNA output −70

RF input = -60 dBm, 1.575 GHz

−80

Digital circuit operation condition: fclock= 39.825 MHz, Duty cycle = 50%, Ccouple= 19 pF

−90 0.8

1

2

3

4

5

6

trise/fall (ns)

43

C Min Xu, Stanford University

Outline • Introduction • Test Vehicles • Substrate noise ~ digital circuits (F1) • Analog circuits ~ substrate noise (F2) • Impact on the GPS receiver system • Conclusions

44

C Min Xu, Stanford University

Bad news • Substrate noise power (~ −10dBm in this study) is several orders of magnitude higher than that of the received signal of GPS receiver (− 130dBm)

• To the accuracy of the second order nonlinearity of the LNA, Substrate noise effects can be divided into

45

-

Differential mode noise: couple directly into the LNA output with some gain factor

-

Common mode noise: modulate with differential RF interference and fall into the GPS signal band.

C Min Xu, Stanford University

GPS Receiver Block Diagram* Antenna 2.048MHz

1.57542GHz

I[n]

mixer RF filter

IF amp

IF filter

A/D

DSP

LNA Q[n]

π/2

limiting amp LO=1.573GHz

*D. K. Shaeffer, et al., “A 115-mW, 0.5µm CMOS GPS Receiver with Wide Dynamic-range Active Filters,” IEEE J. Solid-State Circuits, vol. 33, pp. 2219-2231, Dec. 1998

46

C Min Xu, Stanford University

GPS signal structure* Thermal noise Floor

-175.2dBm/Hz ~-15dB

-190.1~-183.1dBm/Hz

direct sequence spread spectum

C/A code

P code

2.046MHz 1.57542GHz 20MHz *J. J. Spilker, Jr., “GPS Signal Structure and Theoretical Performance,” in B/W. Parkinson and J.J Spilker, Jr., Eds., Global Positioning System: Theory and Applications, vol. I. American Institute of Aeronautics an Astronautics, 1996, pp57-119

47

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Spread Spectrum System* Data signal

Spread spectrumsignal

Interferer Demodulated data

Noise

Radio

Spread spectrum modulator

DATA IN

Trans mitter

Radio

Receiver

Spread spectrum Demodulator

DATA OUT

* Olav Berg, Tore Berg, Svein Haavik, Jens Hjelmstad and Reidar Skaug, “Spread Spectrum in Mobile Communication,” The Institution of Electrical Engineers, London, UK, 1998

48

C Min Xu, Stanford University

GPS Signal Spectrum in the Receiver Signal Path 2MHz

1.57542GHz 1.57542GHz 2.046MHz

2.046MHz

2.046MHz

0dB -68dB

Antenna

3.5MHz

10MHz

DSP RF filter

49

LNA LO=1.573GHz

C Min Xu, Stanford University

Good news •

Frequency selective characteristics -

•

Only low frequency common-mode noise and high frequency differential-mode noise will actually degrade the performance of the LNA

Single chip solutions might be possible by -

Careful design of the digital switching scheme

-

Modifying the LNA

-

Employing system-level techniques, and making full use of the interference rejecting ability of the spread spectrum GPS signal structure =>

High order RF filter

=>

Adaptive quantizer*

=>

Adaptive frequency notch filter*

*J. J. Spilker Jr., and F. D. Natali, “Interference Effects and Mitigation Techniques”, in B/W. Parkinson and J.J Spilker, Jr., Eds., Global Positioning System: Theory and Applications, vol. I. American Institute of Aeronautics an Astronautics, 1996, pp717-771.

50

C Min Xu, Stanford University

Outline • Introduction • Test Vehicles • Substrate noise ~ digital circuits (F1) • Analog circuits ~ substrate noise (F2) • Impacts on the GPS receiver system • Conclusions

51

C Min Xu, Stanford University

Summary of this Work

-

•

F2: substrate noise effects on analog circuits

Vsub2

te

F2 F1 propagates (P)

Vsub1

Frequency domain approach and the functional relationships between the source of substrate noise and its effects provides insight into substrate noise mitigation. -

52

F1: substrate noise as a function of digital circuit characteristics

digital circuit tra

-

analog circuit

bs

Experimentally and theoretically studied

su

•

Extend the process of substrate noise minimization beyond the substrate itself to the design of the sensitive analog circuits, the digital circuits that are the source of the noise, and the system architecture.

C Min Xu, Stanford University

Design Recommendations I. From the Analog circuit designing

•

Fully differential architecture

•

Reduce the differential mode noise effects by -

•

Reduce the common mode noise effects by -

53

Symmetric layout, bonding

Reducing derivatives of system function with respect to the common mode noise (δxc, δb)

C Min Xu, Stanford University

Design Recommendations II. From the Digital designing Depends on the signal band of the mixed-signal system, optimize the substrate noise spectral distribution, some examples: 1. Narrow band

2. High center frequency

high frequency digital clock |power

|power

noise

signal band

increase trise/fall signal band

substrate noise envolope

filter

f

f

3. Wide band Stagger the digital switching, so as to reduce the TOTAL substrate noise power. 4. Reduce substrate impedance at the directly coupling band, or intermodulation band by proper substrate contact, bypassing, bonding, packaging.

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C Min Xu, Stanford University

Design Recommendations III. From the System designing

•

Employing system-level techniques, and making full use of interference rejecting ability of the spread spectrum GPS signal structure -

High order RF filter

-

Adaptive quantizer*

-

Adaptive frequency notch filter*

*J. J. Spilker Jr., and F. D. Natali, “Interference Effects and Mitigation Techniques”, in B/W. Parkinson and J.J Spilker, Jr., Eds., Global Positioning System: Theory and Applications, vol. I. American Institute of Aeronautics an Astronautics, 1996, pp717-771.

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C Min Xu, Stanford University