54215-mt----cmos Analog & Mixed Signal Design

NR

Code No: 54215/MT

M.Tech. – II Semester Regular Examinations, September, 2008 CMOS ANALOG & MIXED SIGNAL DESIGN (Digital Systems & Computer Electronics) Time: 3hours

Max. Marks:60 Answer any FIVE questions All questions carry equal marks ---

1.a) b)

2.a) b)

Using small signal analysis, Derive an expression for the output resistance of the triple cascode current source. Using the Wilson current mirror shown in figure.1 and the CN 20 process, design a mirror in which I0=150 µA with IREF = 50 µA for VDD=5V,VSS=0V.

Explain the behavior of the MOSFET-only voltage divider. Design a MOSFET-MOSFET voltage divider shown in figure-2 so that the reference voltage, Vref is 2V and the current through each MOSFET is 10 µA. Contd…2.,

Code No: 54215/MT

3.a) b)

4.

::2::

Estimate the small signal voltage gain of the common source amplifier with current source load. Assume that both M1 and M2 are biased in the saturation region. The amplifier shown in figure-3 is during a 10 pF load capacitor. What is the maximum rate the load capacitance can be charged. Is there a slew rate limitation for discharging the capacitor?

Explain the properties of negative feed back on amplifier design. Contd…3.,

Code No: 54215/MT

::3::

5.a)

For the differential amplifier shown in figure-4. Determine the drain current of M1 as a function of the input voltage, Vi1-Vi2.

b)

Explain the technique to extend the allowable input swing of a differential amplifier.

6.a)

For OTA, derive the expressions for voltage gain output current and transconductance. Explain the purpose of common mode feed back circuit in differential input-output op-Amp’s.

b) 7.a) b) 8.a) b)

Can the self biased comparator be used as a wide-swing op-Amp? If so explain how would the op-Amp be compensated. Explain dynamic comparator & dynamic biasing of current mirror circuits. Explain the methods used to prevent aliasing and the advantages and disadvantages of each. Design a 3-bitflash ADC with its quantization error centered about zero LSB’s. Determine the worst case DNL and INL if resistor matching is known to be 5%. Assume that Vref = 5V. x-x-x