Mixed Signal Lecture Pll

Mixed signal systems and integrated circuits

Akira Matsuzawa Tokyo Institute of Technology 2005/5/10

A. Matsuzawa

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PLL system • •

Basic PLL system Basic circuit block – Phase detector • Analog mixer • Digital 3 state Phase Frequency Detector • Charge pump circuit

– Filter – Voltage Controlled Oscillator

• •

Pull-in process System characteristics (frequency and time response) – With 1st order filter – With Lag-Lead filter

• • •

2005/5/10

Delay Locked Loop Clock recovery circuits Frequency synthesizer

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Phase locked loop (PLL) Application area 1. 2. 3. 4.

Internal clock generation in LSI locked to external clock Frequency Synthesizer for communication systems Clock recovery for communication systems and data storage systems FM demodulation

Frequency Synthesizer

Fast settling and accurate frequency are required

Clock recovery

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Basic Phase-Locked Loop (PLL) system PLL is a feedback system to match the input signal phase and the output signal phase. Through this process, frequencies of these signals become equal completely.

V PD = K p (θi − θo )

Higher frequency components are attenuated

Input signal

θi

θo

Phase detector

Filter (LPF)

ωvco ∝ Vc

Vc

Voltage Controlled Oscillator

Output signal

Basic construction of a PLL system

Frequency Divider

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Waveforms in PLL system

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Analog phase detector (mixer type) Suitable for high frequency application, but no ability as a frequency detector sin (ω1t + θ1 )

Vout

A Vout

sin ((ω1 + ω2 )t + θ1 + θ 2 ) Filter out

Vout

B

cos (ω2 t + θ 2 ) A

+ sin ((ω1 − ω2 )t + θ1 − θ 2 ) ≈ sin (θ1 − θ 2 ) ≈ θ1 − θ 2 Vout ≈ θ1 − θ 2

B

−π

π

π

2

2

π Δθ

Gilbert cell PD (Small signal) Or EXOR 2005/5/10

−

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3 state Phase Frequency Detector This 3 state phase detector is currently most widely used. Because it has a ability for frequency detect. “1”

D

Q

Up

A

Clk

A

B

R

Glitch Up

R

B Clk “1”

D

Q

Down

Down Vout goes “High”, if rising edge comes earlier.

B

Frequency detector State II State 0 A B UP=0 UP=0 Down=1 Down=0 A B

Vout

State I UP=1 Down=0

A

− 2π 2π

Δθ

Works as an Up-Down counter 2005/5/10

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Dead zone in PFD The most serious issue of PFD is dead zone at a small phase deviation. This causes a large jitter and a phase noise. Improved PDF

Id

Insert delay circuits

Δθ

Dead zone

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Narrow pulse effect If the output pulse is very narrow, the pulse height can not exceed the logic threshold voltage. This results in the missing data. Finally, this makes the dead zone.

2005/5/10

A. Matsuzawa

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Charge pump circuit The charge pump circuit can generate the averaged current of which the value is proportional to the phase difference.

This circuit works as Digital to Analog Converter.

Ipump up

Vcont to VCO

IPD

F(s) Δθ

down Ipump

I PD = K PD ⋅ Δθ K PD =

I pump 2π

( A / rad )

2π

IPD :Effective average current 2005/5/10

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Actual charge pump circuit Cascode: high impedance and small capacitance

Prevent large voltage change, when not connected

Stable node voltage

Active filter

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Voltage Controlled Oscillator Design points

Proper tuning range Low jitter and phase noise Low power supply noise and stability High linearity for V to f characteristics

Vcntr is low

Frequency

Vcntr

VCO

ωout = ω fr + KVCO ⋅ Vcntr Vcntr is high

ωmax ωfr ωmin Vmin

2005/5/10

Vcenter Vmax

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Vcont 12

VCO VCO act as a low pass filter to the control voltage signal

ωout = ω fr + K VCOVcntr

(

∫

y( t ) = A cos ω fr t + K VCO Vcntr dt For example :

)

Vcntr ( t ) = Vm cos ωm t

⎛ ⎞ K y( t ) = A cos ⎜⎜ ω fr t + VCO Vm sin ωm t ⎟⎟ ωm ⎝ ⎠

High frequency component in Vcntr can be suppressed 2005/5/10

Low frequency component in Vcntr can't be suppressed

A. Matsuzawa

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Current starved Ring oscillator This ring oscillator is widely used for the digital clock generator in LSI

Current sourse

IVCO Ring Oscillator (Odd stages) Vcntr

C tot = C out + C in = C ox ( L pW p + LnWn ) +

3 C ox ( L pW p + LnWn ) 2

5 C ox ( L pW p + LnWn ) 2 I VCO = N ⋅ C tot ⋅ VDD =

f osc

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Merit: easy implementation on LSI Issue: large jitter noise A. Matsuzawa

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VCO (Source coupled VCO) VDD

VDD VDD

Out M1

M1

M2

X VinVCO

M2

2Io

Off

Y

Discharge X

Io

Out

M2 on

M1 on

Io

M2 on

Out

Sometime used for Low frequency oscillator

Y Io

M1 on M2 on

Out

Low frequency generation Differential signal High noise tolerance

VDD VDD-VTHN

Y X Time 2005/5/10

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