54211-mt----design Of Fault Tolerant Systems

NR

Code No: 54211/MT

M.Tech. – II Semester Regular Examinations, September, 2008 DESIGN OF FAULT TOLERANT SYSTEMS (Common to Digital Systems & Computer Electronics/ Digital Electronics & Communication Systems) Time: 3hours

Max. Marks:60 Answer any FIVE questions All questions carry equal marks ---

1.a) b)

Define ‘Maintainability’, ‘Availability’ and Mean–time-to-repair (MTTR) and their inter relationship? Show that the reliability of parallel-to-series interconnection of subsystems each with reliability ‘R’ is always greater than seriesto-parallel inter connection.

2.

Explain the hardware masking technique ‘Triple Modular Redundancy’ and discuss its advantages and disadvantages?

3.a)

Discuss the advantages of Berger codes compared with m-out-of-n codes? Explain the design procedure of check bit generator circuit for Berger codes?

b) 4.

Design a fail safe machine using partian theory for the sequential machine described by the following state table. Input Present state A B C D E

I1 C, 0 B, 1 C, 0 B, 1 E, 0

I2 C, 0 C, 0 B, 0 A, 0 E, 0

I3 A, 0 D, 1 A, 0 D, 1 A, 0

I4 A, 0 A, 0 A, 0 A, 0 A, 0

5.

Explain the Read-Muller Expansion technique with the help of an example.

6.

Explain briefly the LFSR. Explain LFSR may be used as signature analyzer?

7.

Explain level sensitive scan design method of synthesizing testable sequential circuit?

8.

Explain in detail the generic offline BIST architecture? $$$