Rr321503-fault-tolerant-systems

Set No. 1

Code No: RR321503

III B.Tech Supplimentary Examinations, Aug/Sep 2008 FAULT TOLERANT SYSTEMS (Computer Science & Systems Engineering) Time: 3 hours Max Marks: 80 Answer any FIVE Questions All Questions carry equal marks ⋆⋆⋆⋆⋆ 1. (a) Distinguish between failures, and faults ? Explain

[2+2]

(b) Explain the different modeling schemes of faults that generally come across in digital circuits. [3x2=6] (c) Explain the following terms with respect to digital circuits with suitable examples. i. Fault diagnosis. ii. Fault detection test set. iii. Test vector generation.

[3x2=6]

2. (a) A circuit realizes the function. Z=X1 X4 +X2 X3 +X1 X4 Using Boolean Difference method find the test vectors for SA0, SA1 faults on all input lines of the circuit. (b) What are the different properties of Boolean differences? Explain

[5+5+6]

3. (a) Explain the 5MR Reconfiguration scheme. Explain in detail the function of each block. [4+4] (b) Discuss the 3 cases for which the 5MR system automatically reconfigure to tolerate single and multiple faults. Explain each with an example. [3+3+2] 4. (a) What is the mechanism adopted in COPRA a fault Tolerant system. Explain in detail. (b) What is meant by Time redundancy? Explain.

[4+4+4+4]

5. (a) Design a checker for 1 out of 3 codes that satisfy the partially strongly fault secure properties. (b) Explain the principle of operation of strongly fault secure circuit with one example. [8+8] 6. (a) Explain the general appraoch to the design of totally self-checking PLAs. (b) Explain why self-checking machines are essential in digital system.

[10+6]

7. (a) Prove that five tests are sufficient to detect all faults in a combinational logic circuit by inserting addition control logic to the following function, obtain the test pattern. f=(A,B,C,D)=AB+BC+BD 1 of 2

Set No. 1

Code No: RR321503

(b) Obtain the ten sequences denoted as P = {xo x1 ......xa } from the basic module of the above circuit and get the compatable pair from the set P. [8+8] 8. (a) What is meant by controllability? Explain with suitable examples.

[3+5]

(b) What is meant by Observability? Explain with suitable examples.

[3+5]

⋆⋆⋆⋆⋆

2 of 2

Set No. 2

Code No: RR321503

III B.Tech Supplimentary Examinations, Aug/Sep 2008 FAULT TOLERANT SYSTEMS (Computer Science & Systems Engineering) Time: 3 hours Max Marks: 80 Answer any FIVE Questions All Questions carry equal marks ⋆⋆⋆⋆⋆ 1. (a) A computer system contains 10,000 components each with failure rate 0.5% per 1000 hours. What is the period of 0.99 reliability of this system. (b) What is meant by active repair time and passive repair time referred in maintainability of a system. Derive the expression for the MTTR. [6+3+3+4] 2. For the circuit shown as in figure 2 , derive

Figure 2 (a) minimal complete fixed scheduled fault detection experiment. (b) minimal complete fixed scheduled fault location experiment.

[8+8]

3. (a) Construct a seven-bit error correcting code to represent the decimal digit by augmenting the Excess-3 code and by using add-1 parity check. (b) Design a redundant circuit for f = a ⊕ b

[9+7]

4. (a) What is the mechanism adopted in COPRA a fault Tolerant system. Explain in detail. (b) What is meant by Time redundancy? Explain.

[4+4+4+4]

5. (a) List out the advantages and disadvantages of self-checking circuit in all aspects. [3+3] (b) Design a totally self checking checker circuit for a given berger code of length I bits.Explain with an example the design procedure. [5+5] 6. (a) Explain the advantages of PLA and how it is used as totally self-checking circuit. (b) For the given 4 input, 4 output function design a totally self checking checker circuit using PLAs. [6+10] P f1 (A,B,C,D) = (0,2,3,7,8,10,12,13,15) 1 of 2

Set No. 2

Code No: RR321503 P f2 (A,B,C,D) = P (0,2,3,4,9,12,13,15) f3 (A,B,C,D) = P (0,1,2,4,8,9,10,14) f4 (A,B,C,D) = (0,1,2,4,5,6,8,11,14).

7. (a) Explain the Reed-Muller expansion Technique used in Design for testable circuit. (b) Obtain the Reed Muller circuit for the given function. Also give the test set for the same. f = AB + AC + BC [8+4+4] 8. List Level Sensitive Scan Design rules and explain. Distinguish between single and double latch LSSD. [10+3+3] ⋆⋆⋆⋆⋆

2 of 2

Set No. 3

Code No: RR321503

III B.Tech Supplimentary Examinations, Aug/Sep 2008 FAULT TOLERANT SYSTEMS (Computer Science & Systems Engineering) Time: 3 hours Max Marks: 80 Answer any FIVE Questions All Questions carry equal marks ⋆⋆⋆⋆⋆ 1. (a) A computer system contains 10,000 components each with failure rate 0.5% per 1000 hours. What is the period of 0.99 reliability of this system. (b) What is meant by active repair time and passive repair time referred in maintainability of a system. Derive the expression for the MTTR. [6+3+3+4] 2. (a) A circuit realizes the function. Z=X1 X4 +X2 X3 +X1 X4 Using Boolean Difference method find the test vectors for SA0, SA1 faults on all input lines of the circuit. (b) What are the different properties of Boolean differences? Explain

[5+5+6]

3. (a) Analyze the circuit shown in figure3a. below for static hazards. Redesign the circuit so that it becomes hazard free?

Figure 3a (b) What is the importance of Hamming code in Fault Tolerant System. [5+5+4] 4. (a) Explain in detail the practicle fault Tolerant space shuttle computer complex system. (b) What are the different ways to have software redundancy.

[8+8]

5. (a) What is the need for self checking circuits (b) Design a totally self checking checker by using reddy’s partition method for 2out of 5 code. [6+10] 6. (a) Explain the design consideration of self checking PLA considering stray faults with suitable example. 1 of 2

Set No. 3

Code No: RR321503

(b) How do you implement strong fault service for the functional PLA.

[8+8]

7. (a) What are the goals of a design for testability? (b) What are the different DET methods available? Explain at least two such techniques. [6+4+6] 8. (a) What is meant by controllability? Explain with suitable examples.

[3+5]

(b) What is meant by Observability? Explain with suitable examples.

[3+5]

⋆⋆⋆⋆⋆

2 of 2

Set No. 4

Code No: RR321503

III B.Tech Supplimentary Examinations, Aug/Sep 2008 FAULT TOLERANT SYSTEMS (Computer Science & Systems Engineering) Time: 3 hours Max Marks: 80 Answer any FIVE Questions All Questions carry equal marks ⋆⋆⋆⋆⋆ 1. (a) A computer system contains 10,000 components each with failure rate 0.5% per 1000 hours. What is the period of 0.99 reliability of this system. (b) What is meant by active repair time and passive repair time referred in maintainability of a system. Derive the expression for the MTTR. [6+3+3+4] 2. (a) A circuit realizes the function. Z=X1 X4 +X2 X3 +X1 X4 Using Boolean Difference method find the test vectors for SA0, SA1 faults on all input lines of the circuit. (b) What are the different properties of Boolean differences? Explain

[5+5+6]

3. (a) Design a redundant circuit for f = ab + a′ b′ (b) Explain the Dynamic redundancy Technique of a fault Tolerant system.[8+8] 4. With an example explain : (a) software redundancy. (b) time redundancy.

[8+8]

5. Design a totally self-checking checker for maximal-length Berger codes also give the procedure to generate test vectors of 8 bit long. [8+8] 6. (a) Explain the advantages of PLA and how it is used as totally self-checking circuit. (b) For the given 4 input, 4 output function design a totally self checking checker circuit using PLAs. [6+10] P f1 (A,B,C,D) =P (0,2,3,7,8,10,12,13,15) f2 (A,B,C,D) = P (0,2,3,4,9,12,13,15) f3 (A,B,C,D) = P (0,1,2,4,8,9,10,14) f4 (A,B,C,D) = (0,1,2,4,5,6,8,11,14). 7. (a) Explain the Reed-Muller expansion Technique used in Design for testable circuit. (b) Obtain the Reed Muller circuit for the given function. Also give the test set for the same. [8+4+4] f = AB + AC + BC 8. (a) Draw the logic diagram of Built-in Logic Block Observer. 1 of 2

Set No. 4

Code No: RR321503 (b) Discuss BILBO based BIST architecture. ⋆⋆⋆⋆⋆

2 of 2

[8+8]