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11.3

A Variable Gain CMOS Amplifier with Exponential Gain Control Christopher W. Mangelsdorf Analog Devices, Japan 1-16-1 Kaigan, Minato-ku Tokyo 105-6891 Japan phone: 8 1-3-5402-8254 fax: 81-3-5402- 1065 [email protected]

Abstract A variable gain amplifier architecture suitable for foundry CMOS is constructed using linearized transconductance blocks. The use of a four-transistor transconductance cell allows for wider gain range and larger signal swing under low supply conditions than the simple differential pair used in previous work. Experimental results with 0.6 um CMOS show -5 to 35 dB gain and 20 MHz bandwidth at 21 mW.

Introduction High speed analog signal processing channels in hard disk drives and CCD imaging equipment make use of variable gain amplifiers (VGAs) for adaptive control of signal amplitudes under a wide variety of conditions. System requirements dictate that the best choice for such VGAs is an exponential control characteristic (i.e. linear in dB). Switched capacitor techniques can be used to create digitally programmable gain, but because the VGA is part of a system wide gain control servo, monotonicity is essential. Also, real time image processing systems need very smooth gain transitions to prevent jumps in picture brightness as an image is scanned. These requirements translate to a very high level of gain "resolutions" and gain linearity or "DNL". Consequently, a switched capacitor implementation requires a large number of capacitors and tight controls on mismatch. A continuously variable analog control scheme, on the other hand, efficiently provides a monotonic characteristic which is free from jumps or steps. For this reason, analog gain control was chosen instead of a switched-cap implementation. If the ultimate application requires digital control, an external DAC can be used, allowing the designer to concentrate on handling the linearity problems in a low speed control channel rather than in the signal path. The requirements of the particular application presented were for a range from 0 to 34 dB (1X to 50X) which could handle signals as large as 1 volt p-p with reasonable distortion (approx. 1%). Of course this amp had to be high speed, low noise, low power and 3 volt compatible using foundry CMOS.

Figure 1

If the bias is arranged so that the current in one pair increases as the current in the other pair decreases, the resulting equations have the form,

Gml= k * G

Gain = G ~ I / G)= -~/, Z

(3)

where Gml is the input stage transconductance, Gm2 is the conductance of the diode connected load, x is a control variable which varies between +1 and -1, and k is a constant. Over a limited range, this last expression is a very good approximation to an exponential. For the present application, however, this approach has two drawbacks. Because current control of transconductance is used, the gain is limited by the square-root nature of the device to a fairly small range. Also, the signal path linearity is not very good unless large Vgs voltages are used. A solution more suitable for the present requirements of wide gain range, large signal swing and low supply voltage is to use two "linearized" transconductors rather than simple differential pairs. Researchers developing CMOS multipliers have come up with variable transconductors that are not only linear for fairly large signals, but the transconductance is also a linear function of the control signal. Hence,

Exponential Control (4)

For disk drive applications, variable gain amplifiers have been developed using variable MOS transconductances (1). A standard differential pair with variable tail current is used to drive a pair of diode-connected devices, also with variable bias current as shown in Fig. 1.

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Cm2 = k * (1 - x)

Gain = ~ m 1 / ~ = m(12+ x)/(l- x )

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which approximates an exponential over a larger gain range.

(Z4 - I , ) + ( [ ,

-I3)=k*(4ViVs)+k*(4ViVb-4ViVs) = k * (4ViVb) (10)

Linear Transconductors The linearization scheme chosen here is similar to one published by Wang and Guggenbuhl of the Swiss Federal Institute of Technology (2,3). The basis of the linearization is shown in Fig. 2, where all of the transistors are the same size. Pot

r

Amplifier Topology The differential current output of the Gm stage shown in Fig. 2 can be passed to a similar, diode-connected stage acting as a load. Fig. 3 shows how this can be achieved. Notice that the source node of the output stage is connected to a fixed voltage, not a current source.

in1 1°C

IPS

1 '

Q Figure 2

Figure 3

If the voltage Vb is large, transistors M2 and M3 carry all the current and the transconductance is that of a simple differential pair. As Vb is decreased, M1 and M 4 carry more current and decrease the net transconductance of the cell. (At Vb=O, the transconductance goes to zero.) In fact, the transconductance is

G m = C * Vb

(7)

until you start to turn the outer pair off. (Here C is a constant de ending on bias and device size.) This can be seen as follows.

P

For the outer pair:

I , - I , =k*(-Vi-Vs)2-k*(Vi-Vs)2

There are now two sets of controlling voltages, Vbf ("f' for "front") and Vbb ("b" for "back'). By making these voltages vary linearly in opposite directions, i.e. one increases as the other decreases, we can get the desired (l+x)/(l-x) behavior required to approximate the exponential. Alternatively, if we fix one of the control voltages, we get a simple linear, or l/x control characteristic for the stage. The circuit is improved by putting more sophisticated feedback around the output stage. For one thing, a much more predictable gain characteristic at the high and low gains can be achieved if the impedance at the output is reduced using the loop gain. Although there are several ways to handle the feedback, Fig. 4 shows how it is done in the present application. Here the two transconductance stages are configured as an "ads-amp"* architecture with a voltage gain stage, A, closing the loop. The output Gm is servoed to match the differential current from the input Gm.

= k * (4vivs)

For the outer pair:

1r2 1 Vi2+Vb2 +Vs2 + 2ViVb - 2VbVs - 2ViVs

=

*

Figure 4

+ Vb2+ Vs

- 2ViVb - 2VbVs

+ 2ViVs

= k * (4ViVb - 4ViVs) (9)

So the total differential current is:

'

To simplify the calculations, a threshold voltage of 0 volts is used for all devices.

One drawback of this implementation is the fact that the loop gain will vary as the output transconductance is changed. To avoid this, another Gm stage is connected as a simple diode as shown in Fig. 5 . Here the voltage gain stage of Fig. 4 is replaced by a fixed transconductance, "GM', and a copy of the original output transconductor, "Gmo". Both of the Gmo transconductors in the output stage are controlled by the same signals so that they track each other and keep the gain of the loop constant as the gain varied. Note that this This topology lacks a unique name, but Banie Gilbert has recently dubbed it "active feedback'.

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147

diode connected Gmo does not really create the output voltage as in Fig. 3, it merely loads the loop. The output voltage is created by the servo action of the loop and is thus much more accurate.

Input

output

Results Fig. 9 shows measured results for 0.6 um CMOS and 3 volt supplies. The plot is in dB, and is relatively straight for the 0.5V 2.5V range indicating exponential behavior. Table 1 summarizes the circuit parameters and performance.

-

35

30 25 20

-

Figure 5

A simplified version of the differential topology is shown in' Fig. 6 and the complete schematic is in Fig. 7. The control voltages (the Vb's) are created by variable currents through polysilicon resistors. Vpf, - Vpb, - Vnf, and Vnb are all variable control voltages. The others, Vbpl, Vbp2, Vbn2, and VbnO are all fixed bias levels. The two output transconductance stages shown in Figs. 5 and 6 have been merged in Fig. 7 so that they use the same control signals.

.

0

0.5

1

1.5

2

2.5

Control Voltage (v)

Figure 9

Table 1 process: gain range: power supply: dissipation: bandwidth: die area:

0.6um CMOS, 2-poly, 2-AI Oto34dB 2.7 to 3.3 V 21 mW (VGA, 3V) 2.3 mW (control ckt, 3V) 20 MHz 680 sq. mil

References

I

I

Figure 6 The last refinement evident in Fig. 7 is to tweak the loop gain a bit to do an even better job of compensation. The resistors in the output stage marked with "*" have the effect of making the diode connected Gm vary a bit faster than the feedback Gm. This makes for more constant closed-loop bandwidth as the gain is changed.

(1) R. Harjani, "A Low-Power CMOS VGA for 5OMb/s Disk Drive Read Channels", IEEE Transactions on Circuits and Systems 11, vol. 42, no. 6, June 1995, pp. 370-376.

(2) Wang and Guggenbuhl, "A VariableXontrollable Linear MOS Transconductor Using Bias Offset Technique", IEEE Journal of Solid-state Circuits, vol. 25, no. 1, Feb. 1990, pp. 315-317. (3) Z. Wang, "A CMOS Four-Quadrant Analog Multiplier with Single-Ended Voltage Output and Improved Temperature Performance", IEEE Journal of Solid-state Circuits, vol. 26, no. 9, Sept. 1991, pp. 1293-1301.

Control Circuit The circuit which generates the variable control voltages is shown in Fig. 8. This is designed to yield the (l+x)/(l-x) function, that is, Vbf decreases as Vbb increases. If the resistor attached to the "gain control voltage" terminal is made of the same material as the resistors in Fig. 7, the gain control characteristic will be independent of sheet rho variations.

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3

1 i9

]E

m

> n

a0 l 0

i; c 3

n

c 3

0

s Figure 8 Control Circuit Schematic L

01

0 0

i; c

IJ n C

I

Figure 7 VGA Schematic

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