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Sequential Circuits

1. Ways of Describing Sequential Circuits

2. Flip-Flops 3. Registers and Counters 4. Finite State Machines

Sequential Circuits

1

1. Ways of Describing Sequential Circuits

1.1 Definition 1.2 Description

Sequential Circuits

2

1. Ways of Describing Sequential Circuits 1.1 Definition

X

CLC

Qn

CLC X Y Qn Qn+1

Y

Qn+1 Y2 Memory

The typical structure of the sequential circuit

Combinational logic circuit Input signals Output signals; Current state; Next state

Observation: X  X1 , X 2 ,, X m 

Y  Y1 , Y2 ,, Yp  Q  Q1 , Q 2 ,, Q r  Sequential Circuits

3

1. Ways of Describing Sequential Circuits 1.1 Definitions (cont.)

X

CLC

Qn

Definition: Sequential logic circuit is defined as the quintuple:

Y

SS={X, Y, Q ,f, g}

Qn+1 Y2 Memory

The typical structure of the sequential circuit X  X1 , X 2 ,, X m 

X Y Q F g

set of inputs; set of outputs; set of states; transition function of the states; transition function of the outputs.

f : XQ  Q g :XQ  Y

Y  Y1 , Y2 ,, Yp 

Q  Q1 , Q2 ,, Qr 

Sequential Circuits

or

g:Q  Y

4

1. Ways of Describing Sequential Circuits 1.2 Description Sequential circuits can be represented in three ways: •transition tables; •charts; •flow graphs (transition graphs).

Sequential Circuits

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1. Ways of Describing Sequential Circuits 1.2 Description Transition Table Input

Current State

Next State

Output

Xn+1

Qn

Qn+1

Yn+1

Depending on the application

Depending on the application

Depending on the application

Depending on the application

Sequential Circuits

6

1. Ways of Describing Sequential Circuits 1.2 Description Transition Table

Example:

Let’s analyze a machine with two states, two outputs and a single input. In other words: Q={0, 1} X1={0, 1} X2={0, 1} Y={0, 1} The transition table will look like this:

Sequential Circuits

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1. Ways of Describing Sequential Circuits 1.2 Description Transition Table

Input X1,n+1 X2,n+1 0 0 1 0 0 1 1 1 0 0 1 0 0 1 1 1

Current State Qn 0 0 0 0 1 1 1 1

Next State Qn+1 1 0 1 1 0 1 0 1

Sequential Circuits

Output Yn+1 0 1 0 1 0 1 1 0

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1. Ways of Describing Sequential Circuits 1.2 Description Transition Table

•If •If •If •If •If •If •If •If

{X1,X2}={0,0} and Qn=0 then Qn+1=1 and Y=1 (line 1) {X1,X2}={1,0} and Qn=0 then Qn+1=0 and Y=1 (line 2) {X1,X2}={0,1} and Qn=0 then Qn+1=1 and Y=0 (line 3) {X1,X2}={1,1} and Qn=0 then Qn+1=0 and Y=0 (line 4) {X1,X2}={0,0} and Qn=1 then Qn+1=0 and Y=0 (line 5) {X1,X2}={1,0} and Qn=1 then Qn+1=1 and Y=1 (line 6) {X1,X2}={0,1} and Qn=1 then Qn+1=0 and Y=1 (line 7) {X1,X2}={1,1} and Qn=1 then Qn+1=1 and Y=0 (line 8)

Sequential Circuits

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1. Ways of Describing Sequential Circuits 1.2 Description Chart Only transitions starting from “0” state are presented

•If •If •If •If

Qn=0 and {X1,X2}={0,0} then Qn+1=1 and Y=1 Qn=0 and {X1,X2}={1,0} then Qn+1=0 and Y=1 Qn=0 and {X1,X2}={0,1} then Qn+1=1 and Y=0 Qn=0 and {X1,X2}={1,1} then Qn+1=0 and Y=0

Sequential Circuits

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1. Ways of Describing Sequential Circuits 1.2 Description Flow Grafs

Flow graf associated with transition from state "0" to "1“

Sequential Circuits

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2. Flip-Flops 2.1 RS Flip-Flop 2.2 D Flip-Flop 2.3 JK Flip-Flop

Sequential Circuits

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2.1 RS Flip-Flop 2.1.1 RS Latch 2.1.2 Latch RS Latch 2.1.3 Gated RS Latch

Sequential Circuits

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2.1 RS Flip-Flop 2.1.1 RS NOR Latch a.) Symbol

RS Latch ANSI standard

RS Latch DIN standard

b.) Notation R, S Q, Q

Data inputs Data outputs

Sequential Circuits

14

2.1 RS Flip-Flop 2.1.1 RS NOR Latch c.) Schematic Diagram

d.) Operation Inputs A B 0 0 0 1 1 0 1 1

Output Y 1 0 0 0

Truth table for NOR gate type Sequential Circuits

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2.1 RS Flip-Flop 2.1.1 RS NOR Latch d.) Operation Input

Next State

Comments

Sn

Rn

Qn+1

0

0

Qn

Qn

Hold state

0

1

1

Set

0

1

0

1

Reset

1

1

0

0

Not allowed

Q n+1

Simplified transition table for the RS NOR latch

Sequential Circuits

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2.1 RS Flip-Flop 2.1.1 S Latch d.) Operation Inputs

Next State

Comments

Sn

Rn

Qn+1

0

0

Qn

Qn

Hold state

1

0

1

0

Set

0

1

0

1

Reset

1

1

1

0

Set

Q n+1

Simplified transition table for the S latch

Sequential Circuits

17

2.1 RS Flip-Flop 2.1.1 R Latch d.) Operation Inputs

Next Stage

Comments

Sn

Rn

Qn+1

0

0

Qn

Qn

Hold state

1

0

1

0

Set

0

1

0

1

Reset

1

1

0

1

Reset

Q n+1

Simplified transition table for the R latch

Sequential Circuits

18

2.1 RS Flip-Flop 2.1.1 E Latch d.) Operation Inputs

Next Stage

Comentarii

Sn

Rn

Qn+1

0

0

Qn

Qn

Hold state

1

0

1

0

Set

0

1

0

1

Reset

1

1

Qn

Qn

Hold state

Q n+1

Simplified transition table for the E latch

Sequential Circuits

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2.1 RS Flip-Flop 2.1.1 RS Latch e.) SPICE Simulation

Circuit used to simulate the operation of a RS latch

Waveforms associated with the operation of a RS latch

Sequential Circuits

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2.1 RS Flip-Flop 2.1.1 RS Latch e.) SPICE Simulation The analysis of the waveforms must be made taking into account two objectives: i. ”When” Analysis - when the transitions occur; ii. ”How” Analysis - how transitions occur. i.) ”When” Analysis Waveform analysis reveals that the output transitions are controlled by signals applied to the inputs R and S – times t1 – t6. ii.) ”How” Analysis Waveform analysis reveals that: Q=0; _ interval t1 – t2 S=1; R=0 Q=1 _ interval t2 – t3 S=0; R=0 Q=1 Q=0; _ interval t3 – t4 S=0; R=1 Q=0 Q=1; _ interval t4 – t5 S=0; R=0 Q=0 Q =1; Q =1. _ interval t5 – t6 S=0; R=0 Q=0 Conclusion: The results presented confirm the transition table. Sequential Circuits

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2.1 RS Flip-Flop 2.1.2 RS Latch a.) Symbol

Latch RS Latch ANSI standard

RS Latch DIN standard

b.) Notation R, S Q, Q

Data inputs. Outputs

Sequential Circuits

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2.1 RS Flip-Flop 2.1.2 RS Latch c.) Schematic diagram

d.) Operation Inputs A B 0 0 0 1 1 0 1 1

Output Y 1 1 1 0

Truth table for NAND gate Sequential Circuits

23

2.1 RS Flip-Flop 2.1.2 RS Latch d.) Operation Inputs

Next State

Comments

Sn

Rn

Qn+1

0

0

Qn+1= Q n+1=1

Not allowed

1

0

1

Set

0

1

0

Reset

1

1

Qn

Hold state

Simplified transition table for the R S latch

Sequential Circuits

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2.1 RS Flip-Flop 2.1.2 RS Latch e.) SPICE Simulation

Circuit used to simulate the operation of a R S latch

Waveforms associated with the operation of a R S latch

Sequential Circuits

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2.1 RS Flip-Flop 2.1.2 RS Latch e.) SPICE Simulation i.) ”When” Analysis Waveform analysis reveals that the output transitions are controlled by signals applied to the inputs ~R and ~S – times t1 – t5. .

ii.) ”How” Analysis Waveform analysis reveals that: : S =1; _ interval t1 – t2 R =0 _ interval t2 – t3 S =1; R =1 _ interval t3 – t4 S =0; R =1 R =1 _ interval t4 – t5 S =1;

Q=0 Q=0 Q=1 Q=1

Q =1; Q =1; Q =0; Q =0.

Note: The results presented confirm the transition table associated with latch operation The latch does not make a distinction between "when“ and "how”

Sequential Circuits

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2.1 RS Flip-Flop 2.1.3 Gated RS Latch a.) Symbol

Gated RS Latch ANSI standard

Gated RS Latch DIN standard

b.) Notation R, S QQ EN

Data input Output Enable

Sequential Circuits

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2.1 RS Flip-Flop 2.1.3 Gated RS Latch c.) Circuit Diagram

Gated RS Latch - circuit diagram

Sequential Circuits

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2.1 RS Flip-Flop 2.1.3 Gated RS Latch d.) Operation

Inputs

Next State

Comments

EN

Sn

Rn

Qn+1

0

X

X

Qn

Hold state

1

0

0

Qn

Hold state

1

1

0

1

Set

1

0

1

0

Reset

1

1

1

Qn+1= Q n+1=0

Not allowed

Sequential Circuits

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2.1 RS Flip-Flop 2.1.3 Gated RS Latch e.) SPICE Simulation

•“When" Analysis: Waveform analysis reveals that the output transitions occur if EN = logical "1" (the interval t1 - t2). In other words, transitions occur on the level of gate pulse. • “How" Analysis: Waveform analysis reveals that the output transitions are controlled by signals applied to the inputs R and S.

Sequential Circuits

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2.2 D Flip-Flop 2.2.1 D Latch 2.2.2 Gated D Latch 2.2.3 D Flip-Flop

Sequential Circuits

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2.2 D Flip-Flop 2.2.1 D Latch a.) Symbol

D Latch ANSI standard

D Latch DIN standard

b.) Notation D Q, Q

Data inputs Outputs

Sequential Circuits

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2.2 D Flip-Flop 2.2.1 D Latch c.) Circuit diagram

d.) Operation Input Dn

Current State Qn

Next State Qn+1

Comments

0

X

0

Reset

1

X

1

Set

Sequential Circuits

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2.2 D Flip-Flop 2.2.1 D Latch e.) SPICE Simulation

„When” Analysis: Waveform analysis reveals that the output transitions are controlled by the signal applied to the D input - (see times t1, t2 and t3) „How” Analysis: Waveform analysis reveals that : interval t1 – t2 D=1

Q=1

Q =1

interval t2 – t3 D=0

Q=0

Q =0

Sequential Circuits

34

2.2 D Flip-Flop 2.2.2 Gated D Latch a.) Symbol

Gated D Latch D ANSI standard

Gated D Latch D DIN standard

b.) Notation D EN QQ

Data input. Enable. Transitions between states can occur where EN = 1 Outputs

Sequential Circuits

35

2.2 D Flip-Flop 2.2.2 Gated D Latch c.) Circuit diagram

d.) Operation Input EN 0

Dn X

Next State Qn+1 Qn

1

1

1

Set

1

0

0

Reset

Sequential Circuits

Comments Hold state

36

2.2 D Flip-Flop 2.2.2 Gated D Latch e.) SPICE Simulation

„When” Analysis: Waveform analysis reveals that the output transitions occur if EN = logical "1" (the interval t2 - t3). In other words, transitions occur on the level of the clock pulse

„How” Analysis: Waveform analysis reveals that the output transitions are controlled by the signal applied to the input D D-type latch with gate does not make a distinction between "when” and "how" (how are these transitions). Sequential Circuits

37

2.2 D Flip-Flop 2.2.3 D Flip-Flop

•D flip-flop switching on positive edge (transition "0" to "1“) •D flip-flop switching on positive edge (transition "0" to "1“)

Sequential Circuits

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2.2 D Flip-Flop 2.2.3 D Flip-Flop D flip-flop switching on positive edge (transition "0" to "1“) a.) Symbol

ANSI Standard

DIN Standard

b.) Notation D CLK QQ

Data input CLOCK Output

Sequential Circuits

39

2.2 D Flip-Flop 2.2.3 D Flip-Flop D flip-flop switching on positive edge (transition "0" to "1“) c.) Operation Inputs

Outputs

CLK ↑

D 1

Qn+1 Q n+1 1 0



0

0

0

X

Qn

Q

1

X

Qn

Q



X

Qn

Q

Comments Set

1

Reset

n

Hold state

n

Hold state

n

Hold state

Simplified transition table

Sequential Circuits

40

2.2 D Flip-Flop 2.2.3 D Flip-Flop D flip-flop switching on positive edge (transition "0" to "1“) d.) SPICE Simulation

„When” Analysis: Waveform analysis reveals that the output transitions occur on the positive edge of the clock pulse (times t1 and t2). „How” Analysis: Waveform analysis reveals that : Time t1;

D=1

Q=1 Q =0

Time t2; D=0 Q=0 Q =1 D flip-flop switching on positive edge of the clock pulse makes a clear distinction between "when” and "how“ Sequential Circuits

41

2.2 D Flip-Flop 2.2.3 D Flip-Flop D flip-flop switching on negative edge (transition "0" to "1“) a.) Symbol

ANSI Standard

DIN Standard

b.) Notatii folosite D CLK QQ

Data input CLOCK Output

Sequential Circuits

42

2.2 D Flip-Flop 2.2.3 D Flip-Flop D flip-flop switching on negative edge (transition "0" to "1“) c.) Operation

Inputs

Outputs

Comments

CLK

D

Qn+1



1

1

0

Set



0

0

1

Reset

0

X

Qn

Qn

Hold state

1

X

Qn

Qn

Hold state



X

Qn

Q

Hold state

Q n+1

n

Sequential Circuits

43

2.2 D Flip-Flop 2.2.3 D Flip-Flop D flip-flop switching on negative edge (transition "0" to "1“) d.) SPICE Simulare

„When” Analysis: Waveform analysis reveals that the output transitions occur on the negative edge of the clock pulse (times t1 and t2) „How” Analysis: Waveform analysis reveals that : Time t1; D=1 Q=1 Q =0 Time t2; D=0 Q=0 Q =1 D flip-flop switching on negative edge of the clock pulse makes a clear distinction between "when“ and "how“ Sequential Circuits

44

2.3 JK Flip-Flop Previously, RS flip-flop was presented. Analysis of this flip-flop revealed that a certain combination of inputs, namely R = S = 1 is not allowed. D flip-flop presented a possible solution to avoid this limitation. Another solution is the JK flip-flop. This type of solution implies the introduction of a new level of internal reaction. Thus, the internal structure of such a flip-flop becomes:

Inputs Jn 0 1 0 1

Next state Kn 0 0 1 1

Circuit diagram

Qn+1 Qn 1 0 Qn

Comments Hold state Set Reset Change state

Transition table

Sequential Circuits

45

2.3 JK Flip-Flop Note There are four types of JK flip-flops. Namely they are: JK flip-flop switching on positive edge of the clock pulse and RS asynchronous active inputs JK flip-flop switching on positive edge of the clock pulse and RS asynchronous active inputs JK flip-flop switching on negative edge of the clock pulse and RS asynchronous active inputs JK flip-flop switching on negative edge of the clock pulse and RS asynchronous active inputs

Sequential Circuits

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3. Registers and Counters 3.1 Registers 3.2 Counters

Sequential Circuits

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3.1 Registers a.) Definition Digital circuit consisting of several flip-flops connected so that they can perform certain operations such as storing multiple bits simultaneously (digital word), or the ability to "move" the information contained in a digital word. Observation 'Movement' of information means specific procedures such as "shift left" and “shift right"

shift left

shift right

Sequential Circuits

48

3.1 Registers b.) Classification Memory Register - group of BIST able to be write or read simultaneously. Important to note is that all four flip-flops that have the same clock signal (CLK) Register Files - groups of flip-flops, that may be addressed (read or write) by a digital word. Shift register - Bist group that have the ability to move information between different BIST existing I/O Registers - used in parallel-series or series-parallel conversion

Series-parallel conversion shift left

Series-parallel conversion shift right Sequential Circuits

Parallel-series conversion 49

3.2 Counters a.) Definition The counter is a digital circuit - consisting of several BIST - able to perform only certain well-defined sequence of states with no additional conditions for the transition between states b.) Classification The literature presents several ways of classifying according to: •The mechanism of transition between states (analysis of "when") •Asynchronous counters •Synchronous counters •Ordering of states (analysis of "how"). •decimal •binary •Gray

Sequential Circuits

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3.2 Counters b.) Classification (cont.) Depending on the mechanism of transition:

Asynchronous counters

Synchronous counters Sequential Circuits

51

3.2 Counters b.) Classification (cont.) According to states ordering there are:

•Binary counter, Gray counter, decade counter, ring counter or Johnson counter. •Up/down counter

Sequential Circuits

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3.2 Counters b.) Classification (cont.)

Binary State Decimal State QD QC QB QA 0 0 0 0 0 1 0 0 0 1 2 0 0 1 0 3 0 0 1 1 4 0 1 0 0 5 0 1 0 1 6 0 1 1 0 7 0 1 1 1 8 1 0 0 0 9 1 0 0 1 10 1 0 1 0 11 1 0 1 1 12 1 1 0 0 13 1 1 0 1 14 1 1 1 0 15 1 1 1 1

Binary counter Sequential Circuits

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3.2 Counters b.) Classification (cont.)

Graph associated with the operation of the four-bit binary counter counting upwards

Graph associated with the operation of the four-bit binary counter counting downwards

Sequential Circuits

54

3.2 Counters b.) Classification (cont.) Gray Counter Stare zecimal 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

QD 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1

Stare binar QC QB 0 0 0 0 0 1 0 1 1 1 1 1 1 0 1 0 1 0 1 0 1 1 1 1 0 1 0 1 0 0 0 0

QA 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0

Gray Counter Sequential Circuits

55

3.2 Counters b.) Classification (cont.) Gray Counter

Graph associated with the operation of Gray Counter

Sequential Circuits

56

3.2 Counters b.) Classification (cont.) Decade counter Stare zecimal QD 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 1 9 1

Stare binar QC QB 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 0 0 0 0

Sequential Circuits

QA 0 1 0 1 0 1 0 1 0 1

57

3.2 Counters b.) Classification (cont.) Decade counter

Graph associated with the operation of four bit decimal counter counting upwards

Sequential Circuits

Graph associated with the operation of four bit decimal counter counting downwards

58

3.2 Counters b.) Classification (cont.) Ring counter

Binary (state) Decimal (state) QD QC QB QA 0 0 0 0 1 1 0 0 1 0 2 0 1 0 0 3 1 0 0 0

Sequential Circuits

59

3.2 Counters b.) Classification (cont.) Ring counter

Graph associated with the ring counter, upwards counting

Sequential Circuits

60

3.2 Counters b.) Classification (cont.) Jhonson Counter

Decimal (state) 0 1 2 3 4 5 6 7

QD 0 0 0 0 1 1 1 1

Binary (state) QC QB 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0

Sequential Circuits

QA 0 1 1 1 1 0 0 0

61

3.2 Counters b.) Classification (cont.) Numărătorul de tip Jhonson

Graph associated with Jhonson four bit counter counting upwards

Sequential Circuits

62

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